Digital
Computer
Electronics
Third Edition
Albert Paul Malvino, Ph.D.
Jerald A. Brown
GL£NCOE
McGraw-Hill
New York, New York Columbus, Ohio Woodland Hills, California Peoria, Illinois
This textbook was prepared with the assistance of Publishing Advisory Service.
LSI circuit photo: Manfred Kage/Peter Arnold Inc.
To my wife, Joanna, who encourages me to write.
And to my daughters, Joanna, Antonia, Lucinda,
Patricia, and Miriam, who keep me young.
—A.P.M.
. . . to my wife Vickie
dearest friend
fellow adventurer
love of my life
—J.A.B.
Library of Congress Cataloging-in-Publication Data
Malvino, Albert Paul.
Digital computer electronics / Albert Paul Malvino, Jerald A.
Brown. — 3rd ed.
p. cm.
Includes index.
ISBN 0-02-800594-5 (hardcover)
1. Electronic digital computers. 2. Microcomputers. 3. Intel
8085 (Microprocessor) I. Brown, Jerald A. II. Title.
TK7888.3.M337 1993
621.39'16—dc20 92-5895
CIP
Digital Computer Electronics, Third Edition
Imprint 1999
Copyright© 1993,1983 by Glencoe/McGraw-Hill. All rights reserved. Copyright© 1983, 1977 by
McGraw-Hill, Inc. All rights reserved. Printed in the United States of America. Except as
permitted under the United States Copyright Act, no part of this publication may be reproduced
or distributed in any form or by any means, or stored in a database or retrieval system, without
prior written permission of the publisher.
ISBN 0-02-800594-5
Printed in the United States of America.
4567891011 12 004/043 03 02 01 00 99
Contents
PREFACE vi
PART I
Digital Principles 1
CHAPTER 1. NUMBER SYSTEMS AND
CODES 1
1-1. Decimal Odometer 1-2. Binary Odometer
1-3. Number Codes 1-4. Why Binary Numbers Are
Used 1-5. Binary-to-Decimal Conversion
1-6. Microprocessors 1-7. Decimal-to-Binary
Conversion 1-8. Hexadecimal Numbers
1-9. Hexadecimal-Binary Conversions
1-10. Hexadecimal-to-Decimal Conversion
1-11. Decimal-to-Hexadecimal Conversion
1- 12. BCD Numbers 1-13. The ASCII Code
CHAPTER 2. GATES 19
2- 1. Inverters 2-2. or Gates 2-3. and Gates
2- 4. Boolean Algebra
CHAPTER 3. MORE LOGIC GATES 32
3- 1. nor Gates 3-2. De Morgan’s First Theorem
3-3. nand Gates 3-4. De Morgan’s Second Theorem
3-5. exclusive-or Gates 3-6. The Controlled
Inverter 3-7. exclusive-nor Gates
CHAPTER 4. TTL CIRCUITS 48
4-1. Digital Integrated Circuits 4-2. 7400 Devices
4-3. TTL Characteristics 4-4. TTL Overview
4-5. and-or-invert Gates 4-6. Open-Collector Gates
4-7. Multiplexers
CHAPTER 5. BOOLEAN ALGEBRA AND
KARNAUGH MAPS 64
5-1. Boolean Relations 5-2. Sum-of-Products Method
5-3. Algebraic Simplification 5-4. Karnaugh Maps
5-5. Pairs, Quads, and Octets 5-6. Karnaugh
Simplifications 5-7. Don’t-Care Conditions
CHAPTER 6. ARITHMETIC-LOGIC UNITS
79
6-1. Binary Addition 6-2. Binary Subtraction
6- 3. Half Adders 6-4. Full Adders 6-5. Binary
Adders 6-6. Signed Binary Numbers 6-7. 2’s
Complement 6-8. 2’s-Complement Adder-Subtracter
CHAPTER 7. FLIP-FLOPS 90
7- 1. /?,£ Latches 7-2. Level Clocking 7-3. D Latches
7- 4. Edge-Triggered D Flip-Flops 7-5. Edge-Triggered
JK Flip-Flops 7-6. JK Master-Slave Flip-Flop
CHAPTER 8. REGISTERS AND
COUNTERS 106
8- 1. Buffer Registers 8-2. Shift Registers
8-3. Controlled Shift Registers 8-4. Ripple Counters
8-5. Synchronous Counters 8-6. Ring Counters
8-7. Other Counters 8-8. Three-State Registers
8- 9. Bus-Organized Computers
CHAPTER 9. MEMORIES 130
9- 1. ROMs 9-2. PROMs and EPROMs 9-3. RAMs
9-4. A Small TTL Memory 9-5. Hexadecimal
Addresses
PART 2
SAP (Simple-as-Possible)
Computers 140
CHAPTER 10. SAP-1 140
10-1. Architecture 10-2. Instruction Set
10-3. Programming SAP-1 10-4. Fetch Cycle
10-5. Execution Cycle 10-6. The SAP-1
Microprogram 10-7. The SAP-1 Schematic Diagram
10- 8. Microprogramming
CHAPTER 11. SAP-2 173
11- 1. Bidirectional Registers 11-2. Architecture
11-3. Memory-Reference Instructions 11-4. Register
Instructions 11-5. Jump and Call Instructions
11-6. Logic Instructions 11-7. Other Instructions
11-8. SAP-2 Summary
• • •
ill
CHAPTER 12. SAP-3 195
12-1. Programming Model 12-2. MOV and MVI
12-3. Arithmetic Instructions 12-4. Increments,
Decrements, and Rotates 12-5. Logic Instructions
12-6. Arithmetic and Logic Immediates 12-7. Jump
Instructions 12-8. Extended-Register Instructions
12-9. Indirect Instructions 12-10. Stack Instructions
PART 3
Programming Popular
Microprocessors 213
CHAPTER 13. INTRODUCTION TO
MICROPROCESSORS 213
13-1. Computer Hardware
13-2. Definition of a Microprocessor
13-3. Some Common Uses for Microprocessors
13-4. Microprocessors Featured in This Text
13- 5. Access to Microprocessors
CHAPTER 14. PROGRAMMING AND
LANGUAGES 216
14- 1. Relationship between Electronics and Programming
14-2. Programming 14-3. Fundamental Premise
14-4. Flowcharts 14-5. Programming Languages
14- 6. Assembly Language 14-7. Worksheets
CHAPTER 15. SYSTEM OVERVIEW 224
New Concepts 15-1. Computer Architecture
15- 2. Microprocessor Architecture
Specific Microprocessor Families
15-3. 6502 Family 15-4. 6800/6808 Family
15- 5. 8080/8085/Z80 Family 15-6. 8086/8088 Family
CHAPTER 16. DATA TRANSFER
INSTRUCTIONS 240
New Concepts 16-1. CPU Control Instructions
16- 2. Data Transfer Instructions
Specific Microprocessor Families
16-3. 6502 Family 16-4. 6800/6808 Family
16- 5. 8080/8085/Z80 Family 16-6. 8086/8088 Family
CHAPTER 17. ADDRESSING MODES—I 263
New' Concepts 17-1. What Is an Addressing Mode?
17- 2. The Paging Concept
17-3. Basic Addressing Modes
Specific Microprocessor Families 17-4. 6502 Family
17-5. 6800/6808 Family 17-6. 8080/8085/Z80 Family
17-7. 8086/8088 Family
CHAPTER 18. ARITHMETIC AND FLAGS
270
New Concepts 18-1. Microprocessors and Numbers
18-2. Arithmetic Instructions 18-3. Flag Instructions
Specific Microprocessor Families 18.4 6502 Family
18-5. 6800/6808 Family 18-6. 8080/8085/Z80 Family
18- 7. 8086/8088 Family
CHAPTER 19. LOGICAL INSTRUCTIONS
305
New Concepts 19-1. The and Instruction
19- 2. The OR Instruction
19-3. The exclusiveor (EOR, xor) Instruction
19-4. The not Instruction
19-5. The neg (NEGate) Instruction
Specific Microprocessor Families 19-6. 6502 Family
19-7. 6800/6808 Family 19-8. 8080/8085/Z80 Family
19- 9. 8086/8088 Family
CHAPTER 20. SHIFT AND ROTATE
INSTRUCTIONS 319
New Concepts 20-1. Rotating 20-2. Shifting
20- 3. An Example Specific Microprocessor Families
20-4. 6502 Family 20-5. 6800/6808 Family
20- 6. 8080/8085/Z80 Family 20-7. 8086/8088 Family
CHAPTER 21. ADDRESSING MODES—II 329
New Concepts 21-1. Advanced Addressing Modes
Specific Microprocessor Families 21-2. 6502 Family
21- 3. 6800/6808 Family 21-4. 8080/8085/Z80 Family
21- 5. 8086/8088 Family
CHAPTER 22. BRANCHING AND LOOPS 342
New Concepts 22-1. Unconditional Jumps
22- 2. Conditional Branching
22-3. Compare and Test Instructions
22-4. Increment and Decrement Instructions
22-5. Nested Loops
Specific Microprocessor Families 22-6. 6502 Family
22-7. 6800/6808 Family 22-8. 8080/8085/Z80 Family
22- 9. 8086/8088 Family
CHAPTER 23. SUBROUTINE AND STACK
INSTRUCTIONS 363
New 7 Concepts 23-1. Stack and Stack Pointer
23- 2. Branching versus Subroutines
23-3. How Do Subroutines Return?
23-4. Pushing and Popping Registers
Specific Microprocessor Families 23-5. 6502 Family
23- 6. 6800/6808 Family 23-7. 8080/8085/Z80 Family
24- 8. 8086/8088 Family
tV Contents
PART 4
Microprocessor Instruction
Set Tables 379
A.
Expanded Table of 8085/8080 and Z80 (8080 Subset)
Instructions Listed by Category 381
Mini Table of 8085/8080 and Z80 (8080 Subset)
Instructions Listed by Category 410
Condensed Table of 8085/8080 and Z80 (8080)
Instructions Listed by Category 415
Condensed Table of 8085/8080 and Z80 (8080 Subset)
Instructions Listed by Op Code 417
Condensed Table of 8085/8080 and Z80 (8080 Subset)
Instructions Listed Alphabetically by 8085/8080
Mnemonic 419
Condensed Table of 8085/8080 and Z80 (8080 Subset)
Instructions Listed Alphabetically by Z80 Mnemonic
421
B.
Expanded Table of 6800 Instructions Listed by Category
422
Short Table of 6800 Instructions Listed Alphabetically
434
Short Table of 6800 Instructions Listed by Category
437
Condensed Table of 6800 Instructions Listed by Category
441
Condensed Table of 6800 Instructions Listed
Alphabetically 443
Condensed Table of 6800 Instructions Listed by Op Code
444
C.
Expanded Table of 8086/8088 Instructions Listed by
Category 445
Condensed Table of 8086/8088 Instructions Listed by
Category 465
Condensed Table of 8086/8088 Instructions Listed
Alphabetically 469
D.
Expanded Table of 6502 Instructions Listed by Category
471
Short Table of 6502 Instructions Listed by Category
478
Condensed Table of 6502 Instructions Listed by Category
480
Condensed Table of 6502 Instructions Listed
Alphabetically 481
Condensed Table of 6502 Instructions Listed by Op Code
482
APPENDIXES 485
L The Analog Interface 2. Binary-Hexadecimal-
Decimal Equivalents 3. 7400 Series TTL
4. Pinouts and Function Tables 5. SAP-1 Parts List
6. 8085 Instructions 7. Memory Locations: Powers of 2
8. Memory Locations: 16K and 8K Intervals
9. Memory Locations: 4K Intervals 10. Memory
Locations: 2K Intervals 11. Memory Locations: IK
Intervals 12. Programming Models
ANSWERS TO ODD-NUMBERED PROBLEMS
513
INDEX 519
Contents V
Preface
Textbooks on microprocessors are sometimes hard to un¬
derstand. This text attempts to present the various aspects
of microprocessors in ways that are understandable and
interesting. The only prerequisite to using this textbook is
an understanding of diodes and transistors.
A unique aspect of this text is its wide range. Whether
you are interested in the student-constructed SAP (simple -
as-possible) microprocessor, the 6502, the 6800/6808, the
8080/8085/Z80, or the 8086/8088, this textbook can meet
your needs.
The text is divided into four parts. These parts can be
used in different ways to meet the needs of a wide variety
of students, classrooms, and instructors.
Part 1, Digital Principles, is composed of Chapters 1 to
9. Featured topics include number systems, gates, boolean
algebra, flip-flops, registers, counters, and memory. This
information prepares the student for the microprocessor
sections which follow.
Part 2, which consists of Chapters 10 to 12, presents the
SAP (simple-as-possible) microprocessor. The student con¬
structs this processor using digital components. The SAP
processor contains the most common microprocessor func¬
tions. It features an instruction set which is a subset of that
of the Intel 8085—leading naturally to a study of that
microprocessor.
Part 3, Programming Popular Microprocessors (Chapters
13 to 23), simultaneously treats the MOS/Rockwell 6502,
the Motorola 6800/6808, the Intel 8080/8085 and Zilog
Z80, and the 16-bit Intel 8086/8088. Each chapter is divided
into two sections. The first section presents new concepts;
second section applies the new concepts to each micropro¬
cessor family. Discussion, programming examples, and
problems are provided. The potential for comparative study
is excellent.
This part of the text takes a strong programming approach
to the study of microprocessors. Study is centered around
the microprocessor’s instruction set and programming model.
The 8-bit examples and homework problems can be per¬
formed by using either hand assembly or cross-assemblers.
The 16-bit 8086/8088 examples and problems can be per¬
formed by using either an assembler or the DOS DEBUG
utility.
Part 4 is devoted to the presentation of the instruction
sets of each microprocessor family in table form. Several
tables are provided for each microprocessor family, per¬
mitting instructions to be looked up alphabetically, by op
code, or by functional category, with varying levels of
detail. The same functional categories are correspondingly
used in the chapters in Part 3. This coordination between
parts makes the learning process easier and more enjoyable.
Additional reference tables are provided in the appen¬
dixes. Answers to odd-numbered problems for Chapters 1
to 16 follow the appendixes.
A correlated laboratory manual, Experiments for Digital
Computer Electronics by Michael A. Miller, is available
for use with this textbook. It contains experiments for every
part of the text. It also includes programming problems for
each of the featured microprocessors.
A teacher’s manual is available which contains answers
to all of the problems and programs for every micropro¬
cessor. In addition, a diskette (MS-DOS 360K 5!/4-inch
diskette) containing cross-assemblers is included in the
teacher’s manual.
Special thanks to Brian Mackin for being such a patient
and supportive editor. To Olive Collen for her editorial
work. To Michael Miller for his work on the lab manual.
And to Thomas Anderson of Speech Technologies Inc. for
the use of his cross-assemblers. Thanks also to reviewers
Lawrence Fryda, Illinois State University; Malachi Mc¬
Ginnis, ITT Technical Institute, Garland Texas; and Ben¬
jamin Suntag.
Albert Paul Malvino
Jerald A. Brown
A man of true science uses but few hard words ,
and those only when none other will answer his purpose;
whereas the smatterer in science thinks that
by mouthing hard words he understands hard things .
Herman Melville
PART 1
DIGITAL PRINCIPLES
Number Systems
and Codes
Modem computers don’t work with decimal numbers.
Instead, they process binary numbers, groups of Os and Is.
Why binary numbers? Because electronic devices are most
reliable when designed for two-state (binary) operation.
This chapter discusses binary numbers and other concepts
needed to understand computer operation.
1-1 DECIMAL ODOMETER
Rene Descartes (1596-1650) said that the way to learn a
new subject is to go from the known to the unknown, from
the simple to the complex. Let’s try it.
The Known
Everyone has seen an odometer (miles indicator) in action.
When a car is new, its odometer starts with
00000
After 1 mile the reading becomes
00001
Successive miles produce 00002, 00003, and so on, up to
00009
A familiar thing happens at the end of the tenth mile.
When the units wheel turns from 9 back to 0, a tab on this
wheel forces the tens wheel to advance by 1. This is why
the numbers change to
00010
Reset-and-Carry
The units wheel has reset to 0 and sent a carry to the tens
wheel. Let’s call this familiar action reset-and-carry .
The other wheels also reset and carry. After 999 miles
the odometer shows
00999
What does the next mile do? The units wheel resets and
carries, the tens wheel resets and carries, the hundreds
wheel resets and carries, and the thousands wheel advances
by 1, to get
01000
Digits and Strings
The numbers on each odometer wheel are called digits.
The decimal number system uses ten digits, 0 through 9.
In a decimal odometer, each time the units wheel runs out
of digits, it resets to 0 and sends a carry to the tens wheel.
When the tens wheel runs out of digits, it resets to 0 and
sends a carry to the hundreds wheel. And so on with the
remaining wheels.
One more point. A string is a group of characters (either
letters or digits) written one after another. For instance,
734 is a string of 7, 3, and 4. Similarly, 2C8A is a string
of 2, C, 8, and A.
1-2 BINARY ODOMETER
Binary means two. The binary number system uses only
two digits, 0 and 1. All other digits (2 through 9) are
thrown away. In other words, binary numbers are strings
of 0s and Is.
An Unusual Odometer
Visualize an odometer whose wheels have only two digits,
0 and 1. When each wheel turns, it displays 0, then 1, then
1
back to 0, and the cycle repeats. Because each wheel has
only two digits, we call this device a binary odometer.
In a car a binary odometer starts with
0000 (zero)
After 1 mile, it indicates
0001 (one)
The next mile forces the units wheel to reset and carry; so
the numbers change to
0010 (two)
The third mile results in
0011 (three)
What happens after 4 miles? The units wheel resets and
carries, the second wheel resets and carries, and the third
wheel advances by 1. This gives
0100 (four)
Successive miles produce
0101 (five)
0110 (six)
0111 (seven)
After 8 miles, the units wheel resets and carries, the
second wheel resets and carries, the third wheel resets and
carries, and the fourth wheel advances by 1. The result is
1000 (eight)
The ninth mile gives
1001 (nine)
and the tenth mile produces
1010 (ten)
(Try working out a few more readings on your own.)
You should have the idea by now. Each mile advances
the units wheel by 1. Whenever the units wheel runs out
of digits, it resets and carries. Whenever the second wheel
runs out of digits, it resets and carries. And so for the other
wheels.
Binary Numbers
A binary odometer displays binary numbers, strings of 0s
and Is. The number 0001 stands for 1, 0010 for 2, 0011
for 3, and so forth. Binary numbers are long when large
amounts are involved. For instance, 101010 represents
decimal 42. As another example, 111100001111 stands for
decimal 3,855.
Computer circuits are like binary odometers; they count
and work with binary numbers. Therefore, you have to
learn to count with binary numbers, to convert them to
decimal numbers, and to do binary arithmetic. Then you
will be ready to understand how computers operate.
A final point. When a decimal odometer shows 0036,
we can drop the leading 0s and read the number as 36.
Similarly, when a binary odometer indicates 0011, we can
drop the leading 0s and read the number as 11. With the
leading 0s omitted, the binary numbers are 0, 1, 10, 11,
100, 101, and so on. To avoid confusion with decimal
numbers, read the binary numbers like this: zero, one, one-
zero, one-one, one-zero-zero, one-zero-one, etc.
1-3 NUMBER CODES
People used to count with pebbles. The numbers 1, 2, 3
looked like • , •••. Larger numbers were worse:
seven appeared as •••••••.
Codes
From the earliest times, people have been creating codes
that allow us to think, calculate, and communicate. The
decimal numbers are an example of a code (see Table
1-1). It’s an old idea now, but at the time it was as
revolutionary; 1 stands for •, 2 for ##, 3 for ###,
and so forth.
Table 1-1 also shows the binary code. 1 stands for #, 10
for ##, 11 for ###, and so on. A binary number and a
decimal number are equivalent if each represents the same
amount of pebbles. Binary 10 and decimal 2 are equivalent
because each represents ##. Binary 101 and decimal 5 are
equivalent because each stands for #####.
TABLE 1-1. NUMBER CODES
Decimal
Pebbles
Binary
0
None
0
1
•
1
2
••
10
3
•••
11
4
••••
100
5
•••••
101
6
••••••
110
7
•••••••
111
8
1000
9
1001
2 Digital Computer Electronics
Equivalence is the common ground between us and
computers; it tells us when we’re talking about the same
thing. If a computer comes up with a binary answer of 101,
equivalence means that the decimal answer is 5. As a start
to understanding computers, memorize the binary-decimal
equivalences of Table 1-1.
EXAMPLE 1-1
Figure 1-1 a shows four light-emitting diodes (LEDs). A
dark circle means that the LED is off; a light circle means
it’s on. To read the display, use this code:
©o o
(a)
(b)
Fig. 1-1 LED display of binary numbers.
TABLE 1-2. BINARY-TO-DECIMAL
EQUIVALENCES
Decimal
Binary
Decimal
Binary
0
0000
8
1000
1
0001
9
1001
2
0010
10
1010
3
0011
11
1011
4
0100
12
1100
5
0101
13
1101
6
0110
14
1110
7
0111
15
mi
Therefore, you should memorize the equivalences of Table
1 - 2 .
LED Binary
Off 0
On 1
What binary number does Fig. 1-la indicate? Fig. 1-16?
SOLUTION
Figure 1-la shows off-off-on-on. This stands for binary
0011, equivalent to decimal 3.
Figure 1-16 is off-on-off-on, decoded as binary 0101 and
equivalent to decimal 5.
EXAMPLE 1-2
A binary odometer has four wheels. What are the successive
binary numbers?
SOLUTION
As previously discussed, the first eight binary numbers are
0000, 0001, 0010, 0011,0100, 0101, 0110, and 0111. On
the next count, the three wheels on the right reset and carry;
the fourth wheel advances by one. So the next eight numbers
are 1000, 1001, 1010, 1011, 1100, 1101, 1110, and 1111.
The final reading of 1111 is equivalent to decimal 15. The
next mile resets all wheels to 0, and the cycle repeats.
Being able to count in binary from 0000 to 1111 is
essential for understanding the operation of computers.
1-4 WHY BINARY NUMBERS
ARE USED
The word “computer” is misleading because it suggests a
machine that can solve only numerical problems. But a
computer is more than an automatic adding machine. It can
play games, translate languages, draw pictures, and so on.
To suggest this broad range of application, a computer is
often referred to as a data processor.
Program and Data
Data means names, numbers, facts, anything needed to
work out a problem. Data goes into a computer, where it
is processed or manipulated to get new information. Before
it goes into a computer, however, the data must be coded
in binary form. The reason was given earlier: a computer’s
circuits can respond only to binary numbers.
Besides the data, someone has to work out a program ,
a list of instructions telling the computer what to do. These
instructions spell out each and every step in the data
processing. Like the data, the program must be coded in
binary form before it goes into the computer.
So the two things we must input to a computer are the
program and the data. These are stored inside the computer
before the processing begins. Once the computer run starts,
each instruction is executed and the data is processed.
Hardware and Software
The electronic, magnetic, and mechanical devices of a
computer are known as hardware . Programs are called
software . Without software, a computer is a pile of ‘ ‘dumb”
metal.
Chapter 1 Number Systems and Codes 3
An analogy may help. A phonograph is like hardware
and records are like software. The phonograph is useless
without records. Furthermore, the music you get depends
on the record you play. A similar idea applies to computers.
A computer is the hardware and programs are the software.
The computer is useless without programs. The program
stored in the computer determines what the computer will
do; change the program and the computer processes the
data in a different way.
Transistors
Computers use integrated circuits (ICs) with thousands of
transistors, either bipolar or MOS. The parameters (p dc ,
Ico, g m > etc.) can var y more than 50 percent with temperature
change and from one transistor to the next. Yet these
computer ICs work remarkably well despite the transistor
variations. How is it possible?
The answer is two-state design, using only two points
on the load line of each transistor. For instance, the common
two-state design is the cutoff-saturation approach; each
transistor is forced to operate at either cutoff or saturation.
When a transistor is cut off or saturated, parameter variations
have almost no effect. Because of this, it’s possible to
design reliable two-state circuits that are almost independent
of temperature change and transistor variations.
Transistor Register
Here’s an example of two-state design. Figure 1-2 shows
a transistor register. (A register is a string of devices that
store data.) The transistors on the left are cut off because
the input base voltages are 0 V. The dark shading symbolizes
the cutoff condition. The two transistors on the right have
base drives of 5 V.
The transistors operate at either saturation or cutoff. A
base voltage of 0 V forces each transistor to cut off, while
a base voltage of 5 V drives it into saturation. Because of
this two-state action, each transistor stays in a given state
until the base voltage switches it to the opposite state.
Another Code
Two-state operation is universal in digital electronics. By
deliberate design, all input and output voltages are either
low or high. Here’s how binary numbers come in: low
voltage represents binary 0, and high voltage stands for
binary 1. In other words, we use this code:
Voltage
Binary
Low
0
High
1
For instance, the base voltages of Fig. 1-2 are low-low-
high-high, or binary 0011. The collector voltages are high-
high-low-low, orbinary 1100. By changing the base voltages
we can store any binary number from 0000 to 1111 (decimal
0 to 15).
Bit
Bit is an abbreviation for binary digit. A binary number
like 1100 has 4 bits; 110011 has 6 bits; and 11001100 has
8 bits. Figure 1-2 is a 4-bit register. To store larger binary
numbers, it needs more transistors. Add two transistors and
you get a 6-bit register. With four more transistors, you’d
have an 8-bit register.
Nonsaturated Circuits
Don’t get the idea that all two-state circuits switch between
cutoff and saturation. When a bipolar transistor is heavily
saturated, extra carriers are stored in the base region. If the
base voltage suddenly switches from high to low, the
transistor cannot come out of saturation until these extra
carriers have a chance to leave the base region. The time
it takes for these carriers to leave is called the saturation
delay time t d . Typically, t d is in nanoseconds.
In most applications the saturation delay time is too short
to matter. But some applications require the fastest possible
Fig. 1-2 Transistor register.
4 Digital Computer Electronics
switching time. To get this maximum speed, designers have
come up with circuits that switch from cutoff (or near
cutoff) to a higher point on the load line (but short of
saturation). These nonsaturated circuits rely on clamping
diodes or heavy negative feedback to overcome transistor
variations.
Remember this: whether saturated or nonsaturated circuits
are used, the transistors switch between distinct points on
the load line. This means that all input and output voltages
are easily recognized as low or high, binary 0 or binary 1.
(a)
Fig. 1-3 Core register.
Magnetic Cores
Early digital computers used magnetic cores to store data.
Figure l-3a shows a 4-bit core register. With the right-
hand rule, you can see that conventional current into a wire
produces a clockwise flux; reversing the current gives a
counterclockwise flux. (The same result is obtained if
electron-flow is assumed and the left-hand rule is used.)
The cores have rectangular hysteresis loops; this means
that flux remains in a core even though the magnetizing
current is removed (see Fig. 1-3 b). This is why a core
register can store binary data indefinitely. For instance,
let’s use the following code:
Flux
Binary
Counterclockwise
0
Clockwise
1
Other Two-State Examples
The simplest example of a two-state device is the on-off
switch. When this switch is closed, it represents binary 1;
when it’s open, it stands for binary 0.
Punched cards are another example of the two-state
concept. A hole in a card stands for binary 1, the absence
of a hole for binary 0. Using a prearranged code, a card-
punch machine with a keyboard can produce a stack of
cards containing the program and data needed to run a
computer.
Magnetic tape can also store binary numbers. Tape
recorders magnetize some points on the tape (binary 1),
while leaving other points unmagnetized (binary 0). By a
prearranged code, a row of points represents either a coded
instruction or data. In this way, a reel of tape can store
thousands of binary instructions and data for later use in a
computer.
Even the lights on the control panel of a large computer
are binary; a light that’s on stands for binary 1, and one
that’s off stands for binary 0. In a 16-bit computer, for
instance, a row of 16 lights allows the operator to see the
binary contents in different computer registers. The operator
can then monitor the overall operation and, when necessary,
troubleshoot.
In summary, switches, transistors, cores, cards, tape,
lights, and almost all other devices used with computers
are based on two-state operation. This is why we are forced
to use binary numbers when analyzing computer action.
EXAMPLE 13
Figure 1-4 shows a strip of magnetic tape. The black circles
are magnetized points and the white circles unmagnetized
points. What binary number does each horizontal row
represent?
Then, the core register of Fig. 1-3 b stores binary 1001,
equivalent to decimal 9. By changing the magnetizing
currents in Fig. 1-3 a we can change the stored data.
To store larger binary numbers, add more cores. Two
cores added to Fig. 1-3 a result in a 6-bit register; four more
cores give an 8-bit register.
The memory is one of the main parts of a computer.
Some memories contain thousands of core registers. These
registers store the program and data needed to run the
computer.
Fig. 1-4 Binary numbers on magnetic tape.
SOLUTION
The tape stores these binary numbers:
Row 1
00001111
Row 5
11100110
Row 2
10000110
Row 6
01001001
Row 3
10110111
Row 7
11001101
Row 4
00110001
Chapter 1 Number Systems and Codes 5
(Note: these binary numbers may represent either coded
instructions or data.)
A string of 8 bits is called a byte. In this example, the
magnetic tape stores 7 bytes. The first byte (row 1) is
00001 111. The second byte (row 2) is 10000110. The third
byte is 10110111. And so on.
A byte is the basic unit of data in computers. Most
computers process data in strings of 8 bits or some multiple
(16, 24, 32, and so on). Likewise, the memory stores data
in strings of 8 bits or some multiple of 8 bits.
(1 x 2 4 ) + (1 X 2 3 ) + (0 X 2 2 ) + (0 X V)
+ (1 x 2°) = 16 + 8 + 0 + 0 + 1 = 25
Binary 11001 is therefore equivalent to decimal 25.
As another example, the byte 11001100 converts to
decimal as follows:
(1 x 2 7 ) + (1 x 2 6 ) T (0 x 2 5 ) + (0 x 2 4 )
+ (1 X 2 3 ) + (1 X 2 2 ) + (0 x V) + (0 X 2°)
= 128 + 64 + 0 + 0 + 8 + 4 + 0 + 0 = 204
1-5 BINARY-TO-DECIMAL
CONVERSION
You already know how to count to 15 using binary numbers.
The next thing to learn is how to convert larger binary
numbers to their decimal equivalents.
5
7
0
3
4
1
1
0
0
1
10 4
10 3
10 2
10 1
10 °
2 4
2 3
2 2
2 1
2 °
(a) (b)
Fig. 1-5 (a) Decimal weights; (b) binary weights.
Decimal Weights
The decimal number system is an example of positional
notation; each digit position has a weight or value. With
decimal numbers the weights are units, tens, hundreds,
thousands, and so on. The sum of all digits multiplied by
their weights gives the total amount being represented.
For instance, Fig. 1 -5a illustrates a decimal odometer.
Below each digit is its weight. The digit on the right has a
weight of 10° (units), the second digit has a weight of 10'
(tens), the third digit a weight of 10 2 (hundreds), and so
forth. The sum of all units multiplied by their weights is
So, binary 11001100 is equivalent to decimal 204.
Fast and Easy Conversion
Here’s a streamlined way to convert a binary number to its
decimal equivalent:
1. Write the binary number.
2. Write the weights 1, 2, 4, 8, ... , under the binary
digits.
3. Cross out any weight under a 0.
4. Add the remaining weights.
For instance, binary 1101 converts to decimal as follows:
1 . 1 1 0 1
2. 8 4 2 1
3. 8 4 0 1
4. 8 + 4 + 0+1 = 13
(Write binary number)
(Write weights)
(Cross out weights)
(Add weights)
You can compress the steps even further:
110 1 (Step 1)
8 4 t 1 —> 13 (Steps 2 to 4)
As another example, here’s the conversion of binary
1110101 in compressed form:
(5 x 10 4 ) + (7 x 10 3 ) + (0 X 10 2 ) + (3 x 10 1 )
+ (4x 10°) = 50,000 + 7000 + 0 + 30 + 4
= 57,034
Binary Weights
Positional notation is also used with binary numbers because
each digit position has a weight. Since only two digits are
used, the weights are powers of 2 instead of 10. As shown
in the binary odometer of Fig. 1-5 b, these weights are 2°
(units), 2 1 (twos), 2 2 (fours), 2 3 (eights), and 2 4 (sixteens).
If longer binary numbers are involved, the weights continue
in ascending powers of 2.
The decimal equivalent of a binary number equals the
sum of all binary digits multiplied by their weights. For
instance, the binary reading of Fig. 1-5 b has a decimal
equivalent of
1 1 10 10 1
64 32 16 0 4 % 1 —^ 117
Base or Radix
The base or radix of a number system equals the number
of digits it has. Decimal numbers have a base of 10 because
digits 0 through 9 are used. Binary numbers have a base
of 2 because only the digits 0 and 1 are used. (In terms of
an odometer, the base or radix is the number of digits on
each wheel.)
A subscript attached to a number indicates the base of
the number. 100 2 means binary 100. On the other hand,
100 lo stands for decimal 100. Subscripts help clarify equa¬
tions where binary and decimal numbers are mixed. For
instance, the last two examples of binary-to-decimal con¬
version can be written like this:
6 Digital Computer Electronics
1101 2 = 13 10
1110101 2 - 117,0
In this book we will use subscripts when necessary for
clarity.
1-6 MICROPROCESSORS
What is inside a computer? What is a microprocessor? What
is a microcomputer?
Computer
The five main sections of a computer are input, memory,
arithmetic and logic, control, and output. Here is a brief
description of each.
Input This consists of all the circuits needed to get
programs and data into the computer. In some computers
the input section includes a typewriter keyboard that converts
letters and numbers into strings of binary data.
Memory This stores the program and data before the
computer run begins. It also can store partial solutions
during a computer run, similar to the way we use a scratchpad
while working out a problem.
Control This is the computer’s center of gravity, analo¬
gous to the conscious part of the mind. The control section
directs the operation of all other sections. Like the conductor
of an orchestra, it tells the other sections what to do and
when to do it.
Arithmetic and logic This is the number-crunching sec¬
tion of the machine. It can also make logical decisions.
With control telling it what to do and with memory feeding
it data, the arithmetic-logic unit (ALU) grinds out answers
to number and logic problems.
Output This passes answers and other processed data to
the outside world. The output section usually includes a
video display to allow the user to see the processed data.
Microprocessor
The control section and the ALU are often combined
physically into a single unit called the central processing
unit (CPU). Furthermore, it’s convenient to combine the
input and output sections into a single unit called the input-
output (I/O) unit. In earlier computers, the CPU, memory,
and I/O unit filled an entire room.
With the advent of integrated circuits, the CPU, memory,
and I/O unit have shrunk dramatically. Nowadays the CPU
can be fabricated on a single semiconductor chip called a
microprocessor. In other words, a microprocessor is nothing
more than a CPU on a chip.
Likewise, the I/O circuits and memory can be fabricated
on chips. In this way, the computer circuits that once filled
a room now fit on a few chips.
Microcomputer
As the name implies, a microcomputer is a small computer.
More specifically, a microcomputer is a computer that uses
a microprocessor for its CPU. The typical microcomputer
has three kinds of chips: microprocessor (usually one chip),
memory (several chips), and TO (one or more chips).
If a small memory is acceptable, a manufacturer can
fabricate all computer circuits on a single chip. For instance,
the 8048 from Intel Corporation is a one-chip microcomputer
with an 8-bit CPU, 1,088 bytes of memory, and 27 I/O
lines.
Powers of 2
Microprocessor design started with 4-bit devices, then
evolved to 8- and 16-bit devices. In our later discussions
of microprocessors, powers of 2 keep coming up because
of the binary nature of computers. For this reason, you
should study Table 1-3. It lists the powers of 2 encountered
in microcomputer analysis. As shown, the abbreviation K
stands for 1,024 (approximately l,000).f Therefore, IK
means 1,024, 2K stands for 2,048, 4K for 4,096, and so
on.
Most personal microcomputers have 640K (or greater)
memories that can store 655,360 bytes (or more).
TABLE 1-3. POWERS OF 2
Powers of 2
Decimal equivalent
Abbreviation
2°
1
2 1
2
2 2
4
2 3
8
2 4
16
2 5
32
2 6
64
2 7
128
2 8
256
2 9
512
2 10
1,024
IK
2 11
2,048
2K
2 12
4,096
4K
2 13
8,192
8K
2 14
16,384
16K
2 15
32,768
32K
2 16
65,536
64K
t The abbreviations IK, 2K, and so on, became established
before K- for kilo- was in common use. Retaining the capital K
serves as a useful reminder that K only approximates 1,000.
Chapter 1 Number Systems and Codes 7
1-7 DECIMAL-TO-BINARY
CONVERSION
Next, you need to know how to convert from decimal to
binary. After you know how it’s done, you will be able to
understand how circuits can be built to convert decimal
numbers into binary numbers.
Double-Dabble
Double-dabble is a way of converting any decimal number
to its binary equivalent. It requires successive division by
2, writing down each quotient and its remainder. The
remainders are the binary equivalent of the decimal number.
The only way to understand the method is to go through
an example, step by step.
Here is how to convert decimal 13 to its binary equivalent.
Step 1. Divide 13 by 2, writing your work like this:
6 1 —> (first remainder)
2 7T3
The quotient is 6 with a remainder of 1.
Step 2. Divide 6 by 2 to get
3 0 —» (second remainder)
2 J6 1
2 Jl3
This division gives 3 with a remainder of 0.
Step 3. Again you divide by 2:
1 1 —> (third remainder)
2 J3 0
2 F6 1
2 Jl3
Here you get a quotient of 1 and a remainder of 1.
Step 4. One more division by 2 gives
Read
down
0 1
2 FT i
2 F3 0
2 F6 1
2 Fl3
In this final division, 2 does not divide into 1; therefore,
the quotient is 0 with a remainder of 1.
Whenever you arrive at a quotient of 0 with a remainder
of 1, the conversion is finished. The remainders when read
downward give the binary equivalent. In this example,
binary 1101 is equivalent to decimal 13.
Double-dabble works with any decimal number. Pro¬
gressively divide by 2, writing each quotient and its
remainder. When you reach a quotient of 0 and a remainder
of 1, you are finished; the remainders read downward are
the binary equivalent of the decimal number.
Streamlined Double-Dabble
There’s no need to keep writing down 2 before each division
because you’re always dividing by 2. From now on, here’s
how to show the conversion of decimal 13 to its binary
equivalent:
0 1
n i
Jl 0
J~6 1 w
2 FI3
EXAMPLE 1-4
Convert decimal 23 to binary.
SOLUTION
The first step in the conversion
looks like this:
11
1
2 F23
After all divisions, the finished
work looks like this:
0
1
FT
0
12
1
FT
1
m
1
2 J23
/
This says that binary 10111 is equivalent to decimal 23.
8 Digital Computer Electronics
1-8 HEXADECIMAL NUMBERS
Hexadecimal numbers are extensively used in micropro¬
cessor work. To begin with, they are much shorter than
binary numbers. This makes them easy to write and
remember. Furthermore, you can mentally convert them to
binary form whenever necessary.
An Unusual Odometer
Hexadecimal means 16. The hexadecimal number system
has a base or radix of 16. This means that it uses 16 digits
to represent all numbers. The digits are 0 through 9, and
A through F as follows: 0, 1,2, 3, 4, 5, 6, 7, 8, 9, A, B,
C, D, E, and F. Hexadecimal numbers are strings of these
digits like 8A5, 4CF7, and EC58.
An easy way to understand hexadecimal numbers is to
visualize a hexadecimal odometer. Each wheel has 16 digits
on its circumference. As it turns, it displays 0 through 9
as before. But then, instead of resetting, it goes on to
display A, B, C, D, E, and F.
The idea of reset and carry applies to a hexadecimal
odometer. When a wheel turns from F back to 0, it forces
the next higher wheel to advance by 1. In other words,
when a wheel runs out of hexadecimal digits, it resets and
carries.
If used in a car, a hexadecimal odometer would count
as follows. When the car is new, the odometer shows all
Os:
0000 (zero)
The next 9 miles produce readings of
0001 (one)
0002 (two)
0003 (three)
0004 (four)
0005 (five)
0006 (six)
0007 (seven)
0008 (eight)
0009 (nine)
The next 6 miles give
000A (ten)
000B (eleven)
000C (twelve)
000D (thirteen)
000E (fourteen)
000F (fifteen)
At this point the least significant wheel has run out of
digits. Therefore, the next mile forces a reset-and-carry to
get
0010 (sixteen)
The next 15 miles produce these readings: 0011, 0012,
0013, 0014, 0015, 0016, 0017, 0018, 0019, 001A, 001B,
001C, 001D, 001E, and 001F. Once again, the least
significant wheel has run out of digits. So, the next mile
results in a reset-and-carry:
0020 (thirty-two)
Subsequent readings are 0021, 0022, 0023, 0024, 0025,
0026, 0027, 0028, 0029, 002A, 002B, 002C, 002D, 002E,
and 002F.
You should have the idea by now. Each mile advances
the least significant wheel by 1. When this wheel runs out
of hexadecimal digits, it resets and carries. And so on for
the other wheels. For instance, if the odometer reading is
835F
the next reading is 8360. As another example, given
5FFF
the next hexadecimal number is 6000.
Equivalences
Table 1-4 shows the equivalences between hexadecimal,
binary, and decimal digits. Memorize this table. It’s essential
that you be able to convert instantly from one system to
another.
TABLE 1-4. EQUIVALENCES
Hexadecimal
Binary
Decimal
0
0000
0
1
0001
1
2
0010
2
3
0011
3
4
0100
4
5
0101
5
6
0110
6
7
0111
7
8
1000
8
9
1001
9
A
1010
10
B
1011
11
C
1100
12
D
1101
13
E
1110
14
F
mi
15
Chapter 1 Number Systems and Codes 9
1-9 HEXADECIMAL-BINARY
CONVERSIONS
After you know the equivalences of Table 1-4, you can
mentally convert any hexadecimal string to its binary
equivalent and vice versa.
Hexadecimal to Binary
To convert a hexadecimal number to a binary number,
convert each hexadecimal digit to its 4-bit equivalent, using
Table 1-4. For instance, here’s how 9AF converts to binary:
9 A F
l' "i 'i
looi ioio mi
As another example, C5E2 converts like this:
C 5 E 2
>1 >t >L
1100 0101 1110 0010
Incidentally, for easy reading it’s common practice to leave
a space between the 4-bit strings. For example, instead of
writing
C5E2 16 - 1100010111100010 2
we can write
C5E2i 6 = 1100 0101 1110 0010 2
Binary to Hexadecimal
To convert in the opposite direction, from binary to
hexadecimal, you again use Table 1-4. Here are two
examples. The byte 1000 1100 converts as follows:
1000 1100
i i
8 C
The 16-bit number 1110 1000 1101 0110 converts like this:
1110 1000 1101 0110
't >1 i' >i
E 8 D 6
In both these conversions, we start with a binary number
and wind up with the equivalent hexadecimal number.
EXAMPLE 1-5
Solve the following equation for x:
r 16 = mi mi mi nn 2
SOLUTION
This is the same as asking for the hexadecimal equivalent
of binary 1111 1111 1111 1111. Since hexadecimal F is
equivalent to 1111, x = FFFF. Therefore,
ffff 16 = mi mi nil nn 2
EXAMPLE 1-6
As mentioned earlier, the memory contains thousands of
registers (core or semiconductor) that store the program and
data needed for a computer run. These memory registers
are known as memory locations. A typical microcomputer
may have up to 65,536 memory locations, each storing 1
byte.
Suppose the first 16 memory locations contain these
bytes:
0011 1100
1100 1101
0101 0111
0010 1000
ini oooi
0010 1010
1101 0100
0100 0000
0111 0111
1100 0011
1000 0100
0010 1000
0010 0001
0011 1010
0011 1110
oooi nil
Convert these bytes to their hexadecimal equivalents.
SOLUTION
Here are the stored bytes and their hexadecimal equivalents:
Memory Contents Hex Equivalents
0011 1100 3C
1100 1101 CD
01010111 57
0010 1000 28
1111 0001 FI
10 Digital Computer Electronics
0010 1010
2A
1101 0100
D4
0100 0000
40
0111 0111
77
1100 0011
C3
1000 0100
84
0010 1000
28
0010 0001
21
0011 1010
3A
0011 1110
3E
0001 1111
IF
What’s the point of this example? When talking about
the contents of a computer memory, we can use either
binary numbers or hexadecimal numbers. For instance, we
can say that the first memory location contains 0011 1100,
or we can say that it contains 3C. Either string gives the
same information. But notice how much easier it is to say,
write, and think 3C than it is to say, write, and think 0011
1100. In other words, hexadecimal strings are much easier
for people to work with. This is why everybody working
with microprocessors uses hexadecimal notation to represent
particular bytes.
What we have just done is known as chunking , replacing
longer strings of data with shorter ones. At the first memory
location we chunk the digits 0011 1100 into 3C. At the
second memory location we chunk the digits 1100 1101
into CD, and so on.
EXAMPLE 1-7
The typical microcomputer has a typewriter keyboard that
allows you to enter programs and data; a video screen
displays answers and other information.
Suppose the video screen of a microcomputer displays
the hexadecimal contents of the first eight memory locations
as
A7
28
C3
19
5A
4D
2C
F8
What are the binary contents of the memory locations?
SOLUTION
Convert from hexadecimal to binary to get
1010 0111
0010 1000
1100 0011
0001 1001
0101 1010
0100 1101
0010 1100
mi iooo
The first memory location stores the byte 1010 0111, the
second memory location stores the byte 0010 1000, and so
on.
This example emphasizes a widespread industrial prac¬
tice. Microcomputers are programmed to display chunked
data, often hexadecimal. The user is expected to know
hexadecimal-binary conversions. In other words, a computer
manufacturer assumes that you know that A7 represents
1010 0111, 28 stands for 0010 1000, and so on.
One more point. Notice that each memory location in
this example stores 1 byte. This is typical of first-generation
microcomputers because they use 8-bit microprocessors.
1-10 HEXADECIMAL-TO-DECIMAL
CONVERSION
You often need to convert a hexadecimal number to its
decimal equivalent. This section discusses methods for
doing it.
Hexadecimal to Binary to Decimal
One way to convert from hexadecimal to decimal is the
two-step method of converting from hexadecimal to binary
and then from binary to decimal. For instance, here’s how
to convert hexadecimal 3C to its decimal equivalent.
Step 1. Convert 3C to its binary equivalent:
3 C
i i
0011 1100
Step 2. Convert 0011 1100 to its decimal equivalent:
0 0 1 1110 0
M 32 16 8 4 % /->60
Therefore, decimal 60 is equivalent to hexadecimal 3C. As
an equation,
3C 16 = 0011 1100 2 = 60 10
Positional-Notation Method
Positional notation is also used with hexadecimal numbers
because each digit position has a weight. Since 16 digits
are used, the weights are the powers of 16. As shown in
Chapter 1 Number Systems and Codes 11
□
8
E
□
16 3
16 2
16 1
Fig. 1 -6 Hexadecimal weights.
the hexadecimal odometer of Fig. 1-6, the weights are 16°,
16 1 , 16 2 , and 16 3 . If longer hexadecimal numbers are
involved, the weights continue in ascending powers of 16.
The decimal equivalent of a hexadecimal string equals
the sum of all hexadecimal digits multiplied by their weights.
(In processing hexadecimal digits A through F, use 10
through 15.) For instance, the hexadecimal reading of Fig.
1-6 has a decimal equivalent of
(F X 16 3 ) + (8 x 16 2 ) + (E x 16 1 ) + (6x 16°)
= (15 x 16 3 ) + (8 x 16 2 ) + (14 x 16 1 ) + (6 x 16°)
= 61,440 + 2,048 + 224 + 6
= 63,718
In other words,
F8E6 16 = 63,718,0
0000
0001
0002
0003
0004
0005
0006
0007
0008
0009
000A
000 B
00 0C
000D
000E
000F
3C
CD
57
28
FI
2A
D4
40
77
C3
84
28
21
3A
3E
IF
16
locations
0000
FFFF
65,536
locations
< a > (b)
Fig. 1-7 (a) First 16 words in memory; ( b ) 64K memory.
Memory Locations and Addresses
If a certain microcomputer has 64K memory, meaning
65,536 memory locations, each is able to store 1 byte. The
different memory locations are identified by hexadecimal
numbers called addresses. For instance, Fig. I -la shows
the first 16 memory locations; their addresses are from 0000
to 000F.
The address of a memory location is different from its
stored contents, just as a house address is different from
12 Digital Computer Electronics
the people living in the house. Figure I -la emphasizes the
point. At address 0000 the stored contents are 3C (equivalent
to 0011 1100). At address 0001 the stored contents are CD,
at address 0002 the stored contents are 57, and so on.
Figure 1-7 b shows how to visualize a 64K memory. The
first address is 0000, and the last is FFFF.
Table of Binaiy-Hexadecimal-Decimal
Equivalents
A 64K memory has 65,536 hexadecimal addresses from
0000 to FFFF. The equivalent binary addresses are from
0000 0000 0000 0000
to
mi mi nil nil
The first 8 bits are called the upper byte (UB); the second
8 bits are the lower byte (LB). If you have to do a lot of
binary-hexadecimal-decimal conversions, use the table of
equivalents in Appendix 2, which shows all the values for
a 64K memory.
Appendix 2 has four headings: binary, hexadecimal, UB
decimal, and LB decimal. Given a 16-bit address, you
convert the upper byte to its decimal equivalent (UB
decimal), the lower byte to its decimal equivalent (LB
decimal), and then add the two decimal equivalents. For
instance, suppose you want to convert
1101 0111 1010 0010
to its decimal equivalent. The upper byte is 1101 0111, or
hexadecimal D7; the lower byte is 1010 0010, or A2. Using
Appendix 2, find D7 and its UB decimal equivalent
D7 55,040
Next, find A2 and its LB decimal equivalent
A2 —» 162
Add the UB and LB decimal equivalents to get
55,040 + 162 = 55,202
This is the decimal equivalent of hexadecimal D7A2 or
binary 1101 0111 1010 0010.
Once familiar with Appendix 2, you will find it enor¬
mously helpful. It is faster, more accurate, and less tiring
than other methods. The only calculation required is adding
the UB and LB decimal, easily done mentally, with pencil
and paper, or if necessary, on a calculator. Furthermore, if
you are interested in converting only the lower byte, no
calculation is required, as shown in the next example.
EXAMPLE 1-8
Convert hexadecimal 7E to its decimal equivalent.
SOLUTION
When converting only a single byte, all you are dealing
with is the lower byte. With Appendix 2, look up 7E and
its LB decimal equivalent to get
7E —» 126
In other words, Appendix 2 can be used to convert single
bytes to their decimal equivalents (LB decimal) or double
bytes to their decimal equivalents (UB decimal + LB
decimal).
1-11 DECIMAL-TO-HEXADECIMAL
CONVERSION
One way to perform decimal-to-hexadecimal conversion is
to go from decimal to binary then to hexadecimal. Another
way is hex-dabble. The idea is to divide successively by
16, writing down the remainders. (Hex-dabble is like double-
dabble except that 16 is used for the divisor instead of 2.)
Here’s an example of how to convert decimal 2,479 into
hexadecimal form. The first division is
154 15 F
16 ) 2,479
The next step is
9 10 A
) 154 15 F
16 )2,479
The final step is
Read
down
0 9 9
J9 10 A
) 154 15 F
16 ) 2,479
Notice how similar hex-dabble is to double-dabble. Also,
remainders greater than 9 have to be changed to hexadecimal
digits (10 becomes A, 15 becomes F, etc.).
If you prefer, use Appendix 2 to look up the decimal-
hexadecimal equivalents. The next two examples show
how.
EXAMPLE 1-9
Convert decimal 141 to hexadecimal.
SOLUTION
Whenever the decimal number is between 0 and 255, all
you have to do is look up the decimal number and its
hexadecimal equivalent. With Appendix 2, you can see at
a glance that
8D <- 141
EXAMPLE 1-10
Convert decimal 36,020 to its hexadecimal equivalent.
SOLUTION
If the decimal number is between 256 and 65,535, you
need to proceed as follows. First, locate the largest UB
decimal that is less than 36,020. In Appendix 2, the largest
UB decimal is
UB decimal = 35,840
which has a hexadecimal equivalent of
8C <- 35,840
This is the upper byte.
Next, subtract the UB decimal from the original decimal
number:
36,020 - 35,840 - 180
The difference 180 has a hexadecimal equivalent
B4 <- 180
This is the lower byte.
By combining the upper and lower bytes, we get the
complete answer: 8CB4. This is the hexadecimal equivalent
of 36,020.
After a little practice, you will find Appendix 2 to be
one of the fastest methods of decimal-hexadecimal conver¬
sion.
1-12 BCD NUMBERS
A nibble is a string of 4 bits. Binary-coded-decimal (BCD)
numbers express each decimal digit as a nibble. For instance,
decimal 2,945 converts to a BCD number as follows:
Chapter 1 Number Systems and Codes 1 3
2 9 4 5
't >1 I' 'i
0010 1001 0100 0101
As you see, each decimal digit is coded as a nibble.
Here’s another example: 9,863 10 converts like this:
9 8 6 3
'l I' 'l >1
1001 1000 0110 0011
Therefore, 1001 1000 0110 0011 is the BCD equivalent of
9,863 10 .
The reverse conversion is similar. For instance, 0010
1000 0111 0100 converts as follows:
0010 1000 0111 0100
1 l' 'l >i
2 8 7 4
Applications
BCD numbers are useful wherever decimal information is
transferred into or out of a digital system. The circuits
inside pocket calculators, for example, can process BCD
numbers because you enter decimal numbers through the
keyboard and see decimal answers on the LED or liquid-
crystal display. Other examples of BCD systems are elec¬
tronic counters, digital voltmeters, and digital clocks; their
circuits can work with BCD numbers.
BCD Computers
BCD numbers have limited value in computers. A few
early computers processed BCD numbers but were slower
and more complicated than binary computers. As previously
mentioned, a computer is more than a number cruncher
because it must handle names and other nonnumeric data.
In other words, a modem computer must be able to process
alphanumerics (alphabet letters, numbers, and other sym¬
bols). This why modem computers have CPUs that process
binary numbers rather than BCD numbers.
Comparison of Number Systems
Table 1-5 shows the four number systems we have discussed.
Each number system uses strings of digits to represent
quantity. Above 9, equivalent strings appear different. For
instance, decimal string 128, hexadecimal string 80, binary
string 1000 0000, and BCD string 0001 0010 1000 are
equivalent because they represent the same number of
pebbles.
Machines have to use long strings of binary or BCD
numbers, but people prefer to chunk the data in either
decimal or hexadecimal form. As long as we know how to
1 4 Digital Computer Electronics
TABLE 1-5. NUMBER SYSTEMS
Decimal
Hexadecimal Binary
BCD
0
0
0000 0000
0000 0000 0000
1
1
0000 0001
0000 0000 0001
2
2
0000 0010
0000 0000 0010
3
3
0000 0011
0000 0000 0011
4
4
0000 0100
0000 0000 0100
5
5
0000 0101
0000 0000 0101
6
6
0000 0110
0000 0000 0110
7
7
0000 0111
0000 0000 0111
8
8
0000 1000
0000 0000 1000
9
9
0000 1001
0000 0000 1001
10
A
0000 1010
0000 0001 0000
11
B
0000 1011
0000 0001 0001
12
C
0000 1100
0000 0001 0010
13
D
0000 1101
0000 0001 0011
14
E
0000 1110
0000 0001 0100
15
F
oooo mi
0000 0001 0101
16
10
0001 0000
0000 0001 0110
32
20
0010 0000
0000 0011 0010
64
40
0100 0000
0000 0110 0100
128
80
1000 0000
0001 0010 1000
255
FF
mi nil
0010 0101 0101
convert from one number system to the next, we can always
get back to the ultimate meaning, which is the number of
pebbles being represented.
1-13 THE ASCII CODE
To get information into and out of a computer, we need to
use numbers, letters, and other symbols. This implies some
kind of alphanumeric code for the I/O unit of a computer.
At one time, every manufacturer had a different code,
which led to all kinds of confusion. Eventually, industry
settled on an input-output code known as the American
Standard Code for Information Interchange (abbreviated
ASCII). This code allows manufacturers to standardize
I/O hardware such as keyboards, printers, video displays,
and so on.
The ASCII (pronounced ask'-ee) code is a 7-bit code
whose format (arrangement) is
X 6 X 5 X 4 X 3 X 2 X 1 X 0
where each X is a 0 or a 1. For instance, the letter A is
coded as
1000001
Sometimes, a space is inserted for easier reading:
100 0001
TABLE 1-6. THE ASCII CODE
More examples are
(b)
(c)
(d)
X 3 X 2 XjXo
x 6 x 5 x 4
010
Oil
100
101
110
in
0000
SP
0
@
p
p
0001
!
1
A
Q
a
q
0010
rr
2
B
R
b
r
0011
#
3
c
s
c
s
0100
$
4
D
T
d
t
0101
%
5
E
U
e
u
0110
&
6
F
V
f
V
0111
’
7
G
w
g
w
1000
(
8
H
X
h
x
1001
)
9
I
Y
i
y
1010
*
J
Z
j
z
1011
+
*
K
k
1100
>
<
L
1
1101
-
=
M
m
1110
•
>
N
n
mi
/
?
O
0
Table 1-6 shows the ASCII code. Read the table the
same as a graph. For instance, the letter A has an X 6 X 5 X 4
of 100 and an X 3 X 2 XJXQ of 0001. Therefore, its ASCII
code is
100 0001 (A)
Table 1-6 includes the ASCII code for lowercase letters.
The letter a is coded as
110 0001 (a)
1100010
110 0011
1100100
and so on.
Also look at the punctuation and mathematical symbols.
Some examples are
010 0100 ($)
0101011 ( + )
0111101 ( = )
In Table 1-6, SP stands for space (blank). Hitting the space
bar of an ASCII keyboard sends this into a microcomputer:
010 0000 (space)
EXAMPLE 1-11
With an ASCII keyboard, each keystroke produces the
ASCII equivalent of the designated character. Suppose you
type
PRINT X
What is the output of an ASCII keyboard?
SOLUTION
P (101 0000), R (101 0010), I (100 1001), N (100 1110),
T (101 0100), space (010 0000), X (101 1000).
GLOSSARY
address Each memory location has an address, analogous
to a house address. Using addresses, we can tell the computer
where desired data is stored.
alphanumeric Letters, numbers, and other symbols.
base The number of digits (basic symbols) in a number
system. Decimal has a base of 10, binary a base of 2, and
hexadecimal a base of 16. Also called the radix.
bit An abbreviation for binary digit.
byte A string of 8 bits. The byte is the basic unit of binary
information. Most computers process data with a length of
8 bits or some multiple of 8 bits.
central processing unit The control section and the arith¬
metic-logic section. Abbreviated CPU.
chip An integrated circuit.
chunking Replacing a longer string by a shorter one.
data Names, numbers, and any other information needed
to solve a problem.
digital Pertains to anything in the form of digits, for
example, digital data.
hardware The electronic, magnetic, and mechanical de¬
vices used in a computer.
hexadecimal A number system with a base of 16. Hexa¬
decimal numbers are used in microprocessor work.
input-output Abbreviated I/O. The input and output sec¬
tions of a computer are often lumped into one unit known
as the I/O unit.
microcomputer A computer that uses a microprocessor
for its central processing unit (CPU).
microprocessor A CPU on a chip. It contains the control
and arithmetic-logic sections. Sometimes abbreviated MPU
(microprocessor unit).
nibble A string of 4 bits. Half of a byte.
program A sequence of instructions that tells the computer
how to process the data. Also known as software.
register A group of electronic, magnetic, or mechanical
devices that store digital data.
software Programs.
string A group of digits or other symbols.
Chapter 1 Number Systems and Codes 1 5
SELF-TESTING REVIEW
Read each of the following and provide the missing words.
Answers appear at the beginning of the next question.
1* Binary means-Binary numbers have a
base of 2. The digits used in a binary number
system are_and_
2. (two; 0, 1) Names, numbers, and other information
needed to solve a problem are called_
The-is a sequence of instructions that
tells the computer how to process the data.
3. (data, program) Computer ICs work reliably be¬
cause they are based on_design. When
a transistor is cut off or saturated, transistor
-have almost no effect.
4. (two-state, variations) A_is a group of
devices that store digital data._is an
abbreviation for binary digit. A byte is a string of
_bits.
5. ( register, Bit, 8) The control and arithmetic-logic
sections are called the_(CPU). A micro¬
processor is a CPU on a chip. A microcomputer
is a computer that uses a_for its CPU.
6. (central processing unit, microprocessor ) The ab¬
breviation K indicates units of approximately 1,000
or precisely 1,024. Therefore, IK means 1,024, 2K
means 2,048, 4K means_and 64 K
means_
7. (4,096, 65,536) The hexadecimal number system is
widely used in analyzing and programming_
The hexadecimal digits are 0 to 9 and A to_
The main advantage of hexadecimal numbers is the
ease of conversion from hexadecimal to_
and vice versa.
8. ( microprocessors, F, binary ) A typical microcom¬
puter may have up to 65,536 registers in its mem¬
ory. Each of these registers, usually called a_,
stores 1 byte. Such a memory is specified as a 64-
kilobyte memory, or simply a_memory.
9. (memory location, 64K) Binary-coded-decimal
(BCD) numbers express each decimal digit as a_
BCD numbers are useful whenever_in¬
formation is transferred into or out of a digital
system. Equipment using BCD numbers includes
pocket calculators, electronic counters, and digital
voltmeters.
10. (nibble, decimal) The ASCII code is a 7-bit code
for-(letters, numbers, and other sym¬
bols).
11. (alphanumerics) With the typical microcomputer,
you enter the program and data with typewriter
keyboard that converts each character into ASCII
code.
PROBLEMS
1-1. How many bytes are there in each of these num¬
bers?
a. 1100 0101
b. 1011 1001 0110 1110
c. 1111 1011 0111 0100 1010
1-2. What are the equivalent decimal numbers for each
of the following binary numbers: 10, 110, 111,
1011, 1100, and 1110?
1-3. What is the base for each of these numbers?
a. 348 io
b. 1100 0101 2
c. 2312 5
d. F4C3 16
1-4. Write the equation
2 + 2 — 4
using binary numbers.
1-5. What is the decimal equivalent of 2 10 ? What does
4K represent? Express 8,192 in K units.
1-6. A 4-bit register has output voltages of high-low-
high-low. What is the binary number stored in the
register? The decimal equivalent?
16 Digital Computer Electronics
o*oioo»»
Fig. 1-8 An 8-bit LED display.
1-7. Figure 1-8 shows an 8-bit LED display. A light
circle means that a LED is on (binary 1) and a
dark circle means a LED is off (binary 0). What
is the binary number being displayed? The deci¬
mal equivalent?
1-8. Convert the following binary numbers to decimal
numbers:
a. 00111
b. 11001
c. 10110
d. 11110
1-9. Solve the following equation for x :
x 10 = 11001001 2
1-10. An 8-bit transistor register has this output:
low-high-low-high-low-high-low-high
What is the equivalent decimal number being
stored?
Fig- 1-9 An 8-bit core register.
1 - 11 .
Fig. 1
1 - 12 .
M3.
1-14.
1-15.
1-16.
1-17.
1-18.
1-19.
1 - 20 .
In Fig. 1-9 clockwise flux stands for binary 1 and
counterclockwise flux for binary 0. What is the
binary number stored in the 8-bit core register?
Convert this byte to an equivalent decimal
number.
10 A 5-bit switch register.
Figure 1-10 shows a 5-bit switch register. By
opening and closing the switches you can set up
different binary numbers. As usual, high output
voltage stands for binary 1 and low output voltage
for binary 0. What is the binary number stored in
the switch register? The equivalent decimal num¬
ber?
Convert decimal 56 to its binary equivalent.
Convert 72 10 to a binary number.
An 8-bit transistor register stores decimal 150.
What is the binary output of the register?
How would you set the switches of Fig. 1-10 to
get a decimal output of 27?
A hexadecimal odometer displays F52A. What are
the next six readings?
The reading on a hexadecimal odometer is 27FF.
What is the next reading? Miles later, you see a
reading of 8AFC. What are the next six readings?
Convert each of the following hexadecimal num¬
bers to binary:
a. FF
b. ABC
c. CD42
d. F329
Convert each of these binary numbers to an
equivalent hexadecimal number:
a. 1110 1000
b. 1100 1011
c. 1010 11110110
d. 1000 1011 1101 0110
1-21. Here is a program written for the 8085 micro¬
processor:
Address
Hex Contents
2000
3E ! 1
2001
0E
2002
D3
2003
20
2004
76
Convert the hex contents to equivalent binary
numbers.
1-22. Convert each of these hexadecimal numbers to its
decimal equivalent:
a. FF
b. A4
c. 9B
d. 3C
1-23. Convert the following hexadecimal numbers to
their decimal equivalents:
a. 0FFF
b. 3FFF
c. 7FE4
d. B3D8
1-24. A microcomputer has memory locations from
0000 to 0FFF. Each memory location stores 1
byte. In decimal, how many bytes can the micro¬
computer store in its memory ? How many kilo¬
bytes is this?
1-25. Suppose a microcomputer has memory locations
from 0000 to 3FFF, each storing 1 byte. How
Chapter 1 Number Systems and Codes 1 7
many bytes can the memory store? Express this in
kilobytes.
1-26. A microcomputer has a 32K memory. How many
bytes does this represent? If 0000 stands for the
first memory location, what is the hexadecimal
notation for the last memory location?
1-27. If a microcomputer has a 64K memory, what are
the hexadecimal notations for the first and last
memory locations?
1-28. Convert the following decimal numbers to hexa¬
decimal:
a. 4,095
b. 16,383
c. 32,767
d. 65,535
1-29. Convert each of the following decimal numbers to
hexadecimal numbers:
a. 238
b. 7,547
c. 15,359
d. 47,285
1-30. How many nibbles are there in each of the fol¬
lowing:
/j a. 1000 0111- *
b. 10QJ OODO 01(10 0011
c. 0101 1001 0111 0010 0110 01K)
1-31. If the numbers in Prob. 1-30 are BCD numbers,
what are the equivalent decimal numbers?
1-32. What is the ASCII code for each of the following:
a. 7
b. W
c. f
d. y
1-33. Suppose you type LIST with an ASCII keyboard.
What is the binary output as you strike each
letter?
1-34. For each of the following rows, provide the miss¬
ing numbers in the bases indicated.
Base 2
Base 10
Base 16
a 0100 0001
b.
200
C.
3CD
d.
125
noi mo mi
f.
FFFF
g.
2,000
18 Digital Computer Electronics
Gates
For centuries mathematicians felt there was a connection
between mathematics and logic, but no one before George
Boole could find this missing link. In 1854 he invented
symbolic logic, known today as boolean algebra. Each
variable in boolean algebra has either of two values: true
or false. The original purpose of this two-state algebra was
to solve logic problems.
Boolean algebra had no practical application until 1938,
when Claude Shannon used it to analyze telephone switching
circuits. He let the variables represent closed and open
relays. In other words, Shannon came up with a new
application for boolean algebra. Because of Shannon’s
work, engineers realized that boolean algebra could be
applied to computer electronics.
This chapter introduces the gate , a circuit with one or
more input signals but only one output signal. Gates are
digital (two-state) circuits because the input and output
signals are either low or high voltages. Gates are often
called logic circuits because they can be analyzed with
boolean algebra.
2-1 INVERTERS
An inverter is a gate with only one input signal and one
output signal; the output state is always the opposite of the
• input state.
Transistor Inverter
Figure 2-1 shows a transistor inverter. This common-emitter
amplifier switches between cutoff and saturation. When V IN
is low (approximately 0 V), the transistor cuts off and F G ut
is high. On the other hand, a high V IN saturates the transistor,
forcing V ol]T to go low.
Table 2-1 summarizes the operation. A low input produces
a high output, and a high input results in a low output.
Table 2-2 gives the same information in binary form; binary
0 stands for low voltage and binary 1 for high voltage.
An inverter is also called a not gate because the output
is not the same as the input. The output is sometimes called
the complement (opposite) of the input.
+5 V
Fig. 2-1 Example of inverter design.
TABLE 2-1 TABLE 2-2
(c) (d)
Fig. 2-2 Logic symbols: (a) inverter; ( b) another inverter symbol;
(c) double inverter; ( d) buffer.
Inverter Symbol
Figure 2-2 a is the symbol for an inverter of any design.
Sometimes a schematic diagram will use the alternative
symbol shown in Fig. 2-2 b\ the bubble (small circle) is on
19
the input side. Whenever you see either of these symbols,
remember that the output is the complement of the input.
Noninverter Symbol
If you cascade two inverters (Fig. 2-2c), you get a nonin¬
verting amplifier. Figure 2-2 d is the symbol for a nonin¬
verting amplifier. Regardless of the circuit design, the action
is always the same: a low input voltage produces a low
output voltage, and a high input voltage results in a high
output voltage.
The main use of noninverting amplifier is buffering
(isolating) two other circuits. More will be said about
buffers in a later chapter.
EXAMPLE 2-1
i
1 -TSq _ u
A
\s°
B
0
B
0 rso - 1
[y°
0
0 h>o 1
6 bit
6-bit
l/°
register
D
1
register
r>
1 ISo 0
U
ly°
0
p
0 ISo 1
B
o
ly°
F
1
F
■ 1>° ■
(a) (b)
Fig. 2-3 Example 2-1.
Figure 2-3a has an output, A to F, of 100101. Show how
to complement each bit.
SOLUTION
Easy. Use an inverter on each signal line (Fig. 2-3 b). The
final output is now 011010.
A hex inverter is a commercially available IC containing
six separate inverters. Given a 6-bit register like Fig. 2-3a,
we can connect a hex inverter to complement each bit as
shown in Fig. 2-3 b.
One more point. In Fig. 2-3 a the bits may represent a
coded instruction, number, letter, etc. To convey this variety
of meaning, a string of bits is often called a binary word
or simply a word. In Fig. 2-3 b the word 100101 is
complemented to get the word 011010.
2-2 OR GATES
The or gate has two or more input signals but only one
output signal. If any input signal is high, the output signal
is high.
A O
B O
Fig. 2-4 A 2 -input diode or gate.
Diode or Gate
Figure 2-4 shows one way to build an or gate. If both
inputs are low, the output is low. If either input is high,
the diode with the high input conducts and the output is
high. Because of the two inputs, we call this circuit a 2-
input or gate.
Table 2-3 summarizes the action; binary 0 stands for low
voltage and binary 1 for high voltage. Notice that one or
more high inputs produce a high output; this is why the
circuit is called an or gate.
- 1 >\ -
B o-£>(-n-
CO-W-
Fig. 2-5 A 3-input diode or gate.
More than Two Inputs
Figure 2-5 shows a 3-input or gate. If all inputs are low,
all diodes are off and the output is low. If 1 or more inputs
are high, the output is high.
Table 2-4 summarizes the action. A table like this is
called a truth table; it lists all the input possibilities and
the corresponding outputs. When constructing a truth table,
always list the input words in a binary progression as shown
(000, 001, 010, . . . , 111); this guarantees that all input
possibilities will be accounted for.
An or gate can have as many inputs as desired; add one
diode for each additional input. Six diodes result in a 6-
TABLE 2-3.
TWO INPUT
OR GATE
A
B
Y
0
0
0
0
1
1
1
0
1
1
1
1
TABLE 2-4. THREE-
INPUT or GATE
A
B
c
Y
0
0
0
0
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
20 Digital Computer Electronics
input or gate, nine diodes in a 9-input or gate. No matter
how many inputs, the action of any or gate is summarized
like this: one or more high inputs produce a high output.
Bipolar transistors and MOSFETs can also be used to
build or gates. But no matter what devices are used, or
gates always produce a high output when one or more
inputs are high. Figure 2-6 shows the logic symbols for
2-, 3-, and 4-input or gates.
(a) (b) (c)
Fig. 2-6 OR-gate symbols.
EXAMPLE 2-3
How many inputs words are in the truth table of an 8-input
or gate? Which input words produce a high output?
SOLUTION
The input words are 0000 0000, 0000 0001, . . . , 1111
1111. With the formula of the preceding example, the total
number of input words is 2" = 2 8 = 256.
In any or gate, 1 or more high inputs produce a high
output. Therefore, the input word of 0000 0000 results in
a low output; all other input words produce a high output.
EXAMPLE 2-2
Show the truth table of a 4-input or gate.
SOLUTION
Let Y stand for the output bit and A, B, C, D for input bits.
Then the truth table has input words of 0000, 0001, 0010,
. . . , 1111, as shown in Table 2-5. As expected, output Y
is 0 for input word 0000; Y is 1 for all other input words.
As a check, the number of input words in a truth table
always equals 2", where n is the number of input bits. A
2-input or gate has a truth table with 2 2 or 4 input words;
a 3-input or gate has 2 3 or 8 input words; and a 4-input
or gate has 2 4 or 16 input words.
TABLE 2-5. FOUR-INPUT or
GATE
A
B
c
D
Y
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0 j
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
1
- ■ \
\ i \ ;
EXAMPLE 2-4
+5 V
Fig. 2-7 Decimal-to-binary encoder.
The switches of Fig. 2-7 are push-button switches like those
of a pocket calculator. The bits out of the or gates form a
4-bit word, designated Y 3 Y 2 Y!Y 0 . What does the circuit
do?
SOLUTION
Figure 2-7 is a decimal-to-binary encoder, a circuit that
converts decimal to binary. For instance, when push button
3 is pressed, the Y x and Y 0 or gates have high inputs;
therefore, the output word is
Y 3 Y 2 Y 1 Y 0 = 0011
Chapter 2 Gates 2 1
If button 5 is keyed, the V 2 and Y 0 or gates have high
inputs and the output word becomes
TABLE 2-6. TWO-
INPUT and GATE
Y 3 Y 2 Y,Y 0 = 0101
When switch 9 is pressed,
Y 3 Y 2 Y,Yo = 1001
Check the other input switches to convince yourself that
the output word always equals the binary equivalent of the
switch being pressed.
2-3 AND GATES
A
B
Y
0
0
0
0
1
0
1
0
0
1
1
1
Table 2-6 summarizes the action. As usual, binary zero
stands for low voltage and binary 1 for high voltage. As
you see, A and B must be high to get a high output; this is
why the circuit is called an and gate.
The and gate has two or more input signals but only one
output signal. All inputs must be high to get a high output.
+5 v
fa)
+5 V
+5 V +5 V
Fig. 2-8 A 2-input and gate, (a) circuit; ( b ) both inputs low; (t*)l
low input, 1 high; (d) both inputs high.
+5 V
Fig. 2-9 A 3-input and gate.
More than Two Inputs
Figure 2-9 is a 3-input and gate. If all inputs are low, all
diodes conduct and pull the output down to a low voltage.
Even one conducting diode will pull the output down to a
low voltage; therefore, the only way to get a high output
is to have all inputs high. When all inputs are high, all
diodes are nonconducting and the supply voltage pulls the
output up to a high voltage.
Table 2-7 summarizes the 3-input and gate. The output
is 0 for all input words except 111. That is, all inputs must
be high to get a high output.
and gates can have as many inputs as desired; add one
diode for each additional input. Eight diodes, for instance,
result in an 8-input and gate; sixteen diodes in a 16-input
Diode and Gate
Figure 2-8 a shows one way to build an and gate. In this
circuit the inputs can be either low (ground) or high (4- 5
V). When both inputs are low (Fig. 2-8b), both diodes
conduct and pull the output down to a low voltage. If one
of the inputs is low and the other high (Fig. 2-8c), the
diode with the low input conducts and this pulls the output
down to a low voltage. The diode with the high input, on
the other hand, is reverse-biased or cut off, symbolized by
the dark shading in Fig. 2-8c.
When both inputs are high (Fig. 2-8 d), both diodes are
cut off. Since there is no current in the resistor, the supply
voltage pulls the output up to a high voltage (-1-5 V).
TABLE 2-7. THREE-
INPUT and GATE
A
B
c
Y
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
22 Digital Computer Electronics
(a) (b) (c)
Fig. 2-10 AND-gate symbols.
and gate. No matter how many inputs an and gate has,
the action can be summarized like this: All inputs must be
high to get a high output.
Figure 2-10 shows the logic symbols for 2-, 3-, and 4-
input and gates.
EXAMPLE 2-5
Describe the truth table of an 8 -input and gate.
SOLUTION
The input words are from 0000 0000 to 1111 1111, following
the binary progression. The total number of input words is
2* = 2 8 = 256
The first 255 input words produce a 0 output. Only the last
word, 111 1 1111, results in a 1 output. This is because all
inputs must be high to get a high output.
For instance, when
ENABLE = 0
each and gate has a low ENABLE input. No matter what
the register contents, the output of each and gate must be
low. Therefore, the final word is
Y 5 Y 4 Y 3 Y 2 Y 1 Yo = oooooo
As you see, a low ENABLE blocks the register contents
from the final output.
On the other hand, when
ENABLE = 1
the output of each and gate depends on the data inputs (A,
B, C, . . .); a low data input results in a low output, and
a high data input in a high output. For example, if ABCDEF
= 100100, a high ENABLE gives
Y 5 Y 4 Y 3 Y 2 Y 1 Yo = 100100
In general, a high ENABLE transmits the register contents
to the final output to get
Y 5 Y 4 Y 3 Y 2 Y 1 Y 0 = ABCDEF
EXAMPLE 2-6
Fig. 2-11 Using and gates to block or transmit data.
The 6-bit register of Fig. 2-11 stores the word ABCDEF.
The ENABLE input can be low or high. What does the
circuit do?
SOLUTION
One use of and gates is to transmit data when certain
conditions are satisfied. In Fig. 2-11 a low ENABLE blocks
the register contents from the final output, but a high
ENABLE transmits the register contents.
2-4 BOOLEAN ALGEBRA
As mentioned earlier, Boole invented two-state algebra to
solve logic problems. This new algebra had no practical
use until Shannon applied it to telephone switching circuits.
Today boolean algebra is the backbone of computer circuit
analysis and design.
Inversion Sign
In boolean algebra a variable can be either a 0 or a 1. For
digital circuits, this means that a signal voltage can be
either low or high. Figure 2-12 is an example of a digital
circuit because the input and output voltages are either low
or high. Furthermore, because of the inversion, Y is always
the complement of A .
Fig. 2-12 Inverter.
A word equation for Fig. 2-12 is
Y = NOT A (2-1)
Chapter 2 Gates 23
If A is 0,
Y = NOT 0 = 1
On the other hand, if A is 1,
Y = not I = 0
In boolean algebra, the overbar stands for the NOT
operation. This means that Eq. 2-1 can be written
Y = A (2-2)
Read this as ‘7 equals not A” or ‘T equals the complement
of A. ” Equation 2-2 is the standard way to write the output
of an inverter.
Using the equation is easy. Given the value of A, substitute
and solve for Y. For instance, if A is 0,
Y = A = 0=1
because not 0 is 1. On the other hand, if A is 1,
Y = A = I = 0
because not 1 is 0.
Fig. 2-13 or gate.
or Sign
A word equation for Fig. 2-13 is
Y = A or B (2-3)
Given the inputs, you can solve for the output. For instance,
if A = 0 and B — 0,
Y = 0 or 0 = 0
because 0 comes out of an or gate when both inputs are
0s.
As another example, if A = 0 and B = 1,
Y = 0 or 1 = 1
because 1 comes out of an or gate when either input is 1.
Similarly, if A = 1 and # = 0,
r = i or o = i
If A — 1 and B = 1,
Y = ] OR 1 = 1
In boolean algebra the + sign stands for the or operation.
In other words, Eq. 2-3 can be written
Y = A + B (2-4)
Read this as ‘T equals A or ZT” Equation 2-4 is the
standard way to write the output of an or gate.
Given the inputs, you can substitute and solve for the
output. For instance, if A = 0 and B — 0,
Y = A + B = 0 + 0 = 0
If A = 0 and B = 1,
F = A+ 5 = 0+ l = l
because 0 ORed with 1 results in 1. If A = 1 and B — 0,
y=A+S=l+0=l
If both inputs are high,
y = A + 5 = 1 + 1 = 1
because 1 ORed with 1 gives 1 .
Don’t let the new meaning of the + sign bother you.
There’s nothing unusual about symbols having more than
one meaning. For instance, 44 pot” may mean a cooking
utensil, a flower container, the money wagered in a card
game, a derivative of cannabis sativa and so forth; the
intended meaning is clear from the sentence it’s used in.
Similarly, the + sign may stand for ordinary addition or
or addition; the intended meaning comes across in the way
it’s used. If we’re talking about decimal numbers, + means
ordinary addition, but when the discussion is about logic
circuits, + stands for or addition.
and Sign
A word equation for Fig. 2-14 is
Y = A AND B (2-5)
In boolean algebra the multiplication sign stands for the
and operation. Therefore, Eq. 2-5 can be written
Y = A * B
or simply
Y — AB (2-6)
24 Digital Computer Electronics
Read this as ‘T equals A and 5.” Equation 2-6 is the
standard way to write the output of an and gate.
Given the inputs, you can substitute and solve for the
output. For instance, if both inputs are low,
F = A£ = 0- 0 = 0
because 0 ANDed with 0 gives 0. If A is low and B is high,
Y = AB = 0-1=0
because 0 comes out of an and gate if any input is 0. If A
is 1 and B is 0,
Y = AB = 1-0 = 0
When both inputs are high,
Y = AB = 1-1 = 1
because 1 ANDed with 1 gives 1.
Decision-Making Elements
The inverter, or gate, and and gate are often called
decision-making elements because they can recognize some
input words while disregarding others. A gate recognizes a
word when its output is high; it disregards a word when its
output is low. For example, the and gate disregards all
words with one or more 0s; it recognizes only the word
whose bits are all Is.
Notation
In later equations we need to distinguish between bits that
are ANDed and bits that are part of a binary word. To do
this we will use italic (slanted) letters (A, B, Y, etc.) for
ANDed bits and roman (upright) letters (A, B, Y, etc.) for
bits that form a word.
For example, Y 2 Y 2 Y X Y 0 stands for the logical product
(ANDing) of y 3 , Y 2 , Y ]9 and Y 0 . If Y 3 = 1, Y 2 = 0, Y x =
0, and Y 0 = 1, the product Y 3 Y 2 Y X Y 0 will reduce as follows:
y 3 y 2 y 1 y 0 = 1 • 0 • 0 • 1 = 0 O' ■
In this case, the italic letters represent bits that are being
ANDed.
On the other hand, Y 3 Y 2 Y 1 Y 0 is our notation for a 4-bit
word. With the Y values just given, we can write
Y 3 Y 2 YjY 0 = 1001
In this equation, we are not dealing with bits that are
ANDed; instead, we are dealing with bits that are part of a
word.
The distinction between italic and roman notation will
become clearer when we get to computer analysis.
Positive and Negative Logic
A final point. Positive logic means that 1 stands for the
more positive of the two voltage levels. Negative logic
means that 1 stands for the more negative of the two voltage
levels. For instance, if the two voltage levels are 0 and -5
V, positive logic would have 1 stand for 0 V and 0 for -5
V, whereas negative logic would have 1 stand for - 5 V
and 0 for 0 V.
Ordinarily, people use positive logic with positive supply
voltages and negative logic with negative supply voltages.
Throughout this book, we will be using positive logic.
EXAMPLE 2-7
(a)
:=D-£>—
(b)
Fig. 2-15 Logic circuits.
What is the boolean equation for Fig. 2-15a? The output if
both inputs are high?
SOLUTION
A is inverted before it reaches^ the or gate; therefore, the
upper input to the or gate is A. The final output is
Y = A + 5
This is the boolean equation for Fig. 2-15a.
To find the output when both inputs are high, either of
two approaches can be used. First, you can substitute
directly into the foregoing equation and solve for Y
f = a + z? = T+ i = o+ i = 1
Alternatively, you can analyze the operation of Fig. 2-15a
like this. If both inputs are high, the inputs to the or gate
are 0 and 1. Now, 0 ORed with 1 gives 1. Therefore, the
final output is high.
EXAMPLE 2-8
What is the boolean equation for Fig. 2-15 bl If both inputs
are high, what is the output?
Chapter 2 Gates 25
SOLUTION
TABLE 2-8. TRUTH TABLE
FOR Y = AB + CD
The and gate forms the logical product AB, which is
inverted to get
Y = AB
Read this as “Y equals not AB” or “F equals the
complement of AB.”
If both inputs are high, direct substitution into the equation
gives
Y = AB = I 7 ! = 1 = 0
Note the order of operations: the ANDing is done first, then
the inversion.
Instead of using the equation, you can analyze Fig.
2-15B as follows. If both inputs are high, the and gate has
a high output. Therefore, the final output is low.
EXAMPLE 2-9
Fig. 2-16 Logic circuits.
What is the boolean equation for Fig. 2-16 a! The truth
table? Which input words does the circuit recognize?
SOLUTION
The upper and gate forms the logical product AB , and the
lower and gate gives CD . ORing these products results in
Y = AB + CD
Read this as “T equals AB or CD.”
Next, look at Fig. 2-16a. The final output is high if the
or gate has one or more high inputs. This happens when
AB is 1, CD is 1, or both are Is. In turn, AB is 1 when
A = 1 and B = 1
A
B
c
D
Y
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
1
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
1
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
1
CD is 1 when
C = 1 and D = 1
Both products are Is when
A — l B = 1 C = 1 and D = 1
Therefore, the final output is high when A and B are Is,
when C and D are Is, or when all inputs are Is.
Table 2-8 summarizes the foregoing analysis. From this
it’s clear that the circuit recognizes these input words: 0011,
0111, 1011, 1100, 1101, 1110, and 1111.
EXAMPLE 2-10
Write the boolean equation for Fig. 2-16 b. If all inputs are
high, what is the output?
SOLUTION
The OR gate forms the logical sum B + C. This sum is
ANDed with A to get
Y = A(B + C)
(Parentheses indicate ANDing.)
One way to find the output when all inputs are high is
to substitute and solve as follows:
Y = A(B + C) = 1(1 + 1) = 1(1) = 1
26 Digital Computer Electronics
Alternatively, you can analyze Fig. 2-166 like this. If all
inputs are high, the OR gate has a high output; therefore,
both inputs to the and gate are high. Since all high inputs
to an and gate result in a high output, the final output is
high.
EXAMPLE 2-11
Fig. 2-17 A l-of-10 decoder.
What is the boolean equation for each Y output in Fig.
2-17 ?
SOLUTION
Each and gate forms the logical product of its input signals.
The inputs to the top and gate are A, B, C and D; therefore,
To = ABCD
The inputs to the next and gate are A, B, C and D: this
means that
T, = ABCD
Analyzing the remaining gates gives
Y 2 = ABCD
T 3 = ABCD
Y 4 = ABCD
Y 5 = ABCD
Y 6 = ABCD
Y 7 = ABCD
T 8 = ABCD
Y 9 = ABCD
EXAMPLE 2-12
What does the circuit of Fig. 2-17 do?
SOLUTION
This is a binary-to-decimal decoder, a circuit that converts
from binary to decimal. For instance, when the register
contents are 0011, the T 3 and gate has all high inputs;
therefore, T 3 is high. Furthermore, register contents of 0011
mean that all other and gates have at least one low input.
As a result, all other and gates have low outputs. (Analyze
the circuit to convince yourself.)
If the register contents change to 0100, only the Y 4 and
gate has all high inputs; therefore, only Y 4 is high. If the
register contents change to 0111, Y 7 is the only high output.
In general, the subscript of the high output equals the
decimal equivalent of the binary number stored in the
register. This is why the circuit is called a binary-to-decimal
decoder.
The circuit of this example is also called a 4-line-to-10-
line decoder because there are 4 input lines and 10 output
lines. Another name for it is a l-of-10 decoder because
only 1 of 10 output lines has a high voltage.
GLOSSARY
AND gate A logic circuit whose output is high only when boolean algebra Originally known as symbolic logic, this
all inputs are high. modem algebra uses the set of numbers 0 and 1. The
Chapter 2 Gates 27
operations or, and, and not are sometimes called union ,
intersection , and inversion . Boolean algebra is ideally suited
to digital circuit analysis.
complement The output of an inverter.
gate A logic circuit with one or more input signals but
only one output signal.
inverter A gate with only 1 input and 1 output. The output
is always the complement of the input. Also known as a
not gate.
logic circuit A circuit whose input and output signals are
two-state, either low or high voltages. The basic logic
circuits are or, and, and not gates.
OR gate A logic circuit with 2 or more inputs and only 1
output; 1 or more high inputs produce a high output.
truth table A table that shows all input and output
possibilities for a logic circuit. The input words are listed
in binary progression.
word A string of bits that represent a coded instruction
or data.
SELF-TESTING REVIEW
Read each of the following and provide the missing words.
Answers appear at the beginning of the next question.
1. A gate is a logic circuit with one or more input
signals but only_output signal. These
signals are either-or high.
2. (one, low ) An inverter is a gate with only-
input; the output is always in the opposite state from
the input. An inverter is also called a-
gate. Sometimes the output is referred to as the
complement of the input.
3. (7, not) The or gate has two or more input signals.
If any input is_, the output is high. The
number of input words in a truth table always equals
_, where n is the number of input bits.
4. (high, 2 n ) The __-___- gate has two or more
input signals. All inputs must be high to get a high
output.
5. (and) In boolean algebra, the overbar stands for the
not operation, the plus sign stands for the-
operation, and the times sign for the-
operation.
6. (or, and) The inverter, or gate, and and gate are
called decision-making elements because they can
recognize some input-while disregarding
others. A gate recognizes a word when its output is
7. (words, high) A binary-to-decimal decoder is also
called a 4-line-to-10-line decoder because it has 4
input lines and 10 output lines. Another name for it
is the l-of-10 decoder because only 1 of its 10 output
lines is high at a time.
PROBLEMS
2-1. How many inputs signals can a gate have? How
many output signals?
2-2. If you cascade seven inverters, does the overall
circuit act like an inverter or noninverter?
2-3. Double inversion occurs when two inverters are
cascaded. Does such a connection act like an
inverter or noninverter?
2-4. The contents of the 6-bit register in Fig. 2-3 b
change to 101010. What is the decimal equivalent
of the register contents? The decimal equivalent
out of the hex inverter?
2-5. An or gate has 6 inputs. How many input words
are in its truth table? What is the only input word
that produces a 0 output?
2-6. Figure 2-18 shows a hexadecimal encoder, a cir¬
cuit that converts hexadecimal to binary. Press¬
ing each push-button switch results in a differ¬
ent output word Y 3 Y 2 Y 1 Y 0 . Starting with switch
0, what are the output words? (Note: The new
symbol in Fig. 2-18 is another way to draw an or
gate.
2 8 Digital Computer Electronics
2-7. In Fig. 2-18 what switches would you press to
produce
0011 1001 1100 1111
(Work from left to right.)
2-8. What is the 4-bit output in Fig. 2-18 when switch
A is pressed? Switch 4? Switch E? Switch 6?
2-9. An and gate has 7 inputs. How many input
words are in its truth table? What is the only
input word that produces a 1 output?
2-10. Visualize the register contents of Fig. 2-19 as the
word A 7 A 6 • • • A 0 , and the final output as the
word Y 7 Y 6 • • • Y 0 . What is the output word for
each of the following conditions:
a.
A 7 A 6
• A 0 = 1100 1010, ENABLE = 0.
b.
a 7 a 6 • ,*
• • Aq = 0101 1101, ENABLE = 1.
c.
A 7 A 6
• • A 0 = 1111 0000, ENABLE = 1.
d.
A 7 A 6
■ • A 0 = 1010 1010, ENABLE = 0.
+ 5 V
Fig. 2-18 Hexadecimal encoder.
ENABLE
Fig. 2-20
(a)
B c E^y ~£>°— r
(b)
2-11. The 8-bit register of Fig. 2-19 stores 59 I0 . What
is the decimal equivalent of the final output word
if ENABLE = 0? If ENABLE - 1?
2-12. Answer these questions:
a. What input words does a 6-input or gate
recognize? What word does it disregard?
b. What input word does an 8-input and gate
recognize? What words does it disregard?
2-13. What is the boolean equation for Fig. 2-20a? The
output if both inputs are high?
2-14. If all inputs are high in Fig. 2-206, what is the
output? The boolean equation for the circuit?
What is the only ABC input word the circuit
recognizes?
2-15. If you constructed the truth table for Fig. 2-206,
how many input words would it contain?
Chapter 2 Gates 29
2-16. What is the boolean equation for Fig. 2-21 at The
output if both inputs are high?
2-17. If all inputs are high in Fig. 2-21 b, what is the
output? What is the boolean equation of the cir¬
cuit? What ABC input words does the circuit
recognize? What is the only word it disregards?
2-18. What is the boolean equation for Fig. 2-22 al The
output if all inputs are Is? If you were to con¬
struct the truth table, how many input words
would it have?
2-19. Write the boolean equation for Fig. 2-22 b. If all
inputs are Is, what is the output?
2-20. If both inputs are high in Fig. 2-23, what is the
output? What is the boolean equation for the cir¬
cuit? Describe the truth table.
2-21. What is the boolean equation for Fig. 2-24? How
many ABCD input words are in the truth table?
Which input words does the circuit recognize?
2-22. Because of the historical connection between bool¬
ean algebra and logic, some people use the words
“true” and “false” instead of “high” and
“low” when discussing logic circuits. For in¬
stance, here’s how an and gate can be described.
If any input is false, the output is false; if all
inputs are true, the output is true.
a. If both inputs are false in Fig. 2-23, what is
the output?
b. What is the output in Fig. 2-23 if one input is
false and the other true?
c. In Fig. 2-23 what is the output if all inputs are
true?
2-23. Figure 2-25 shows a l-of-16 decoder. The signals
coming out of the decoder are labeled LDA,
ADD, SUB , and so on. The word formed by the 4
leftmost register bits is called the OP CODE. As
an equation,
OP CODE = I 15 I 14 I 13 I 12
a. If LDA is high, what does OP CODE equal?
b. If ADD is high, what does it equal?
c. When OP CODE = 1001, which of the output
signals is high?
d. Which output signal is high if OP CODE =
mi?
2-24. In Fig. 2-25, list the OP CODE words and the
corresponding high output signals. (Start with
0000 and proceed in binary to 1111.)
2-25. In the following equations the equals sign means
“is equivalent to.” Classify each of the following
as positive or negative logic:
a. 0 = 0 V and 1 = +5 V.
b. 0 = +5 V and 1 = 0 V.
c. 0 = —5 V and 1 = 0 V.
d. 0 = 0 V and 1 = — 5 V.
2-26. In Fig. 2-25 four output lines come from the
decoder. Is it possible to add more op codes
without increasing the number of output lines?
2-27. How many output lines from the decoder would
be needed to have 256 op codes?
Chapter 2 Gates
31
More Logic Gates
This chapter introduces nor and nand gates, devices that
are widely used in industry. You will also learn about De
Morgan’s theorems; they help you to rearrange and simplify
logic circuits.
3-1 NOR GATES
The nor gate has two or more input signals but only one
output signal. All inputs must be low to get a high output.
In other words, the NOR gate recognizes only the input
word whose bits are all Os.
Fig. 3-1 nor gate: (a) logical meaning; (b) standard symbol.
TABLE 3-1. TWO-
INPUT nor GATE
A
B
A + B
0
0
1
0
1
0
1
0
0
1
1
0
Incidentally, the boolean equation for a 2-input nor gate
is
Y = AT ~B (3-1)
Read this as ‘T equals not A or B.” If you use this
equation, remember that the ORing is done first, then the
inversion.
Two-Input Gate
Figure 3-1 a shows the logical structure of a nor gate,
which is an or gate followed by an inverter. Therefore,
the final output is not the or of the inputs. Originally
called a not-or gate, the circuit is now referred to as a
nor gate.
Figure 3-lb is the standard symbol for a nor gate. Notice
that the inverter triangle has been deleted and the small
circle or bubble moved to the OR-gate output. The bubble
is a reminder of the inversion that follows the ORing.
With Fig. 3-la and b the following ideas are clear. If
both inputs are low, the final output is high. If one input
is low and the other high, the output is low. And if both
inputs are high, the output is low.
Table 3-1 summarizes the circuit action. As you see, the
nor gate recognizes only the input word whose bits are all
Os. In other words, all inputs must be low to get a high
output.
Three-Input Gate
Regardless of how many inputs a NOR gate has, it is still
logically equivalent to an or gate followed by an inverter.
For instance, Fig. 3-2a shows a 3-input nor gate. The 3
inputs are ORed, and the result is inverted. Therefore, the
boolean equation is
Y = A + B + C (3-2)
The analysis of Fig. 3-2a goes like this. If all inputs are
low, the result of ORing is low; therefore, the final output
32
TABLE 3-2. THREE-INPUT
nor GATE
A
B
c
A + B + C
0
0
0
1
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0
is high. If one or more inputs are high, the result of ORing
is high; so the final output is low.
Table 3-2 summarizes the action of a 3-input nor gate.
As you see, the circuit recognizes only the input word
whose bits are Os. In other words, all inputs must be low
to get a high output.
Four-Input Gate
Figure 3-2 b is the symbol for a 4-input nor gate. The
inputs are ORed, and the result is inverted. For this reason,
the boolean equation is
Y=A+B+C+D (3-3)
The corresponding truth table has input words from 0000
to 1111. Word 0000 gives a 1 output; all other words
produce a 0 output. (For practice, you should construct the
truth table of the 4-input nor gate.)
3-2 DE MORGAN’S FIRST THEOREM
Most mathematicians ignored boolean algbebra when it first
appeared; some even ridiculed it. But Augustus De Morgan
saw that it offered profound insights. He was the first to
acclaim Boole’s great achievement.
Always a warm and likable man, De Morgan himself
had paved the way for boolean algebra by discovering two
important theorems. This section introduces the first theo¬
rem.
The First Theorem
Figure 3-3 a is a 2-input nor gate, analyzed earlier. As you
recall, the boolean equation is
Y = A + B
and Table 3-3 is the truth table.
D—
( a )
Fig. 3-3 De Morgan’s first theorem: («) nor gate; ( b ) and gate
with inverted inputs.
Figure 3-3 b has the inputs inverted before they reach the
and gate. Therefore, the boolean equation is
Y = AB
If both inputs are low in Fig. 3-3 b, the and gate has high
inputs; therefore, the final output is high. If one or more
inputs are high, one or more AND-gate inputs must be low
and the final output is low. Table 3-4 summarizes these
ideas.
TABLE 3-3 TABLE 3-4
A
B
A
B
AB
A + B
0
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
0
Compare Tables 3-3 and 3-4. They’re identical. This
means that the two circuits are logically equivalent; given
the same inputs, the outputs are the same. In other words,
the circuits of Fig. 3-3 are interchangeable.
De Morgan discovered the foregoing equivalence long
before logic circuits were invented. His first theorem says
A + B = AB (3-4)
The left member of this equation represents Fig. 3-3a; the
right member, Fig. 3-3 b. Equation 3-4 says that Fig. 3-3«
and b are equivalent (interchangeable).
Bubbled and Gate
Figure 3-4a shows an and gate with inverted inputs. This
circuit is so widely used that the abbreviated logic symbol
of Fig. 3-4 b has been adopted. Notice that the inverter
triangles have been deleted and the bubbles moved to the
Chapter 3 More Logic Gates 33
:=D-'
(b)
Fig. 3-4 AND gate with inverted inputs: (a) circuit; ( b ) abbreviated
symbol.
AND-gate inputs. From now on, we will refer to Fig.
3-4 b as a bubbled and gate; the bubbles are a reminder of
the inversion that takes place before ANDing.
Fig. 3-5 De Morgan’s first theorem.
Figure 3-5 is a graphic summary of De Morgan’s first
theorem. A nor gate and a bubbled and gate are equivalent.
As shown later, because the circuits are interchangeable,
you can often reduce complicated logic circuits to simpler
forms.
Here’s what really counts. Equation 3-5 says that a 3-
input nor gate and a 3-input bubbled and gate are equivalent
(see Fig. 3-6a). Equation 3-6 means that a 4-input nor
gate and a 4-input bubbled and gate are equivalent (Fig.
3-6 b). Memorize these equivalent circuits; they are a visual
statement of De Morgan’s first theorem.
Notice in Fig. 3-6 b how the input edges of the NOR gate
and the bubbled and gate have been extended. This is
common drafting practice when there are many input signals.
The same idea applies to any type of gate.
EXAMPLE 3-1
Prove that Fig. 3-la and c are equivalent.
Fig. 3-7 Equivalent De Morgan circuits.
SOLUTION
More than Two Inputs
When 3 inputs are involved, De Morgan’s first theorem is
written
A + B + C = ABC (3-5)
For 4 inputs
A + B + C + D = ABCD (3-6)
In both cases, the theorem says that the complement of a
sum equals the product of the complements.
Fig. 3-6 De Morgan’s first theorem: (a) 3-input circuits; ( b) 4-
input circuits.
The final nor gate in Fig. 3-7 a is equivalent to a bubbled
and gate. This allows us to redraw the circuit as shown in
Fig. 3-lb.
Double inversion produces noninversion; therefore, each
double inversion in Fig. 3-lb cancels out, leaving the
simplified circuit of Fig. 3-7c. Figure 3-la and c are
therefore equivalent.
Remember the idea. Given a logic circuit, you can replace
any nor' gate by a bubbled and gate. Then any double
inversion (a pair of bubbles in a series path) cancels out.
Sometimes you wind up with a simpler logic circuit than
you started with; sometimes not.
But the point remains. De Morgan’s first theorem enables
you to rearrange a logic circuit with the hope of finding a
simpler equivalent circuit or perhaps getting more insight
into how the original circuit works.
3-3 NAND GATES
The nand gate has two or more input signals but only one
output signal. All input signals must be high to get a low
output.
34 Digital Computer Electronics
Ial (b)
Fig. 3-8 nand gate: (a) logical meaning; (b) standard symbol.
Two-Input Gate
Figure 3-8 a shows the logical structure of a nand gate, an
and gate followed by an inverter. Therefore, the final
output is not the and of the inputs. Originally called a
not-and gate, the circuit is now referred to as a nand
gate.
Figure 3-8£ is the standard symbol for a nand gate. The
inverter triangle has been deleted and the bubble moved to
the AND-gate output. If one or more inputs are low, the
result of ANDing is low; therefore, the final inverted output
is high. Only when all inputs are high does the ANDing
produce a high signal; then the final output is low.
Table 3-5 summarizes the action of a 2-input nand gate.
As shown, the nand gate recognizes any input word with
one or more Os. That is, one or more low inputs produce
a high output. The boolean equation for a 2-input nand
gate is
Y = AB
(3-7)
TABLE 3-5.
TWO-INPUT
nand GATE
A
B
AB
0
0
1
0
1
1
1
0
1
1
1
0
Four-Input Gate
TABLE 3-6. THREE-
INPUT nand GATE
A
B
c
ABC
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
0
Figure 3-9 b is the symbol for a 4-input nand gate. The
inputs are ANDed, and the result is inverted. Therefore, the
boolean equation is
Y = ABCD (3-9)
If you construct the truth table, you will have input words
from 0000 to 1111. All words from 0000 through 1110
produce a 1 output; only the word 1111 gives a 0 output.
Read this as ‘T equals not AB” If you use this equation, 3-4 DE MORGAN'S SECOND
remember that the ANDing is done first then the inversion. THEOREM
4 — 1
A -
B -
c -
>
>o-y * —
^ c -
D -
zy~ Y
M (b)
Fig. 3-9 nand gates: (a) 3-input; ( b ) 4-input.
Three-Input Gate
Regardless of how many inputs a nand gate has, it’s still
logically equivalent to an and gate followed by an inverter.
For example, Fig. 3-9 a shows a 3-input nand gate. The
inputs are ANDed, and the product is inverted. Therefore,
the boolean equation is
The proof of De Morgan’s second theorem is similar to the
proof given for the first theorem. What follows is a brief
explanation.
The Second Theorem
When two inputs are used, De Morgan’s second theorem
says that
AB = A + B (3-10)
>
In words, the complement of a product equals the sum of
the complements. The left member of this equation repre¬
sents a nand gate (Fig. 3-10a); the right member stands
Y = ABC (3-8)
Here is the analysis of Fig. 3-9a. If one or more inputs
are low, the result of ANDing is low; therefore, the final
output is high. If all inputs are high, the ANDing gives a
high signal; so the final output is low.
Table 3-6 is the truth table for a 3-input nand gate. As
indicated, the circuit recognizes words with one or more
0s. This means that one or more low inputs produce a high
output.
(c)
Fig. 3-10 De Morgan’s second theorem: (a) nand gate; ( b ) or
gate with inverted inputs; (c) bubbled or gate.
Chapter 3 More Logic Gates 3 5
for an or gate with inverted inputs (Fig. 3-106). Therefore,
De Morgan's second theorem boils down to the fact that
Fig. 3-10a and 6 are equivalent.
=0 ■ =£>
Fig. 3-11 De Morgan’s second theorem.
Bubbled or Gate
The circuit of Fig. 3-10 b is so widely used that the
abbreviated logic symbol of Fig. 3-10c has been adopted.
From now on we will refer to Fig. 3-10c as a bubbled or
gate; the bubbles are a reminder of the inversion that takes
place before ORing.
Figure 3-11 is a visual statement of De Morgan’s second
theorem: a nand gate and a bubbled OR gate are equivalent.
This equivalence allows you to replace one circuit by the
other whenever desired. This may lead to a simpler logic
circuit or give you more insight into how the original circuit
works.
More than Two Inputs
When 3 inputs are involved, De Morgan’s second theorem
is written
ABC = A + B + C (3-11)
If 4 inputs are used,
ABCD =A+£+C+D (3-12)
These equations say that the complement of a product
equals the sum of the complements.
(a)
(b)
Fig. 3-12 De Morgan’s second theorem: (a) 3-input circuits; ( b)
4-input circuits.
Figure 3-12 is a visual summary of the second theorem.
Whether 3 or 4 inputs are involved, a nand gate and a
bubbled or gate are equivalent (interchangeable).
EXAMPLE 3-2
Prove that Fig. 3-13a and c are equivalent.
(c)
Fig. 3-13 Equivalent circuits.
SOLUTION
Replace the final nand gate in Fig. 3-13a by a bubbled or
gate. This gives Fig. 3-136. The double inversions cancel
out, leaving the simplified circuit of Fig. 3-13c. Figure
3-13a and c are therefore equivalent. Driven by the same
inputs, either circuit produces the same output as the other.
So if you’re loaded with nand gates, build Fig. 3-13a. If
your shelves are full of and and or gates, build Fig.
3-13c.
Incidentally, most people find Fig. 3-13 b easier to analyze
than Fig. 3-13a. For this reason, if you build Fig. 3-13a,
draw the circuit like Fig. 3-136. Anyone who sees Fig.
3-136 on a schematic diagram knows that the bubbled or
gate is the same as a nand gate and that the built-up circuit
is two nand gates working into a nand gate.
EXAMPLE 3-3
Figure 3-14 shows a circuit called a control matrix . At first,
it looks complicated, but on closer inspection it is relatively
simple because of the repetition of nand gates. De Morgan’s
theorem tells us that nand gates driving nand gates are
equivalent to and gates driving or gates.
The upper set of inputs T ] to T 6 are called timing signals;
only one of them is high at a time. goes high first, then
7 2 , then T 3 , and so on. These signals control the rate and
sequence of computer operations.
The lower set of inputs LDA, ADD , SUB, and OUT are
computer instructions; only one of them is high at a time.
The outputs C P , E P , L M , . . . , to L 0 control different
registers in the computer.
Answer the following questions about the control matrix:
a. Which outputs are high when 7, is high?
b. If T 4 and LDA are high, which outputs are high?
c. When T 6 and SUB are high, which outputs are high?
36 Digital Computer Electronics
SOLUTION
a. Visualize T { high. You can quickly check out each
gate and realize that E P and L M are the only high
outputs.
b. This time T 4 and LDA are high. Check each gate and
you can see that L M and Ej are the only high outputs.
c. When T 6 and SUB are high, the high outputs are L A ,
and E\j.
3-5 EXCLUSIVE-OR GATES
An or gate recognizes words with one or more Is. The
exclusive-or gate is different; it recognizes only words
that have an odd number of Is.
Two Inputs
Figure 3-15a shows one way to build an exclusive-or
gate, abbreviated xor. The upper and gate forms the
product AB, and the lower and gate gives AB . Therefore,
the boolean equation is
Y = AB + AB (3-13)
Here’s what the circuit does. In Fig. 3-15a two low
inputs mean both and gates have low outputs; so the final
output is low. If A is low and B is high, the upper and
gate has a high output; therefore, the final output is high.
Likewise, a high A and low B result in a final output that
is high. If both inputs are high, both and gates have low
outputs and the final output is low.
Table 3-7 shows the truth table for a 2-input exclusive-
or gate. The output is high when A or B is high but not
both; this is why the circuit is known as an exclusive-or
gate. In other words, the output is a 1 only when the inputs
are different.
Chapter 3 More Logic Gates 3 7
TABLE 3-7* TWO-
INPUT xor GATE
A
B
AB + AB
0
0
0
0
1
1
1
o :
1
1
i
0
Logic Symbol and Boolean Sign
Figure 3-15 b is the standard symbol for a 2-input xor gate.
Whenever you see this symbol, remember the action: the
inputs must be different to get a high output.
A word equation for Fig. 3-15 b is
Y = A xor B (3-14)
In boolean algebra the sign © stands for xor addition.
This means that Eq. 3-14 can be written
Y = A © B (3-15)
Read this as “F equals A xor B."
Given the inputs, you can substitute and solve for the
output. For instance, if both inputs are low,
Y = 0 © 0 = 0
because 0 xoRed with 0 gives 0. If one input is low and
the other high,
y = o ® i = i
because 0 xoRed with 1 produces 1. And so on.
Here’s a summary of the four possible xor additions:
0 © 0 = 0
0 © 1 = 1
1 © 0 = I
1 © 1 = 0
Remember these four results; we will be using xor addition
when we get to arithmetic circuits.
Four Inputs
In Fig. 3- 16a the upper gate produces A © B, while the
lower gate gives C © D. The final gate xors both of these
sums to get
Y = (A® B)@(C@D) (3-16)
3 8 Digital Computer Electronics
(a)
(b)
Fig. 3-16 A 4-input exclusive-or gate: (a) circuit with 2-input
xor gates; (b) logic symbol.
It’s possible to substitute input values into the equation and
solve for the output. For instance, if A through C are low
and D is high,
Y = (0 © 0) © (0 © 1)
= 0 © 1
= 1
One way to get the truth table is to plow through all the
input possibilities.
Alternatively, you can analyze Fig. 3-16a as follows. If
all inputs are 0s, the first two gates have 0 outputs; so the
final gate has a 0 output. If A to C are 0s and D is a 1, the
upper gate has a 0 output, the lower gate has a 1 output,
and the final gate has a 1 output. In this way, you can
analyze the circuit action for all input words.
Table 3-8 summarizes the action. Here is an important
property: each input word with an odd number of Is
produces a 1 output. For instance, the first input word to
produce a 1 output is 0001; this word has an odd number
of Is. The next word with a 1 output is 0010; again an odd
number of Is. A 1 output also occurs for these words:
0100, 0111, 1000, 1011, 1101, and 1110, all of which
have an odd number of Is.
The circuit of Fig, 3-16a recognizes words with an odd
number of Is; it disregards words with an even number of
Is. Figure 3-16a is a 4-input xor gate. In this book, we
will use the abbreviated symbol of Fig. 3-16 b to represent
a 4-input xor gate. When you see this symbol, remember
the action: the circuit recognizes words with an odd number
of Is.
Any Number of Inputs
Using 2-input xor gates as building blocks, we can make
xor gates with any number of inputs. For example, Fig.
TABLE 3-8. FOUR-INPUT
xor GATE
Comment
A
B
c
D
Y
Even
0
0
0
0
0
Odd
0
0
0
1
1
Odd
0
0
1
0
1
Even
0
0
1
1
0
Odd
0
1
0
0
1
Even
0
1
0
1
0
Even
0
1
1
0
0
Odd
0
1
1
JL-
Odd
1
0.
~0
0
1
Even
1
0
0
1
o
Even
1
0
1
0
0
Odd
1
0
1
1
l
Even
1
1
0
0
0
Odd
1
1
0
1
i
Odd
1
1
1
0
i
Even
1
1
1
1
0
( 3 ) (b)
Fig. 3-17 xor gates: {a) 3-input; (b) 6-input.
3-11 a shows the abbreviated symbol for a 3-input xor gate,
and Fig. 3-17 b is the symbol for a 6-input xor gate. The
final output of any xor gate is the xor sum of the inputs:
Y = A ®B © C • • • (3-17)
What you have to remember for practical work is this:
an xor gate, no matter how many inputs, recognizes only
words with an odd number of Is.
Parity
Even parity means a word has an even number of Is. For
instance, 110011 has even parity because it contains four
Is. Odd parity means a word has an odd number of Is. As
an example, 110001 has odd parity because it contains
three Is.
Here are two more examples:
1111 0000 1111 0011 (Even parity)
1111 0000 1111 0111 (Odd parity)
The first word has even parity because it contains ten Is;
the second word has odd parity because it contains eleven
Is.
xor gates are ideal for testing the parity of a word, xor
gates recognize words with an odd number of Is. Therefore,
even-parity words produce a low output and odd-parity
words produce a high output.
EXAMPLE 3-4
What is the output of Fig. 3-18 for each of these input
words?
a. 1010 1100 1000 1100
b. 1010 1100 1000 1101
16 bits
ODD
Fig. 3-18 Odd-parity tester.
SOLUTION
a. The word has seven Is, an odd number. Therefore,
the output signal is
ODD =.1
b. The word has eight Is, an even number. Now
ODD = 0
This is an example of an odd-parity tester. An even-
parity word produces a low output. An odd-parity word
results in a high output.
EXAMPLE 3-5
The 7-bit register of Fig. 3-19 stores the letter A in ASCII
form. What does the 8-bit output word equal?
Chapter 3 More Logic Gates 39
bit Instruction or data bits
8-bit word with odd parity
Fig. 3-19 Odd-parity generator.
SOLUTION
The ASCII code for letter A is
100 0001
(see Table 1-6 for the ASCII code). This word has an even
parity, which means that the xor gate has a 0 output.
Because of the inverter, the overall output of the circuit is
the 8-bit word
Because of the 1-bit error, we receive letter C when letter
A was actually sent.
One solution is to transmit an odd-parity bit along with
the data word and have an xor gate test each received
word for odd parity. For instance, with a circuit like Fig.
3-19 the letter A would be transmitted as
1100 0001
An XOR gate will test this word when it is received. If no
error has occurred, the xor gate will recognize the word.
On the other hand, if a 1-bit error has crept in, the xor
gate will disregard the received word and the data can be
rejected.
A final point. When errors come, they are usually 1-bit
errors. This is why the method described catches most of
the errors in transmitted data.
EXAMPLE 3-6
What does the circuit of Fig. 3-20 do?
Fig. 3-20
SOLUTION
1100 0001
Notice that this has odd parity.
The circuit is called an odd-parity generator because it
produces an 8-bit output word with odd parity. If the register
word has even parity, 0 comes out of the xor gate and the
odd-parity bit is 1. On the other hand, if the register word
has odd parity, a 1 comes out of the xor gate and the odd-
parity bit is 0. No matter what the register contents, the
odd-parity bit and the register bits form a new 8-bit word
that has odd parity.
What is the practical application? Because of transients,
noise, and other disturbances, 1-bit errors sometimes occur
in transmitted data. For instance, the letter A may be
transmitted over phone lines in ASCII form:
100 0001 (A)
Somewhere along the line, one of the bits may be changed.
If the X\ bit changes, the received data will be
When INVERT = 0 and A = 0,
Y - 0 © 0 = 0
When INVERT = 0 and A = 1,
Y = 0©1 = 1
In either case, the output is the same as A; that is,
Y = A
for a low INVERT signal.
On the other hand, when INVERT = 1 and A = 0,
Y = 1 © 0 = 1
When INVERT = 1 and A = 1,
100 0011 (C)
Y = 1 © 1 = 0
40 Digital Computer Electronics
This time, the output is the complement of A. As an
equation,
Y = A
for a high INVERT signal.
To summarize, the circuit of Fig. 3-20 does either of
two things. It transmits A when INVERT is 0 and A when
INVERT is 1.
3-6 THE CONTROLLED INVERTER
The preceding example suggests the idea of a controlled
inverter , a circuit that transmits a binary word or its Es
complement.
The l's Complement
Complement each bit in a word and the new word you get
is the l’s complement. For instance, given
1100 0111
the 1 ’s complement is
0011 1000
Each bit in the original word is inverted to get the l’s
complement.
The Circuit
The xor gates of Fig. 3-21 form a controlled inverter
(sometimes called a programmed inverter). This circuit can
transmit the register contents or the l’s complement of the
register contents. As demonstrated in Example 3-6, each
xor gate acts like this. A low INVERT results in
Y„ = A„
and a high INVERT gives
' Y n = A„ U
So each bit is either transmitted or inverted before reaching
the final output.
Visualize the register contents as a word A 7 A 6 ■ • • A 0
and the final output as a word Y 7 Y 6 • • • Y 0 . Then a low
INVERT means
Y 7 Y 6 • Y 0 = A 7 A 6 * * * A 0
On the other hand, a high INVERT results in
Y 7 Y 6 Y 0 = A 7 A 6 * * A 0
As a concrete example, suppose the register word is
A 7 A 6 • • • Ao = 1110 0110
Then, a low INVERT gives an output word of
y 7 y 6 ■ • • Y 0 = 1110 0110
and a high INVERT produces
Y 7 Y 6 • • • Y 0 = 0001 1001
The controlled inverter of Fig. 3-21 is important. Later
you will see how it is used in solving arithmetic and logic
problems. For now, all you need to remember is the key
idea. The output word from a controlled inverter equals the
Chapter 3 More Logic Gates 41
input word when INVERT is low; the output word equals
the l’s complement when INVERT is high.
Boldface Notation
After you understand an idea, it simplifies discussions and
equations if you use a symbol, letter, or other sign to
represent the idea. From now on, boldface letters will stand
for binary words.
For instance, instead of writing
A 7 A 6 • • • A 0 = 1110 0110
we can write
A = 1110 0110
Likewise, instead of
Y 7 Y 6 • • • Y 0 = 0001 1001
the simpler equation
Y = 0001 1001
can be used.
This is another example of chunking. We are replacing
long strings like A 7 A 6 • • • A 0 and Y 7 Y 6 ♦ • • Y 0 by A and
Y. This chunked notation will be convenient when we get
to computer analysis.
This is how to summarize the action of a controlled
inverter:
[A when INVERT = 0
Y “ [A when INVERT = 1
(Note: A boldface letter with an overbar means that each
bit in the word is complemented; if A is a word, A is its
l’s complement.)
3-7 EXCLUSIVE-NOR GATES
The exclusive-nor gate, abbreviated xnor, is logically
equivalent to an xor gate followed by an inverter. For
example, Fig. 3-22 a shows a 2-input xnor gate. Figure
3-22 b is an abbreviated way to draw the same circuit.
(a) (b)
Fig. 3 -22 A 2- input xnor gate: (a) circuit; (b) abbreviated symbol.
TABLE 3-9.
TWO-INPUT
xnor GATE
A
B
F
0
0
1
; 1
0
1
0
1
0
0
1
1
1
Because of the inversion on the output side, the truth
table of an xnor gate is the complement of an xor truth
table. As shown in Table 3-9, the output is high when the
inputs are the same. For this reason, the 2-input xnor gate
is ideally suited for bit comparison , recognizing when two
input bits are identical. (Example 3-7 tells you more about
bit comparison.)
(a) (b)
Fig. 3-23 xnor gates: (a) 3-input; ( b ) 4-input.
Figure 3-23 a is the symbol for a 3-input xnor gate, and
Fig. 3-23 b is the 4-input xnor gate. Because of the inversion
on the output side, these xnor gates perform the comple¬
mentary function of xor gates. Instead of recognizing odd-
parity words, xnor gates recognize even-parity words.
EXAMPLE 3-7
What does the circuit of Fig. 3-24 do?
SOLUTION
The circuit is a word comparator; it recognizes two identical
words. Here is how it works. The leftmost xnor gate
compares A 5 and B 5 \ if they are the same, Y 5 is a 1. The
second xnor gate compares A 4 and # 4 ; if they are the same,
Y 4 is a 1. In turn, the remaining xnor gates compare the
bits that are left, producing a 1 output for equal bits and a
0 output for unequal bits.
If the words A and B are identical, all xnor gates have
high outputs and the and gate has a high EQUAL . If words
A and B differ in one or more bit positions, the and gate
has a low EQUAL.
42 Digital Computer Electronics
1 (
A register
5 4
^3 ^2
A
*0
r
B register
. r '~> i
e 5
S 4
e 3 K
e o
WWW
V
EQUAL
Fig. 3-24 Word comparator.
GLOSSARY
controlled inverter This circuit produces the l’s comple¬
ment of the input word. One application is binary subtrac¬
tion. It is sometimes called a programmed inverter.
De Morgan’s theorems The first theorem says that a nor
gate is equivalent to a bubbled and gate. The second
theorem says that a nand gate is equivalent to a bubbled
or gate.
even parity An even number of Is in a binary word.
nand gate Equivalent to an and gate followed by an
inverter. All inputs must be high to get a low output.
nor gate Equivalent to an or gate followed by an inverter.
All inputs must be low to get a high output.
odd parity An odd number of Is in a binary word.
parity generator A circuit that produces either an odd- or
even-parity bit to go along with the data.
xnor gate Equivalent to an exclusive-or gate followed
by an inverter. The output is high only when the input word
has even parity.
xor gate An exclusive-or gate. It has a high output
only when the input word has odd parity. For a 2-input
xor gate, the output is high only when the inputs are
different.
SELF TESTING REVIEW
Read each of the following and provide the missing words.
Answers appear at the beginning of the next question.
1. A nor gate has two or more input signals. All inputs
must be_to get a high output. A nor
gate recognizes only the input word whose bits are
_The nor gate is logically equivalent to
an or gate followed by an_
2. (low, Os, inverter) De Morgan's first theorem says
that a nor gate is equivalent to a bubbled_
gate.
3. (and) A nand gate is equivalent to an and gate
followed by an inverter. All inputs must be_
to get a low output. De Morgan's second theorem
says that a nand gate is equivalent to a bubbled
-gate.
4. (high, or) An xor gate recognizes only words with
an_number of Is. The 2-input xor gate
has a high output only when the input bits are
_xor gates are ideal for testing parity
because even-parity words produce a_
output and odd-parity words produce a_
output.
5. (odd, different , low, high) An odd-parity generator
produces an odd-parity bit to go along with the data.
Chapter 3 More Logic Gates 43
The parity of the transmitted data is_An 7. (7' s) The exclusive-nor gate is equivalent to an
XOR gate can test each received word for parity, XOR gate followed by an inverter. Because of this,
rejecting words with_parity. even-parity words produce a high output.
6. (odd, even) A controlled inverter is a logic circuit
that transmits a binary word or its_com¬
plement.
PROBLEMS
3-1. In Fig. 3-25 a the two inputs are connected to¬
gether. If A is low, what is Y1 If A is high, what
is F? Does the circuit act like a noninverter or an
inverter?
3-5. The outputs in Fig. 3-27 are cross-coupled back
to the inputs of the jvior gates. If R = 0 and S ■
1, what do Q and Q equal?
3-2. What is the output in Fig. 3-2 5b if both inputs are
low? If one is low and the other high? If both are
high? Does the circuit act like an or gate or an
and gate?
3-3. Figure 3-26 shows a NOR-gate crossbar switch. If
all X and Y inputs are high, which of the Z
outputs is high? If all inputs are high except X x
and Z 2 , which Z output is high? If X 2 and Y 0 are
low and all other inputs are high, which Z output
is high?
3-4. In Fig. 3-26, you want Z 7 to be 1 and all other Z
outputs to be 0. What values must the X and Y
inputs have?
R
*
Fig. 3-27 Cross-coupled nor gates.
3-6. If R = 1 and S = 0 in Fig. 3-27, what does Q
equal? Q1
3-7. Prove that Fig. 3-28 a and b are equivalent.
3-8. What is the output in Fig. 3-28 a if all inputs are
Os. If all inputs are Is?
3-9. What is the output in Fig. 3-28 b if all inputs are
Os. If all inputs are Is?
3-10. A nor has 6 inputs. How many input words are
in its truth table? What is the only input word that
produces a 1 output?
3-11. In Fig. 3-28 a how many input words are there in
the truth table?
3-12. What is the output in Fig. 3-29 if all inputs are
low? If all inputs are high?
44 Digital Computer Electronics
Fig. 3-28
n /?
Fig. 3-29
How many words are in the truth table of Fig.
3-29. What is the value of Y for each of the
following?
a. ABCD = 0011
b. ABCD = 0110
c. ABCD = 1001
d. ABCD = 1100
Which ABCD input words does the circuits of
Fig. 3-29 recognize?
In Fig. 3-30 a the two inputs are connected to¬
gether. If A = 0 what does Y equal? If A = 1,
what does Y equal? Does the circuit act like a
noninverter or an inverter?
b. If all inputs are low except X 2 and Y u which
Z output is low?
c. If all inputs are low except X 0 and Y 2 , which
Z output is low?
d. To get a low Z 8 output, which inputs must be
high?
3 - 18 . In Fig. 3-31, what are the outputs if R = 0 and
5 = 1 ?
Fig. 3-31 Cross-coupled nand gates.
3 - 19 . If R = J. and S = 0 in Fig. 3-31, what does Q
equal? Q ?
3 - 20 . What is the output in Fig. 3-32a if all inputs are
0s? If all inputs are Is?
3 - 21 . How many input words are there in the truth table
of Fig. 3-32 al ^ .. A i M , * , - -.
Fig. 3-30
What is the output in Fig. 3-30Z? if both inputs are
low? If one input is low and the other high? If
both are high? Does the circuit act like an or gate
or an and gate?
Suppose the nor gates of Fig. 3-26 are replaced
by nand gates. Then you’ve got a NAND-gate
crossbar switch.
a. If all X and Y inputs are low, which Z output
is low?
Fig. 3-32
Chapter 3 More Logic Gates 45
3-22. Prove that Fig. 3-32 a and b are equivalent.
3-23. What is the output in Fig. 3-33 if all inputs are
low? If they are all high?
3-24. How many words are in the truth table of Fig.
3-33? What does Y equal for each of the follow¬
ing:
a. ABCDE = 00111
b. ABCDE = 10110
c. ABCDE - 11010
d. ABCDE = 10101
3-25. In Fig. 3-34 the inputs are 7 4 , JMP, JAM, JAZ,
A M9 and A z ; the output is L P . What is the output
for each of these input conditions?
a. All inputs are 0s.
b. All inputs are low except T 4 and JMP.
Fig. 3-33
c. All inputs are low except T 4 , JAZ , and A z .
d. The only high inputs are T 4 , JAM , and A M ,
3-26. Figure 3-35 shows the control matrix discussed in
Example 3-3. Only one of the timing signals T x to
T 6 is high at a time. Also, only one of the instruc¬
tions, LDA to OUT , is high at a time. Which are
the high outputs for each of the following condi-
tions?
a.
T, high
g-
T 5 and ADD high
b.
T 2 high
h.
T 6 and ADD high
c.
f 3 high
i.
T 4 and SUB high
d.
7 4 and LDA high
j*
T 5 and SUB high
e.
T s and LDA high
k.
T 6 and SUB high
f.
r 4 and ADD high
1 .
T 4 and OUT high
T 2 r 3 t a T 5 t 6
46 Digital Computer Electronics
3-27. Figure 3-36 shows a binary-to-Gray-code con¬
verter. (Gray code is a special code used in ana-
log-to-digital conversions.) The input word is
X 4 X 3 • • • X 0 , and the output word is Y 4 Y 3 • * •
Y 0 . What does the output word equal for each of
these inputs?
a.
X 4 X 3 • •
x 0 = 10011
b.
X 4 X 3 • •
Xo = 01110
c.
X 4 X 3 • •
■ x 0 = 10101
d.
X 4 X 3 • • •
■ Xo = 11100
Fig. 3-36 Binary-to-Gray-code converter.
3-28. How many input words are there in the truth table
of an 8-input xor gate?
3-29. How can you modify Fig. 3-19 so that it produces
an 8-bit output word with even parity?
3-30. In the controlled inverter of Fig. 3-21, what is the
output word Y for each of these conditions?
a. A = 1100 1111 and INVERT = 0
b. A = 0101 0001 and INVERT = 1
c. A = 1110 1000 and INVERT = 1
d. A = 1010 0101 and INVERT = 0
3-31. The inputs A and B of Fig. 3-37 produce outputs
of CARRY and SUM. What are the values of
CARRY and SUM for each of these inputs?
a. A = 0 and B ~ 0
b. A = 0 and B = 1
c. A = 1 and B - 0
d. A = 1 and B = 1
A B
Fig. 3-37
3-32. In Fig. 3-37, what is the boolean equation for
CARRY ? For SUM?
3-33. What is the l’s complement for each of these
numbers?
a. 1100 0011
b. 1010 11110011
c. 1110 0001 1010 0011
d. 0000 1111 0010 1101
3-34. What is the output of a 16-input xnor gate for
each of these input words?
a. 0000 0000 0000 1111
b. 1111 0101 1110 1100
c. 0101 1100 0001 0011
d. 1111 0000 1010 0110
3-35. The boolean equation for a certain logic circuit is
Y = AB + CD + AC. What does Y equal for
each of the following:
a.
ABCD -
0000
b.
ABCD =
0101
C.
ABCD -
1010
d.
ABCD =
1001
Chapter 3 More Logic Gates 47
=D-
TTL Circuits
In 1964 Texas Instruments introduced transistor-transistor
logic (TTL), a widely used family of digital devices. TTL
is fast, inexpensive, and easy to use. This chapter concen¬
trates on TTL because once you are familiar with it, you
can branch out to other logic families and technologies.
4-1 DIGITAL INTEGRATED
CIRCUITS
Using advanced photographic techniques, a manufacturer
can produce miniature circuits on the surface of a chip (a
small piece of semiconductor material). The finished net¬
work is so small you need a microscope to see the
connections. Such a circuit is called an integrated circuit
(IC) because the components (transistors, diodes, resistors)
are an integral part of the chip. This is different from a
discrete circuit, in which the components are individually
connected during assembly.
Levels of Integration
Small-scale integration (SSI) refers to ICs with fewer than
12 gates on the same chip. Medium-scale integration (MSI)
means from 12 to 100 gates per chip. And large-scale
integration (LSI) refers to more than 100 gates per chip.
The typical microcomputer has its microprocessor, memory,
and I/O circuits on LSI chips; a number of SSI and MSI
chips are used to support the LSI chips.
Technologies and Families
The two basic technologies for manufacturing digital ICs
are bipolar and MOS. The first fabricates bipolar transistors
on a chip; the second, MOSFETS. Bipolar technology is
preferred for SSI and MSI because it is faster. MOS
technology dominates the LSI field because more MOSFETs
can be packed on the same chip area.
A digital family is a group of compatible devices with
the same logic levels and supply voltages (“compatible”
means that you can connect the output of one device to the
input of another). Compatibility permits a large number of
different combinations.
Bipolar Families
In the bipolar category are these basic families:
DTL Diode-transistor logic
TTL Transistor-transistor logic
ECL Emitter-coupled logic
DTL uses diodes and transistors; this design, once popular,
is now obsolete. TTL uses transistors almost exclusively;
it has become the most popular family of SSI and MSI
chips. ECL, the fastest logic family, is used in high-speed
applications.
MOS Families
In the MOS category are these families:
PMOS p-Channel MOSFETs
NMOS n-Channel MOSFETs
CMOS Complementary MOSFETs
PMOS, the oldest and slowest type, is becoming obsolete.
NMOS dominates the LSI field, being used for micropro¬
cessors and memories. CMOS, a push-pull arrangement of
n- and p-channel MOSFETs, is extensively used where low
power consumption is needed, as in pocket calculators,
digital wristwatches, etc.
4-2 7400 DEVICES
The 7400 series, a line of TTL circuits introduced by Texas
Instruments in 1964, has become the most widely used of
all bipolar ICs. This TTL family contains a variety of SSI
and MSI chips that allow you to build all kinds of digital
circuits and systems.
48
Fig. 4-1 Standard TTL nand gate.
Standard TTL
Figure 4-1 shows a TTL nand gate. The multiple-emitter
input transistor is typical of all the gates and circuits in the
7400 series. Each emitter acts like a diode; therefore, Q,
and the 4-kfl resistor act like a 2-input and gate. The rest
of the circuit inverts the signal; therefore, the overall circuit
acts like a 2-input nand gate.
The output transistors (Q 3 and Q 4 ) form a totem-pole
connection, typical of most TTL devices. Either one or the
other is on. When Q 3 is on, the output is high; when Q 4 is
on, the output is low. The advantage of a totem-pole
connection is its low output impedance.
Ideally, the input voltages A and B are either low
(grounded) or high (5 V). If A or B is low, Q, saturates.
This reduces the base voltage of Q 2 to almost zero.
Therefore, Q 2 cuts off, forcing Q 4 to cut off. Under these
conditions, Q 3 acts like an emitter follower and couples a
high voltage to the output.
On the other hand, when both A and B are high, the
collector diode of Q : goes into forward conduction; this
forces Q 2 and Q 4 into saturation, producing a low output.
Table 4-1 summarizes all input and output conditions.
Incidentally, without diode D l in the circuit, Q 3 would
conduct slightly when the output is low. To prevent this,
the diode is inserted; its voltage drop keeps the base-emitter
TABLE 4-1.
TWO-
INPUT
NAND GATE
A
B
Y
0
0
1
0
1
1
1
0
1
1
1
0
diode of Q 3 reverse-biased. In this way, only Q 4 conducts
when the output is low.
Totem-Pole Output
Why are totem-pole transistors used? Because they produce
a low output impedance. Either Q 3 acts like an emitter
follower (high output) or Q 4 is saturated (low output).
Either way, the output impedance is very low. This is
important because it reduces the switching time. In other
words, when the output changes from low to high, or vice
versa, the low output impedance implies a short RC time
constant; this short time constant means that the output
voltage can change quickly from one state to the other.
Propagation Delay Time and Power Dissipation
Two quantities needed for our later discussions are power
dissipation and propagation delay time. A standard TTL
gate has a power dissipation of about \0 mW. It may vary
from this value because of signal levels, tolerances, etc.,
but on the average, it’s 10 mW per gate.
The propagation delay time is the amount of time it takes
for the output of a gate to change after the inputs have
changed. The propagation delay time of a TTL gate is in
the vicinity of 10 ns.
Device Numbers
By varying the design of Fig. 4-1 manufacturers can alter
the number of inputs and the logic function. The multiple-
emitter inputs and the totem-pole outputs are still used, no
matter what the design. (The only exception is an open
collector, discussed later.)
Table 4-2 lists some of the 7400-series TTL gates. For
instance, the 7400 is a chip with four 2-input nand gates
in one package. Similarly, the 7402 has four 2-input nor
gates, the 7404 has six inverters, and so on.
TABLE 4-2. STANDARD TTL
Device number
Description
7400
Quad 2-input nand gates
7402
Quad 2-input nor gates
7404
Hex inverter
7408
Quad 2-input and gates
7410
Triple 3-input nand gates
7411
Triple 3-input and gates
7420
Dual 4-input nand gates
7421
Dual 4-input and gates
7427
Triple 3-input nor gates
7430
8-input nand gate
7486
Quad 2-input xor gates
Chapter 4 TTL Circuits 49
5400 Series
Any device in the 7400 series works over a temperature
range of 0° to 70°C and over a supply range of 4.75 to
5.25 V. This is adequate for commercial applications. The
5400 series, developed for the military applications, has
the same logic functions as the 7400 series, except that it
works over a temperature range of —55 to 125°C and over
a supply range of 4.5 to 5.5 V. Although 5400-series
devices can replace 7400-series devices, they are rarely
used commercially because of their much higher cost.
High-Speed TTL
The circuit of Fig. 4-1 is called standard TTL. By decreasing
the resistances a manufacturer can lower the internal time
constants; this decreases the propagation delay time. The
smaller resistances, however, increase the power dissipa¬
tion. This variation is known as high-speed TTL. Devices
of this type are numbered 74H00, 74H01, 74H02, and so
on. A high-speed TTL gate has a power dissipation around
22 mW and a propagation delay time of approximately 6
ns.
Low-Power TTL
By increasing the internal resistances a manufacturer can
reduce the power dissipation of TTL gates. Devices of this
type are called low-power TTL and are numbered 74L00,
74L01, 74L02, etc. These devices are slower than standard
TTL because of the larger internal time constants. A low-
power TTL gate has a power dissipation of approximately
1 mW and a propagation delay time around 35 ns.
Schottky TTL
With standard TTL, high-speed TTL, and low-power TTL,
the transistors go into saturation causing extra carriers to
flood the base. If you try to switch this transistor from
saturation to cutoff, you have to wait for the extra carriers
to flow out of the base; the delay is known as the saturation
delay time.
One way to reduce saturation delay time is with Schottky
TTL. The idea is to fabricate a Schottky diode along with
each bipolar transistor of a TTL circuit, as shown in Fig.
4-2. Because the Schottky diode has a forward voltage of
only 0.4 V, it prevents the transistor from saturating fully.
This virtually eliminates saturation delay time, which means
better switching speed. This variation is called Schottky
TTL; the devices are numbered 74S00, 74S01, 74S02, and
so forth.
Schottky TTL devices are very fast, capable of operating
reliably at 100 MHz. The 74S00 has a power dissipation
around 20 mW per gate and a propagation delay time of
approximately 3 ns.
Low-Power Schottky TTL
By increasing internal resistances as well as using Schottky
diodes manufacturers have come up with the best compro¬
mise between low power and high speed: low-power Schottky
TTL. Devices of this type are numbered 74LS00, 74LS01,
74LS02, etc. A low-power Schottky gate has a power
dissipation of around 2 mW and a propagation delay time
of approximately 10 ns, as shown in Table 4-3.
Standard TTL and low-power Schottky TTL are the
mainstays of the digital designer. In other words, of the
five TTL types listed in Table 4-3, standard TTL and low-
power Schottky TTL have emerged as the favorites of the
digital designers. You will see them used more than any
other bipolar types.
4-3 TTL CHARACTERISTICS
7400-series devices are guaranteed to work reliably over a
temperature range of 0 to 70°C and over a supply range of
4.75 to 5.25 V. In the discussion that follows, worst case
means that the parameters (characteristics like maximum
input current, minimum output voltage, and so on) are
measured under the worst conditions of temperature and
voltage—maximum temperature and minimum voltage for
some parameters, minimum temperature and maximum
voltage for others, or whatever combination produces the
worst values.
Floating Inputs
When a TTL input is low or grounded, a current l E
(conventional direction) exists in the emitter, as shown in
TABLE 4-3. TTL POWER-DELAY VALUES
Type
Power,
mW
Delay time,
ns
Low-power
1
35
Low-power Schottky
2
10
Standard
10
10
High-speed
22
6
Schottky
20
3
o
*sF—■■
Fig. 4-2 Schottky diode prevents transistor saturation.
50 Digital Computer Electronics
+5 V
+5 V
f
(c) i • . . (d)
( „■? , ’ '
Fig. 4-3 Open or floating input is the same as a high input.
Fig. 4-3a. On the other hand, when a TTL input is high
(Fig. 4-36), the emitter diode cuts off and the emitter
current is approximately zero.
When a TTL input is floating (unconnected), as shown
in Fig. 4-3c, no emitter current is possible. Therefore, a
floating TTL input is equivalent to a high input. In other
words, Fig. 4-3c produces the same output as Fig. 4-36.
This is important to remember. In building circuits any
floating TTL input will act like a high input .
Figure 4-3d emphasizes the point. The input is floating
and is equivalent to a high input; therefore, the output of
the inverter is low.
Fig. 4-4 TTL inverter.
Worst-Case Input Voltages
Figure 4-4 shows a TTL inverter with an input voltage of
Vj and an output voltage of V Q . When V, is 0 V (grounded),
the output voltage is high. With TTL devices, we can raise
V{ to 0.8 V and still have a high output. The maximum
low-level input voltage is designated V IL . Data sheets list
this worst-case low input as
V IL = 0.8 V
Take the other extreme. Suppose V, is 5 V in Fig. 4-4.
This is a high input; therefore, the output of the inverter is
low. Vj can decrease all the way down to 2 V, and the
output will still be low. Data sheets list this worst-case
high input as
In other words, any input voltage from 2 to 5 V is a high
input for TTL devices.
Worst-Case Output Voltages
Ideally, 0 V is the low output, and 5 V is the high output.
We cannot attain these ideal values because of internal
voltage drops. When the output is low in Fig. 4-4, Q 4 is
saturated and has a small voltage drop across it. With TTL
devices, any voltage from 0 to 0.4 V is a low output.
When the output is high. Q 3 acts like an emitter follower.
Because of the drop across Q 3 , D u and the 130-0 resistor,
the output is less than 5 V. With TTL devices, a high
output is between 2.4 and 3.9 V, depending on the supply
voltage, temperature, and load.
This means that the worst-case output values are
V OL = 0.4 V - 2.4 V
Table 4-4 summarizes the worst-case values. Remember
that they are valid over the temperature range (0 to 70°C)
and supply range (4.75 to 5.25 V).
Compatibility
The values shown in Table 4-4 indicate that TTL devices
are compatible. This means that the output of a TTL device
can drive the input of another TTL device, as shown in
Fig. 4 -5a. To be specific, Fig. 4-56 shows a low TTL
output (0 to 0.4 V). This is low enough to drive the second
TTL device because any input less than 0.8 V is a low
input.
TABLE 4-4. TTL STATES (WORST
CASE)
Output, V
Input, V
Low
0.4
0.8
High
2.4
2
Chapter 4 TTL Circuits 51
TTL
TTL
device
Vo
V,
device
(a)
Similarly, Fig. 4-5 c shows a high TTL output (2.4 to
3.9 V). This is more than enough to drive the second TTL
because any input greater than 2 V is a high input.
Noise Margin
In the worst case, there is a margin of 0,4-Y between the
driver and the load in Fig. 4-5 b and c. This difference,
called the noise margin , represents protection against noise.
In other words, the connecting wire between a TTL driver
and a TTL load may pick up stray noise voltages. As long
as these induced voltages are less than 0.4 V, we get no
false triggering of the TTL load.
Sourcing and Sinking
When a standard TTL output is low (Fig. 4-5 b), an emitter
current of approximately 1.6 mA (worst case) exists in the
direction shown. The charges flow from the emitter of Qj
to the collector of Q 4 . Because it is saturated, Q 4 acts like
a current sink; charges flow through it to ground like water
flowing down a drain.
On the other hand, when a standard TTL output is high
(Fig. 4-5c), a reverse emitter current of 40 jjlA (worst case)
exists in the direction shown. Charges flow from Q 3 to the
emitter of Q L . In this case, Q 3 is acting like a source.
Data sheets lists the worst-case input currents as
l lL = —1.6 mA Ii H = 40 jxA
The minus sign indicates that the current is out of the
device; plus means the current is into the device. All data
sheets use this convention.
Standard Loading
A TTL device can source current (high output) or it can
sink current (low output). Data sheets of standard TTL
devices indicate that any 7400-series device can sink up to
16 mA, designated as
I OL = 16 mA
and can source up to 400 |aA, designated
I oh = -400 |jlA
(Again, a minus sign means that the current is out of the
device and a plus sign means that it’s into the device.)
A single TTL load has a low-level input current of 1.6
mA (Fig., 4-5 b) and a high-level input current of 40 |aA
(Fig. 4-5c). Since the maximum output currents are 10
times as large, we can connect up to 10 TTL emitters to
any TTL output.
Figure 4-6a illustrates a low output. Here you see the
TTL driver sinking 16 mA, the sum of 10 TTL load
currents. In this state, the output voltage is guaranteed to
be 0.4 V or less. If you try connecting more than 10
emitters, the output voltage may rise above 0.4 V.
Figure 4-6 b shows a high output with the driver sourcing
400 jxA for 10 TTL loads of 40 pA each. For this maximum
loading, the output voltage is guaranteed to be 2.4 V or
more under worst-case conditions.
Loading Rules
The maximum number of TTL emitters that can be reliably
driven under worst-case conditions is called the fanout.
With standard TTL, the fanout is 10, as shown in Fig.
4-6. Sometimes, we may want to use a standard TTL device
to drive low-power Schottky devices. In this case, the
fanout increases because low-power Schottky devices have
less input current.
52 Digital Computer Electronics
(a)
the right. Pick the driver, pick the load, and read the fanout
at the intersection of the two. For instance, the fanout of a
standard device (74) driving low-power Schottky devices
(74LS) is 20. As another example, the fanout of a low-
power device (74L) driving high-speed devices (74H) is
only 1.
4-4 TTL OVERVIEW
Let’s take a look at the logic functions available in the
7400 series. This overview will give you an idea of the
variety of gates and circuits found in the TTL family. As
guide, Appendix 3 lists some of the 7400-series devices.
You will find it useful when looking for a device number
or logic function.
Fig. 4-6 Fanout of standard TTL devices: (a) low output; ( b )
high output.
By examining data sheets for the different TTL types we
can calculate the fanout for all possible combinations. Table
4-5 summarizes these fanouts, which may be useful if you
ever have to mix TTL types.
Read Table 4-5 as follows. The series numbers have
been abbreviated; 74 stands for 7400 series, 74H for 74H00
series, and so forth. Drivers are on the left and loads on
TABLE 4-5. FANOUTS
TTL
TTL load
driver
74
74H
74L
74S
74LS
74
10
8
40
8
20
74H
12
10
50
10
25
74L
2
1
20
1
10
74S
12
10
100
10
50
74LS
5
4
40
4
20
Fig. 4-7 Three, four, and eight inputs.
nand Gates
To begin with, the nand gate is the backbone of the entire
series. All devices in the 7400 series are derived from the
2-input nand gate shown in Fig. 4-1. To produce 3-, 4-,
and 8-input nand gates the manufacturer uses 3-, 4 -, and
8-emitter transistors, as shown in Fig. 4-7. Because they
are so basic, nand gates are the least expensive devices in
the 7400 series.
nor Gates
To get other logic functions the manufacturer modifies the
basic NAND-gate design. For instance, Fig. 4-8 shows a 2-
input nor gate. Qj, Q 2 , Q 3 , and Q 4 are the same as in the
basic design. Q 5 and Q 6 have been added to produce ORing.
Notice that Q 2 and Q 6 are in parallel, the key to the ORing
followed by inversion to get NORing.
Chapter 4 TTL Circuits 53
The input currents are the same as those of a standard nand
gate, but the output currents are 3 times as high, which
means that the 7437 can drive heavier loads.
Appendix 3 includes several other buffer-drivers.
'U-
u
(a)
Fig. 4-9 Seven-segment display.
When A and B are both low, Q { and Q 5 are saturated;
this cuts off Q 2 and Q 6 . Then Q 3 acts like an emitter
follower and we get a high output.
If A or B or both are high, Q! or Q 5 or both are cut off,
forcing Q 2 or Q 6 or both to turn on. When this happens,
Q 4 saturates and pulls the output down to a low voltage.
With more transistors, manufacturers can produce 3- and
4-input nor gates. (A TTL 8-input nor gate is not available.)
and and OR Gates
To produce the and function, another common-emitter
stage is inserted before the totem-pole output of the basic
nand gate design. The extra inversion converts the nand
gate to an and gate. Similarly, another CE stage can be
inserted before the totem-pole output of Fig. 4-8; this
converts the nor gate to an or gate.
Buffer-Drivers
A buffer is a device that isolates two other devices.
Typically, a buffer has a high input impedance and a low
output impedance. In terms of digital ICs, this means a low
input current and a high output current.
Since the output current of a standard TTL gate can be
10 times the input current, a basic gate does a certain
amount of buffering (isolating). But it’s only when the
manufacturer optimizes the design for high output currents
that we call a device a buffer or driver.
As an example, the 7437 is a quad 2-input nand buffer,
meaning four 2-input nand gates optimized to get high
output currents. Each gate has the following worst-case
values of input and output currents:
I 1L = —1.6 mA I IH = 40 \xA
/ ol — 48 mA I oh — 1.2 mA
Encoders and Decoders
A number of TTL chips are available for encoding and
decoding data. For instance, the 74147 is a decimal-to-
BCD encoder. It has 10 input lines (decimal) and 4 output
lines (BCD). As another example, the 74154 is a l-of-16
decoder. It has 4 input lines (binary) and 16 output lines
(hexadecimal).
Seven-segment decoders (7446, 7447, etc.) are useful for
decimal displays. They convert a BCD nibble into an output
that can drive a seven-segment display. Figure 4-9 a illus¬
trates the idea behind a seven-segment LED display. It has
seven separate LEDs that allow you to display any digit
between 0 and 9. To display a 7, the decoder will turn on
LEDs a, b, and c (Fig. 4-9 b).
Seven-segment displays are not limited to decimal num¬
bers. For instance, in some microprocessor trainers, seven-
segment displays are used to indicate hexadecimal digits.
Digits A, C, E, and F are displayed in uppercase form;
digit B is shown as a lowercase b (LEDs c, d, e, f, g); and
digit D as a lowercase d (LEDs b , c , e , g).
Schmitt Triggers
When a computer is running, the outputs of gates are
rapidly switching from one state to another. If you look at
these signals with an oscilloscope, you see signals that
ideally resemble rectangular waves like Fig. 4-10a.
When digital signals are transmitted and later received,
they are often corrupted by noise, attenuation, or other
factors and may wind up looking like the ragged waveform
shown in Fig. 4-10 b. If you try to use these nonrectangular
signals to drive a gate or other digital device, you get
unreliable operation.
This is where the Schmitt trigger comes in. It designed
to clean up ragged looking pulses, producing almost vertical
54 Digital Computer Electronics
(c)
Fig. 4-10 Schmitt trigger produces rectangular output.
(b) (c)
Fig. 4-11 (a) Hex Schmitt-trigger inverters; ( b ) 4-input nand
Schmitt trigger; (c) 2-input nand Schmitt trigger.
transitions between the low and high state, and vice versa
(Fig. 4-10c). In other words, the Schmitt trigger produces
a rectangular output, regardless of the input waveform.
The 7414 is a hex Schmitt-trigger inverter, meaning six
Schmitt-trigger inverters in one package like Fig. 4-11 a.
Notice the hysteresis symbol inside each inverter; it des¬
ignates the Schmitt-trigger function.
Two other TTL Schmitt triggers are available. The 7413
is a dual 4-input nand Schmitt trigger, two Schmitt-trigger
gates like Fig. 4-11 b. The 74132 is a quad 2-input nand
Schmitt trigger, four Schmitt-trigger gates like Fig. 4-1 lc.
Other Devices
The 7400 series also includes a number of other devices
that you will find useful, such as and-or-invert gates
(discussed in the next section), latches and flip-flops (Chap.
7), registers and counters (Chap. 8), and memories (Chap.
9).
4-5 AND-OR-INVERT GATES
Figure 4-12a shows an and-or circuit. Figure 4-12 b shows
the De Morgan equivalent circuit, a nand-nand network.
In either case, the boolean equation is
Y = AB + CD (4-1)
Since nand gates are the preferred TTL gates, we would
build the circuit of Fig. 4-12 b. nand-nand circuits like
this are important because with them you can build any
desired logic circuit (discussed in Chap. 5).
TTL Devices
Is there any TTL device with the output given by Eq. 4-1?
Yes, there are some and-or gates but they are not easily
derived from the basic NAND-gate design. The gate that is
easy to derive and comes close to having an expression like
Eq. 4-1 is the and-or-invert gate shown in Fig. 4-12c.
In other words, a variety of circuits like this are available
on chips. Because of the inversion, the output has an
equation of
Y = AB + CD (4-2)
(c)
Fig. 4-12 (a) and-or circuit; ( b ) nand-nand circuit; ( c ) and-
or-invert circuit.
Chapter 4 TTL Circuits 5 5
Fig. 4-13 and-or-invert schematic diagram.
Figure 4-13 shows the schematic diagram of a TTL and-
or-invert gate. Qi, Q 2j Q3, and Q 4 form the basic 2-input
nand gate of the 7400 series. By adding Q 5 and Q 6 we
convert the basic nand gate to an and-or-invert gate.
Qj and Q 5 act like 2-input and gates; Q 2 and Q 6 produce
ORing and inversion. Because of this, the circuit is logically
equivalent to Fig. 4-12c.
In Table 4-6, listing the and-or-invert gates available
in the 7400 series, 2-wide means two and gates across, 4-
wide means four and gates across, and so on. For instance,
the 7454 is a 2-input 4-wide and-or-invert gate like Fig.
4-14a; each and gate has two inputs (2-input) and there
are four and gates (4-wide). Figure 4-14b shows the 7464;
it is a 2-2-3-4-input 4-wide and-or-invert gate.
When we want the output given by Eq. 4-1, we can
connect the output of a 2-input 2-wide and-or-invert gate
to another inverter. This cancels out the internal inversion,
giving us the equivalent of an and-or circuit (Fig. 4-12a)
or a nand-nand network (Fig. 4-12b).
Expandable and-or-invert Gates
The widest and-or-invert gate available in the 7400 series
is 4-wide. What do we do when we need a 6- or 8-wide
circuit? One solution is to use an expandable and-or-
invert gate.
TABLE 4-6. and-or-invert GATES
Device
Description
7451
Dual 2-input 2-wide
7454
2-input 4-wide
7459
Dual 2-3 input 2-wide
7464
2-2-3-4 input 4-wide
5 6 Digital Computer Electronics
(b)
Fig. 4-14 Examples of and-or-invert circuits.
Figure 4-15a shows the schematic diagram of an ex¬
pandable and-or-invert gate. The only difference between
this and the preceding and-or-invert gate (Fig. 4-13) is
collector and emitter tie points brought outside the package.
Since Q 2 and Q 6 are the key to the ORing operation, we are
being given access to the internal ORing function. By
connecting other gates to these new inputs we can expand
the width of the and-or-invert gate.
Figure 4-15b shows the logic symbol for an expandable
and-or-invert gate. The arrow input represents the emitter,
and the bubble stands for the collector. Table 4-7 lists the
expandable and-or-invert gates in the 7400 series.
Expanders
What do we connect to the collector and emitter inputs of
an expandable gate? The output of an expander like Fig.
4-16a. The input transistor acts like a 4-input and gate.
The output transistor is a phase splitter; it produces two
TABLE 4-7. EXPANDABLE and-or-
invert GATES
Device
Description
7450
Dual 2-input 2-wide
7453
2-input 4-wide
7455
4-input 2-wide
Collector
Fig. 4-15 (a) Expandable and-or-invert gate; ( b ) logic symbol.
(b)
O 1
(e)
(c) {d)
Fig. 4-16 (a) Expander; (b) symbol for expander; (c) expander
driving expandable and-or-invert gate; (d) and-or-invert cir¬
cuit; ( e ) expandable and-or-invert with two expanders.
output signals, one in phase (emitter) and the other inverted
(collector). Figure 4-16 b shows the symbol of a 4-input
expander.
Visualize the outputs of Fig. 4-16 a connected to the
collector and emitter inputs of Fig. 4-15a. Then Q 8 is in
parallel with Q 2 and Q 6 . Figure 4-16c shows the logic
circuit. This means that the expander outputs are being
ORed with the signals of the and-or-invert gate. In other
words, Fig. 4-16c is equivalent to the and-or-invert
circuit of Fig. 4-16 d.
We can connect more expanders. Figure 4-16c shows
two expanders driving the expandable gate. Now we have
a 2-2-4-4-input 4-wide and-or-invert circuit.
The 7460 is a dual 4-input expander. The 7450, a dual
expandable and-or-invert gate, is designed for use with
up to four 7460 expanders. This means that we can add
two more expanders in Fig. 4-16c to get a 2-2-4-4-4-4-
input 6-wide and-or-invert circuit.
Chapter 4 TTL Circuits 5 7
4-6 OPEN-COLLECTOR GATES
Instead of a totem-pole output, some TTL devices have an
open-collector output. This means they use only the lower
transistor of a totem-pole pair. Figure 4-lla shows a 2-
input nand gate with an open-collector output. Because
the collector of Q 4 is open, a gate like this won’t work
properly until you connect an external pull-up resistor,
shown in Fig. 4-176.
(a)
+5 v
Putl-up
resistor
f - 0 /
(b)
Fig. 4-17 Open-collector TTL: (a) circuit; ( b ) with pull-up resistor.
The outputs of open-collector gates can be wired together
and connected to a common pull-up resistor. This is known
as wire-or. The big disadvantage of open-collector gates
is their slow switching speed.
Open-collector gates are virtually obsolete because a new
device called the three-state switch appeared in the early
1970s. Section 8-8 discusses three-state switches in detail.
4-7 MULTIPLEXERS
Multiplex means “many into one.” A multiplexer is a
circuit with many inputs but only one output. By applying
control signals we can steer any input to the output.
Data Selection
Figure 4-18 shows a 16-to-l multiplexer, also called a data
selector. The input data bits are D 0 to D l5 . Only one of
these is transmitted to the output. Control word ABCD
determines which data bit is passed to the output. For
instance, when
ABCD = 0000
the upper and gate is enabled but all other and gates are
disabled. Therefore, data bit D 0 is transmitted to the output,
giving
Y = D 0
If the control word is changed to
ABCD =1111
the bottom gate is enabled and all other gates are disabled.
In this case,
Y = D l5
Boolean Function Generator
Digital design often starts with a truth table. The problem
then is to come up with an equivalent logic circuit.
Multiplexers give us a simple way to transform a truth table
into an equivalent logic circuit. The idea is to use input
data bits that are equal to the desired output bits of the
truth table.
For example, look at the truth table of Table 4-8. When
the input word ABCD is 0000, the output is 0; when ABCD
TABLE 4-8
A
B
c
D
Y
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
1
1
1
1
1
0
58 Digital Computer Electronics
Chapter 4 TTL Circuits 59
ABCD
Fig. 4-19 Generating a boolean function.
= 0001, the output is 1; when ABCD = 0010, the output
is 0; and so on. Figure 4-19 shows how to set up a
multiplexer with the foregoing truth table. When ABCD
= 0000, data bit 0 is steered to the output; when ABCD
= 0001, data bit 1 is steered to the output; when ABCD
= 0010, data bit 0 is steered to the output; and so forth.
As a result, the truth table of this circuit is the same as
Table 4-8.
Universal Logic Circuit
The 74150 is a 16-to-l multiplexer. This TTL device is a
universal logic circuit because you can use it to get the
hardware equivalent of any four-variable truth table. In
other words, by changing the input data bits the same IC
can be made to generate thousands of different truth tables.
Multiplexing Words
Figure 4-20 illustrates a word multiplexer that has two input
words and one output word. The input word on the left is
L 3 L 2 L 1 L 0 and the one on the right is R 3 R 2 RiR 0 . The control
signal labeled RIGHT selects the input word that will be
transmitted to the output. When RIGHT is low, the four
nand gates on the left are activated; therefore,
OUT = L 3 L 2 L 1 L 0
When RIGHT is high,
OUT — R^R 2 RiR 0
The 74157 is TTL multiplexer with an equivalent circuit
like Fig. 4-20. Appendix 3 lists other multiplexers available
in the 7400 series.
_ GLOSSARY _
bipolar Having two types of charge carriers: free electrons fanout The maximum number of TTL loads that a TTL
and holes. device can drive reliably over the specified temperature
chip A small piece of semiconductor material. Sometimes, range.
chip refers an IC device including its pins. low-power Schottky TTL A modification of standard TTL
60 Digital Computer Electronics
in which larger resistances and Schottky diodes are used.
The increased resistances decrease the power dissipation,
and the Schottky diodes increase the speed.
multiplexer A circuit with many inputs but only one
output. Control signals select which input reaches the output.
noise margin The amount of noise voltage that causes
unreliable operation. With TTL it is 0.4 V. As long as
noise voltages induced on connecting lines are less than
0.4 V, the TTL devices will work reliably.
saturation delay time The time delay encountered when
a transistor tries to come out of the saturation region. When
the base drive switches from high to low, a transistor cannot
instantaneously come out of saturation; extra carriers that
flooded the base region must first flow out of the base.
Schmitt trigger A digital circuit that produces a rectangular
output from any input large enough to drive the Schmitt
trigger. The input waveform may be sinusoidal, triangular,
distorted, and so on. The output is always rectangular.
sink A place where something is absorbed. When satu¬
rated, the lower transistor in a totem-pole output acts like
a current sink because conventional charges flow through
the transistor to ground.
source A place where something originates. The upper
transistor of a totem-pole output acts like a source because
charges flow out of its emitter into the load.
standard TTL The initial TTL design with resistance
values that produce a power dissipation of 10 mW per gate
and a propagation delay time of 10 ns.
SELF-TESTING REVIEW
Read each of the following and provide the missing words.
Answers appear at the beginning of the next question.
1. Small-scale integration, abbreviated_, re¬
fers to fewer than 12 gates on the same chip.
Medium-scale integration (MSI) means 12 to 100
gates per chip. And large-scale integration (LSI)
refers to more than_gates per chip.
2. (SSI, 100) The two basic technologies for digital
ICs are bipolar and MOS. Bipolar technology is
preferred for_and_whereas
MOS technology is better suited to LSI. The reason
MOS dominates the LSI field is that more_
can be fabricated on the same chip area.
3. (SSI, MSI, MOSFETs ) Some of the bipolar families
include DTL, TTL, and ECL_has be¬
come the most widely used bipolar family._
is the fastest logic family; it’s used in high-speed
applications.
4. (TTL, ECL ) Some of the MOS families are PMOS,
NMOS, and CMOS._dominates the LSI
field, and-is used extensively where
lowest power consumption is necessary.
5. (NMOS, CMOS) The 7400 series, also called stan¬
dard TTL, contains a variety of SSI and_
chips that allow us to build all kinds of digital
circuits and systems. Standard TTL has a multiple-
emitter input transistor and a_output.
The totem-pole output produces a low output
impedance in either state.
6. (MSI, totem-pole) Besides standard TTL, there is
high-speed TTL, low-power TTL, Schottky TTL,
and low-power-TTL. Standard TTL and
low-power-TTL have become the favor¬
ites of digital designers, used more than any other
bipolar families.
7. ( Schottky, Schottky) 7400-series devices are guaran¬
teed to work reliably over a_range of 0
to 70°C and over a voltage range of 4.75 to 5.25 V.
A floating TTL input has the same effect as a
_input.
8. (temperature, high) A_TTL device can
sink up to 16 mA and can source up to 400 jiA.
The maximum number of TTL loads a TTL device
can drive is called the_With standard
TTL, the fanout equals_
9. (standard, fanout, 10) A buffer is a device that
isolates other devices. Typically, a buffer has a high
input impedance and a_output imped¬
ance. In terms of digital ICs, this means a_
input current and a high output current capability.
10. (low, low) A Schmitt trigger is a digital circuit that
produces a-output regardless of the in¬
put waveform. It is used to clean up ragged looking
pulses that have been distorted during transmission
from one place to another.
11. (rectangular) A multiplexer is a circuit with many
inputs but only one output. It is also called a data
selector because data can be steered from one of the
inputs to the output. A 74150 is a 16-to-l multi¬
plexer. With this TTL device you can implement
the logic circuit for any four-variable truth table.
Chapter 4 TTL Circuits 61
PROBLEMS
4-1. In Fig. 4-21 a grounded input means that almost
the entire supply voltage appears across the 4-kfl
resistor. Allowing 0.7 V for the emitter-base volt¬
age of Q 1? how much input emitter current is there
with a grounded input? The supply voltage can be
as high as 5.25 V and the 4-kd resistance can be a
low as 3.28 kfl. What is the input emitter current
in this case?
4-2. What is the fanout of a 74S00 device when it
drives low-power TTL loads?
4-3. What is the fanout of a low-power Schottky device
driving standard TTL devices?
4-4. Section 4-4 gave the input and output currents for a
7437 buffer. What is the fanout of a 7437 when it
drives standard TTL loads?
•-Kh*
U
U
d
(a)
Fig. 4-22
4-5. A seven-segment decoder is driving a LED display
like Fig. 4-22 a. Which LEDs are on when digit 8
appears? Which LEDs are on when digit 4 ap¬
pears?
4-6. Section 4-7 described the 74150, a 16-to-l multi¬
plexer. Refer to Fig. 4-23 and indicate the values
the D 0 to D, 5 inputs of a 74150 should have to
reproduce the following truth table: The output is
high when ABCD = 0000, 0100, 0111, 1100,
and 1111; the output is low for all other inputs.
4-7. What is propagation delay?
4-8. Why are 5400 series devices not normally used in
commercial applications?
4-9. What do Schottky devices virtually eliminate
which makes their high switching speeds possi¬
ble?
4-10. What is the noise margin of TTL devices?
62
Digital Computer Electronics
Boolean Algebra and
Karnaugh Maps
This chapter discusses boolean algebra and Karnaugh maps ,
topics needed by the digital designer. Digital design usually
begins by specifying a desired output with a truth table.
The question then is how to come up with a logic circuit
that has the same truth table. Boolean algebra and Karnaugh
maps are the tools used to transform a truth table into a
practical logic circuit.
5-1 BOOLEAN RELATIONS
What follows is a discussion of basic relations in boolean
algebra. Many of these relations are the same as in ordinary
algebra, which makes remembering them easy.
Commutative, Associative, and
Distributive Laws
Given a 2-input or gate, you can transpose the input signals
without changing the output (see Fig. 5-1 a). In boolean
terms
A + B = B + A (5-1)
Similarly, you can transpose the input signals to a 2-input
and gate without affecting the output (Fig. 5-1 b). The
boolean equivalent of this is
AB = BA (5-2)
The foregoing relations are called commutative laws .
The next group of rules are called the associative laws.
The associative law for ORing is
A + (B + C) = (A + B) 4- C (5-3)
(e)
Fig. 5-1 Commutative, associative, and distributive laws.
Figure 5-lc illustrates this rule. The idea is that how you
group variables in an ORing operation has no effect on the
output. For either gate in Fig. 5-lc the output is
Y = A + B + C
64
Similarly, the associative law for ANDing is
Another boolean relation is
A(BC) = (AB)C (5-4)
Figure 5-1 d illustrates this rule. How you group variables
in ANDing operations has no effect on the output. For either
gate of Fig. 5-1 d the output is
Y = ABC
The distributive law states that
A(B + C) = AB + AC (5-5)
This is easy to remember because it’s identical to ordinary
algebra. Figure 5-\e shows the meaning in terms of gates.
or Operations
The next four boolean relations are about or operations.
Here is the first:
A + 0 = A (5-6)
This says that a variable ORed with 0 equals the variable.
For better grasp of this idea, look at Fig. 5-2 a. (The solid
arrow stands for “implies.”) The two cases on the left
imply the case on the right. In other words, if the variable
is 0, the output is 0 (left gate); if the variable is 1, the
output is 1 (middle gate); therefore, a variable ORed with
0 equals the variable (right gate).
A + A = A (5-7)
which is illustrated in Fig. 5-2 b. You can see what happens.
If A is 0, the output is 0; if A is 1, the output is 1; therefore,
a variable ORed with itself equals the variable.
Figure 5-2c shows the next boolean rule:
A + 1 = 1 (5-8)
In a nutshell, if one input to an or gate is 1, the output is
1 regardless of the other input.
Finally, we have
^ + A = 1 (5-9)
shown in Fig. 5-2 d. In this case, a variable ORed with its
complement equals 1.
and Operations
The first and relation to know about is
A • 1 = A (5-10)
illustrated in Fig. 5-3 a. If A is 0, the output is 0; if A is 1,
the output is 1; therefore, a variable ANDed with 1 equals
the variable.
Another relation is
A • A = A (5-11)
o
o
0
0
0
0
1
1
:=D~
Fig. 5-2 or relations.
:=o*
:=£>•
Chapter 5 Boolean Algebra and Karnaugh Maps 6 5
Id)
Fig. 5-3 and relations.
shown in Fig. 5-3 b. In this case, a variable ANDed with
itself equals the variable.
Figure 5-3c illustrates this relation
A • 0=0 (5-12)
The rule is clear. If one input to an and gate is 0, the
output is 0 regardless of the other input.
The last and rule is
A •A = 0 (5-13)
As shown in Fig. 5-3 d, a variable ANDed with its comple¬
ment produces a 0 output.
Double Inversion and De Morgan's Theorems
The double-inversion rule is
A = A (5-14)
which says that the double complement of a variable equals
the variable. Finally, there are the De Morgan theorems
discussed in Chap. 3:
A = AB _ (5-15)
AB=A+B (5-16)
You should memorize Eqs. 5-1 to 5-16 because they are
used frequently in design work.
Duality Theorem
We state the duality theorem without proof. Starting with
a boolean relation, you can derive another boolean relation
by
1. Changing each or sign to an and sign
2. Changing each and sign to an or sign
3. Complementing each 0 and 1
For instance, Eq. 5-6 says that
A + 0 = A
The dual relation is
A • 1 = A
This is obtained by changing the OR sign to an and sign,
and by complementing the 0 to get a 1 .
The duality theorem is useful because it sometimes
produces a new boolean relation. For example, Eq. 5-5
states that
A{B + C) = AB + AC
By changing each or and and operation we get the dual
relation
A + BC = (A + B)(A + C)
This is a new boolean relation, not previously discussed.
(If you want to prove it, construct the truth table for the
66 Digital Computer Electronics
left and right members of the equation. The two truth tables
will be identical.)
Summary
For future reference, here are
their duals:
some boolean relations and
L (' :
A + B = B + A
AB = BA
A + (B + C) = (A + B) +
C A(BC) = (AB)C
A(B + C) =
A + BC =
AB + AC
(A + B)(A + C)
A + 0 = A
A • 1 = A
A + 1 = 1
A • 0 = 0
A + A = A
AA = A
A + A = 1
AA = 0
A = A
A = A
A + B = AB
AB = A + B
A + AB = A
A(A + B) = A
A + AB = A + B
A(A + B) = AB
5-2 SUM-OF-PRODUCTS METHOD
Digital design often starts by constructing a truth table with
a desired output (0 or 1) for each input condition. Once
you have this truth table, you transform it into an equivalent
logic circuit. This section discusses the sum-of-products
method, a way of deriving a logic circuit from a truth table.
(a)
(b)
*=D—
:n>-
(c)
(d)
Fig. 5-4 Fundamental products.
Fundamental Products
Figure 5-4 shows the four possible ways to and two input
signals_and their complements. In Fig. 5-4 a the inputs are
A and B. Therefore, the output is
Y = AB
The output is high only when A = 0 and B - 0.
Figure 5-Ab shows another possibility. Here the inputs
are A and B; so the output is
Y = AB
TABLE 5-1. TWO VARIABLES
A
B
Fundamental product
0
0
AB
0
1
AB
1
0
AB
1
1
AB
In this case, the output is 1 only when A = 0 and B = 1.
In Fig. 5-4c the inputs are A and B. The output
Y = AB
is high only when A = 1 and £ = 0. Finally, in Fig.
5-4 d the inputs are A and B. The output
Y = AB
is 1 only when A = 1 and 5=1.
Table 5-1 summarizes the four possible ways to and two
signals in complemented or uncomplemented form. The
logical products AB,AB, AB, and AB are called fundamental
products because each produces a high output for its
corresponding input. For instance, AB is a 1 when A is 0
and B is 0, AB is a 1 when A is 0 and B is 1, and so forth.
Three Variables
A similar idea applies to three signals in complemented and
uncomplemented form. Given A, 5, C, and their comple¬
ments, Jhere are eight_fundamental products: ABC , ABC ,
ABC , ABC , ABC , ABC , ABC , and ABC . Table 5-2 lists
each input possibility and its fundamental product. Again
notice this property: each fundamental product is high for
the corresponding input. This_means that ABC is a 1 when
A is 0, B is 0, and C is 0; ABC is a 1 when A is 0, B is
0, and C is 1; and so on.
TABLE 5-2. THREE VARIABLES
A
B
c
Fundamental product
0
0
0
ABC
0
0
1
ABC
0
1
0
ABC
0
1
1
ABC
1
0
0
ABC
1
0
1
ABC
1
1
0
ABC
1
1
1
ABC
Chapter 5 Boolean Algebra and Karnaugh Maps 67
Four Variables
TABLE 5-4
When there are 4 input variables, there are 16 possible
input conditions, 0000 to 1111. The corresponding funda¬
mental products are from ABCD through ABCD. Here is
a quick way to find the fundamental product for any input
condition. Whenever the input variable is 0, the same
variable is complemented in the fundamental product. For
instance, if the input condition is 0110, the fundamental
product is ABCD. Similarly, if the input is 0100, the
fundamental product is ABCD.
Deriving a Logic Circuit
To get from a truth table to an equivalent logic circuit OR
the fundamental products for each input condition that
produces a high output. For example, suppose you have a
truth table like Table 5-3. The fundamental products are
listed for each high output. By ORing these products you
get the boolean equation
Y = ABC A ABC 4- ABC A ABC (5-17)
This equation implies four and ga.tes driving an or gate.
The first and gate has inputs of A , B, and C; the second
and gate has inputs of A, B, and C; the third and gate has
inputs of A, B, and C; the fourth and gate has inputs of
A, B, and C. Figure 5-5 shows the corresponding logic
circuit. This and-or circuit has the same truth table as
Table 5-3.
As another example of the sum-of-products method, look
at Table 5-4. Find each output 1 and write its fundamental
product. The resulting products are ABCD , ABCD , and
ABCD. This means that the boolean eq uation is
Y = ABCD A ABCD + ABCD (5-18)
This ^equation implies that three and gates_ are driving an
or gate. The first and gate has inputs of A, B, C, and D\
the second has inputs of A, B, C , and D\ the third has
A a b b c c
TABLE 5-3
A
B
c
Y
A
B
c
D
Y
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
1 ^ ABC
0
0
1
0
0
0
1
1
0
0
0
1
1
1
1
0
0
0
0
1
0
0
0
1
0
1
1 ABC
0
1
0
1
0
1
1
0
1 ABC
0
1
1
0
0
1
1
1
1 —* ABC
0
1
1
1
1
1
0
0
0
0
1
0
0
1
1
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
0
A A B B C C D D
inputs of A, B, C, and D. Figure 5-6 is the equivalent logic
circuit.
The sum-of-products method always works. You or the
fundamental products of each high output in the truth table.
This gives an equation which you can transform into an
and-or network that is the circuit equivalent of the truth
table.
5-3 ALGEBRAIC SIMPLIFICATION
After obtaining a sum-of-products equation as described in
the preceding section, the thing to do is to simplify the
circuit if possible. One way to do this is with boolean
algebra. Here is the approach. Starting with the boolean
equation for the sum-of-products circuit, you try to rearrange
and simplify the equation as much as possible using the
boolean rules of Sec. 5-1. The simplified boolean equation
means a simpler logic circuit. This section will give you
examples.
68 Digital Computer Electronics
AABBCCDD
(a)
A A B B C C D D
Gate Leads
A preliminary guide for comparing the simplicity of one
logic circuit with another is to count the number of input
gate leads; the circuit with fewer input gate leads is usually
easier to build. For instance, the and-or circuit of Fig.
5-la has a total of 15 input gate leads (4 on each and gate
and 3 on the or gate). The and-or circuit of Fig. 5-lb ,
on the other hand, has a total of 9 input gate leads. The
and-or circuit of Fig. 5-lb is simpler than the and-or
circuit of Fig. 5-la because it has fewer input gate leads.
A bus is a group of wires carrying digital signals. The
8-bit bus of Fig. 5-la transmits variables A, B, C, D and
their complements A, B, C, and D. In the typical micro¬
computer, the microprocessor, memory, and I/O units
exchange data by means of buses.
Factoring to Simplify
One way to reduce the number of input gate leads is to
factor the boolean equation if possible. For instance, the
boolean equation
Y = AB + AB (5-19)
has the equivalent logic circuit shown in Fig. 5-8 a. This
circuit has six input gate leads. By factoring Eq. 5-19 we
get
Y = A(B + B )
A A B B
(c)
Fig. 5-8
The equivalent logic circuit for this is shown in Fig. 5-8 b;
it has only four input gate leads.
Recall that a variable ORed with its complement always
equals 1; therefore,
Y = A(B + B) = A • 1 = A
To get this output, all we need is a connecting wire from
the input to the output, as shown in Fig. 5-8c. In other
words, we don’t need any gates at all.
Another Example
Here is another example of how factoring can simplify a
boolean equation and its corresponding logic circuit. Sup¬
pose we are given
Y = AB + AC 4- BD + CD (5-20)
In this equation, two variables at a time are being ANDed.
The logical products are then ORed to get the final output.
Figure 5-9 a shows the corresponding logic circuit. It has
12 input gate leads.
We can factor and rearrange Eq. 5-20 as
Y = A(B + C) + D(B + C)
Chapter 5 Boolean Algebra and Karnaugh Maps 69
ABCD
In general, one approach in digital design is to transform
a truth table into a sum-of-products equation, which you
then simplify as much as possible to get a practical logic
circuit.
5-4 KARNAUGH MAPS
Many engineers and technicians don’t simplify equations
with boolean algebra. Instead, they use a method based on
Karnaugh maps. This section tells you how to construct a
Karnaugh map.
(a) (b) (c)
B B B B
(d) (e)
Fig. 5-10 Two-variable Karnaugh map.
Y = (A + D)(B + C) (5-21)
In this case, the variables are first ORed, then the logical
sums are ANDed. Figure 5-9 b illustrates the logic circuit.
Notice it has only six input gate leads and is simpler than
the circuit of Fig. 5-9a.
Pinal Example
In Sec. 5-2 we derived this sum-of-products equation from
a truth table:
Y = ABCD + ABCD + A BCD (5-22)
Figure 5-la shows the sum-of-products circuit. It has 15
input gate leads. We can factor the equation as
Y = ACD(B > 5) + ABCD
or as
Y = ACD + ABCD (5-23)
Figure 5-lb shows the equivalent logic circuit; it has only
nine input gate leads.
Two-Variable Map
Suppose you have a truth table like Table 5-5. Here’s how
to construct the Karnaugh map. Begin by drawing Fig.
5-10a. Note the order of the variables and their complements;
the vertical column has A followed by A, and the horizontal
row has B followed by B.
Next, look for output Is in Table 5-5. The first 1 output
to appear is for the input of A_= 1 and 5 = 0. The
fundamental product for this is AB. Now, enter a 1 on the
Karnaugh map as shown in Fig. 5-10b. This 1 represents
the product AB because the 1 is in the A row and the B
column.
Similarly, Table 5-5 has an output 1 appearing for an
input of A = 1 and 5 = 1. The fundamental product for
this is AB. When you enter a 1 on the Karnaugh map to
represent A5, you get the map of Fig. 5-10c.
The final step in the construction of the Karnaugh map
is to enter 0s in the remaining spaces. Figure 5-10 d shows
how the Karnaugh map looks in its final form.
Here’s another example of a two-variable map. In the
truth table of Table 5-6, the fundamental products are AB
and AB. When Is are entered on the Karnaugh map for
these products and 0s for the remaining spaces, the com¬
pleted map looks like Fig. 5-10c.
70 Digital Computer Electronics
TABLE 5-5
TABLE 5-6
c c
C C
C
C
AB
AB
AB
0
0
AB j
AB
1
AB
1
0
AB S
AB
1 1
AB
1
1
AB
AB
AB
0
0
(a)
(b)
(c)
Fig. 5-11 Three-variable Karnaugh map.
Three-Variable Map
Suppose you have a truth table like Table 5-7. Begin by
drawing Fig. 5-1 la. It is especially important to notice the
order of the variable^and their complements. The vertical
column is labeled AB,AB, AB, and AB. This order is not
a binary progression; instead it follows the order of 00, 01,
11, and 10. The reason for this is explained in the derivation
of the Karnaugh method; briefly, it’s done so that only one
variable changes from complemented to uncomplemented
form (or vice versa).
Next, look for output Is in Table 5-7. The fundamental
products for these 1 outputs are ABC, ABC , and ABC.
Enter these Is on the Karnaugh map (Fig. 5-1 lb). The final
step is to enter Os in the remaining spaces (Fig. 5-1 lc).
This Karnaugh map is useful because it shows the funda¬
mental products needed for the sum-of-products circuit.
TABLE 5-7
A
B
c
Y
0
0
0
0
0
0
1
0
0
1
0
1
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
1
1
1
1
1
CD CD CD CD
CD CD CD CD
AB
AB
1
AB
!
AB
1 1
AB
AB
1
AB
AB
(a) (b)
CD
CD
CD
CD
AB
0
1
0
0
AB
0
0
1
1
AB
0
0
0
1
AB
0
0
0
0
(c)
Fig. 5-12 Four-variable Karnaugh map.
Four-Variable Map
Many MSI circuits process binary words of 4 bits each
(nibbles). For this reason, logic circuits are often designed
to handle four variables (or their complements). This is
why the four-variable map is the most important.
Here’s an example of constructing a four-variable map.
Suppose you have the truth table of Table 5-8. The first
step is to draw the blank map of Fig. 5-12a. Again, notice
the progression. The vertical column is labeled AB, AB,
TABLE 5-8
A
B
c
D
Y
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
1
1
1
1
1
0
Chapter 5 Boolean Algebra and Karnaugh Maps 71
AB , and AB. The horizontal row is labeled CD, CD, CD,
and CD.
In Table 5-8 the output Is have these fundamental
products: AB CD, ABCD, ABCD, andASCD. After entering
Is on the Karnaugh map, you will have Fig. 5-12 b. The
final step of filling in Os results in the completed map of
Fig. 5-12c.
5-5 PAIRS, QUADS, AND OCTETS
There is a way of using the Karnaugh map to get simplified
logic circuits. But before you can understand how this is
done, you will have to learn the meaning of pairs , quads ,
and octets.
CD CD CD CD CD CD CD CD
(e) (f)
Fig. 5-13 Pairs on a Karnaugh map.
Pairs
The map of Fig. 5-13 a contains a pair of Is that are
horizontally adjacent. The first 1 represents the_ product
ABCD ; the second 1 stands for the product ABCD. As we
move from the first 1 to the second 1, only one variable
goes from uncomplemented to complemented form (D to
D). The other variables don’t change form (A, S, and C
remain uncomplemented). Whenever this happens, you can
eliminate the variable that changes form.
Algebraic Proof
The sum-of-products equation corresponding to Fig. 5-13a
is
Y = ABCD + ABCD
which factors into
Y = ABC(D F D)
Since D is ORed with D, the equation reduces to
Y = ABC
A pair of adjacent Is is like those of Fig 5-13a always
means that the sum-of-products equation will have a variable
and a complement that drop out.
For easy identification, it is customary to encircle a pair
of adjacent Is, as shown in Fig. 5-13/?. Then when you
look at the map, you can tell at a glance that one variable
and its complement will drop out of the boolean equation.
In other words, an encircled pair of Is like those of Fig.
5-13 b no longer stands for the ORing of two separate
products, ABCD and ABCD. The encircled pair should be
visualized instead as representing a single reduced product
ABC.
Here’s another example. Figure 5-13c shows a pair of
Is that are vertically adjacent. These Is correspond to the
product ABCD and ABCD. Notice that only one variable
changes from uncomplemented to complemented form (B
to B)\ all other variables retain their original form. Therefore,
B and B drop out. This means that the encircled pair of
Fig. 5-13c represents ACD.
From now on, whenever you see a pair of adjacent Is,
eliminate the variable that goes from complemented to
uncomplemented form. A glance at Fig. 5-13 d indicates
that B changes form; therefore, the pair of Is represents
ACD. Likewise, D changes form in Fig. 5-13c; so the pair
of Is stands for A SC.
If more than one pair exists on a Karnaugh map, you
can or the simplified products to get the boolean equation.
For instance, the lower pair of Fig. 5-13/represents ACD.
The upper pair stands for ABD. The corresponding boolean
equation for this map is
Y = ACD + ABD
The Quad
A quad is a group of four Is that are end tc end, as shown
in Fig. 5-14a, or in the form of a square, as shown in Fig.
72 Digital Computer Electronics
5-14 b. When you see a quad, always encircle it because it
leads to a simpler product. In fact, a quad means that two
variables and their complements drop out of the boolean
equation.
Here’s why a quad eliminates two variables. Visualize
the four Is of Fig. 5-14a as two pairs (Fig. 5-14c). The
first pair represents ABC ; the second pair stands for ABC.
The boolean equation for these two pairs is
Y = ABC + ABC
This factors into
CD CD CD CD CD CD CD CD
(a) (b)
Fig. 5-15 Octets on a Karnaugh map.
Y = AB(C + C)
which reduces to
Y = AB
So the quad of Fig. 5-14a represents a product where two
variables and their complements drop out.
A similar proof applies to all quads. There’s no need to
go through the algebra again. Merely determine which
variables go from complemented to uncomplemented form;
these are the variables that drop out.
For instance, look at the quad of Fig. 5-14 b. Pick any 1
as a starting point. When you move horizontally, D is the
variable that changes form. When you move vertically, B
changes form. Therefore, the simplified equation is
The Octet
An octet is a group of eight adjacent Is like those of Fig.
5-15a. An octet always eliminates three variables and their
complements. Here’s why. Visualize the octet as two quads
(Fig. 5-15 b). The equation for these two quads is
Y = AC + AC
Factoring gives
Y = A(C 4- C)
But this reduces to
Y = A
Y = AC
CD
CD
CD
CD
AB
0
0
0
0
AB
0
0
0
0
AB
c
1
1
>
AB
0
0
0
0
(a)
CD CD CD CD
(b)
CD CD CD CD
(c)
Fig. 5-14 Quads on a Karnaugh map.
So the octet of Fig. 5-15a means that three variables and
their complements drop out of the corresponding product.
A similar proof applies to any octet. From now on, don’t
bother with the algebra. Just step through the Is of the
octet and determine which three variables change form.
These are the variables that drop out.
5-6 KARNAUGH SIMPLIFICATIONS
You have seen how a pair eliminates one variable, a quad
eliminates two variables, and an octet eliminates three
variables. Because of this, you should encircle the octets
first, the quads second, and the pairs last. In this way, the
greatest simplification takes place.
An Example
Suppose you’ve translated a truth table into the Karnaugh
map shown in Fig. 5-16a. Look for octets first. There are
none. Next, look for quads. There are two. Finally, look
for pairs. There is one. If you do it correctly, you arrive
at Fig. 5-166.
The pair represents the_simplified product ABD, the
lower quad stands for AC, and the quad on the right
Chapter 5 Boolean Algebra and Karnaugh Maps 73
CD CD CD CD CD CD CD CD
AB 0 111
AB 0 0 0 1
AB 1 10 1
AB 1 10 1
Fig. 5-16
represents CD. By ORing these simplified products, you get
the boolean equation for the map
Y = ABD A AC A CD (5-24)
Overlapping Groups
When you encircle groups, you are allowed to use the same
1 more than once. Figure 5-17a illustrates the idea. The
simplified equation for the overlapping groups is
Y = A A BCD (5-25)
It is valid to encircle the Is as shown in Fig. 5-17 b, but
then the isolated 1 results in a more complicated equation:
Y = A A ABCD
This requires a more complicated logic circuit than Eq.
5-25. So always overlap groups if possible; that is, use the
Is more than once to get the largest groups you can.
CD CD CD CD CD CD CD CD
(c) (d)
Fig. 5-17 Overlapping and rolling.
Rolling the Map
Another thing to know about is rolling. In Fig. 5-17c, the
pairs result in the equation
Y = BCD A BCD (5-26)
Visualize picking up the Karnaugh map and rolling it so
that the left side touches the right side. If you’re visualizing
correctly, you will realize the two pairs actually form a
quad. To indicate this, draw half circles around each pair,
as shown in Fig. 5-11 d. From this viewpoint, the quad of
Fig. 5-11 d has the equation
Y = BD (5-27)
Why is rolling valid? Because Eq. 5-26 can be simplified
to Eq. 5-27. Here’s the proof. Start with Eq. 5-26:
Y = BCD A BCD
This factors into
Y = BD(C A C)
which reduces to
Y = BD
This final equation represents a rolled quad like Fig. 5-lld.
Therefore, Is on the edges of a Karnaugh map can be
grouped with Is on opposite edges.
CD
CD CD
CD
CD
CD
CD
CD
AB
0
0 0
0
AB
0
0
0
0
AB
0
0
0
AB
0
A
0
0
AB
0
4q£f
0
AB
0
u
A
0
AB
0
° u
0
AB
0
0
u
0
(a) (b)
Fig. 5-18 Redundant group.
Redundant Groups
After you finish encircling groups, there is one more thing
to do before writing the simplified boolean equation:
eliminate any group whose Is are completely overlapped
by other groups. (A group whose Is are all overlapped by
other groups is called a redundant group.)
Here is an example. Suppose you have encircled the
three pairs shown in Fig. 5-18a. The boolean equation then
is
Y = BCD A ABD A ACD
74 Digital Computer Electronics
At this point, you should check to see if there are any
redundant groups. Notice that the Is in the inner pair are
completely overlapped by the outside pairs. Because of
this, the inner pair is a redundant pair and can be eliminated
to get the simpler map of Fig. 5-18 b. The equation for this
map is
Y = BCD + ACD
Since this is a simpler equation, it means a simpler logic
circuit. This is why you should eliminate redundant groups
if they exist.
Summary
Here’s a summary of how to use the Karnaugh map to
simplify logic circuits:
1. Enter a 1 on the Karnaugh map for each fundamental
product that corresponds to 1 output in the truth table.
Enter Os elsewhere.
2. Encircle the octets, quads, and pairs. Remember to roll
and overlap to get the largest groups possible.
3. If any isolated Is remain, encircle them.
4. Eliminate redundant groups if they exist.
5. Write the boolean equation by ORing the products
corresponding to the encircled groups.
6. Draw the equivalent logic circuit.
EXAMPLE 5-1
What is the simplified boolean equation for the Karnaugh
map of Fig. 5-19a?
CD
CD
CD
CD
CD
CD
CD
CD
AB
0
0
0
0
AB
0
0
0
0
AB
0
0
1
0
AB
0
0
1
0
AB
1
1
1
1
AB
<C
1
1
AB
0
1
1
1
AB
0
1
1
1
(a)
(b)
CD
CD
CD
CD
CD
CD
CD
CD
(c) (d)
Fig. 5-19
SOLUTION
There are no octets, but there is a quad, as shown in Fig.
5-19 b. By overlapping we can find two more quads (Fig.
5-19c). Finally, overlapping gives us the pair of Fig.
5-19 d.
The horizontal quad of Fig. 5-19 d corresponds to a
simplified product of AB. The square quad on the right
corresponds to AC, while the one on the left stands for AD.
The pair represents BCD. By ORing these products we get
the simplified equation
Y = AB + AC + AD + BCD (5-28)
Figure 5-20 shows the equivalent logic circuit.
A B C D
EXAMPLE 5-2
As you know from Chap. 4, the nand gate is the least
expensive gate in the 7400 series. Because of this, and-
or circuits are usually built as equivalent nand-nand
circuits.
Convert the and-or circuit of Fig. 5-20 to a nand-nand
circuit using 7400-series devices.
SOLUTION
Replace each and gate of Fig. 5-20 by a nand gate and
replace the final or gate by a nand gate. Figure 5-21 is
the De Morgan equivalent of Fig. 5-20. As shown, we can
build the circuit with a 7400, a 7410, and a 7420.
5-7 DON’T-CARE CONDITIONS
Sometimes, it doesn’t matter what the output is for a given
input word. To indicate this, we use an X in the truth table
instead of a 0 or a 1. For instance, look at Table 5-9. The
Chapter 5 Boolean Algebra and Karnaugh Maps 7 5
CD
CD
CD
CD
CD
CD
CD
CD
AB
1
0
1
0
AB
A
0
A
0
AB
1
1
1
0
AB
i '
r
rv
0
AB
X
X
X
X
AB
i x J
xj
X
AB
X
X
X
X
AB
V
X
\xj
X
(a) (b)
AABBCCDL
I I I I 7410
Fig. 5-21 nand-nand circuit using TTL gates.
output is an X for any input word from 1000 through 1111.
The X’s are called don't cares because they can be treated
either as Os or Is, whichever leads to a simpler circuit.
Figure 5-22a shows_the Karnaugh map for Table 5-9.
X’s_are used_for ABCD, ABCD y A BCD, ABCD, ABCD ,
ABCD , ABCD , and ABCD because these are don’t cares
in the truth table. Figure 5-22 b shows the most efficient
way to encircle the groups. Notice two crucial ideas. First,
we visualize all X’s as Is and try to form the largest groups
that include the real Is. This gives us three quads. Second,
we visualize all remaining X’s as Os. In this way, the X’s
are used to the best advantage. We are free to do this
because the don’t cares can be either Os or Is, whichever
we prefer.
TABLE 5-9
A
B
c
D
Y
0
0
0
0
1
0
0
0
1 1
0
0
0
1
0 !
0
0
0
1
1 |
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
0
0
1
1
1
1
1
0
0
0
X
1
0
0
1
X
1
0
1
0
X
1
0
I
1
X
1
1
0
0 ;
X
1
1
0
1
X
1
1
1
0
X
1
1
1
1
X
(c)
Fig. 5-22 Don’t cares.
Figure 5-22 b implies the simplified boolean equation
Y = BD + CD + CD
Figure 5-22c is the simplified logic circuit. This and-or
network has nine input gate leads.
EXAMPLE 5-3
Recall that BCD numbers express each decimal digit as a
nibble: 0 to 9 are encoded as 0000 to 1001. Especially
important, nibbles 1010 to 1111 are never used in a BCD
system.
Table 5-10 shows a truth table for use in a BCD system.
As you see, don’t cares appear for 1010 through 1111.
Construct the Karnaugh map and show the simplified logic
circuit.
SOLUTION
Figure 5-23 a illustrates the Karnaugh map. The largest
group we can form is the pair shown in Fig. 5-23 b. The
boolean equation is
Y = BCD
Figure 5-23c is the simplified logic circuit.
76 Digital Computer Electronics
TABLE 5-10
A
B
c
D
Y
0
0
0
0
0
0
0
0
1
0
0
0
I
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
1
1
0
0
0
0
1
0
0
1
0
- 1
0
1
0
X
1
0
l
1
X
1
1
0
0
X
1
1
0
r
X
1
1
1
0
X
1
1
1
1
X
v :>
CD CD CD CD
AB 0 0 0 0
AB 0 0 10
AB X X X X
45 0 0 X X
CD CD CD CD
AABBCCDD
Fig. 5-23 Don’t cares in a BCD system.
GLOSSARY
bus A group of wires carrying digital signals.
don’t care An output that may be either low or high
without affecting the operation of the system.
fundamental product The logical product of variables and
complements that produces a high output for a given input
condition.
Karnaugh map A graphical display of the fundamental
products in a truth table.
octet A group of eight adjacent Is on a Karnaugh map.
pair A group of two adjacent Is on a Karnaugh map.
These Is may be horizontally or vertically aligned.
quad A group of four adjacent Is on a Karnaugh map.
redundant group A group of Is on a Karnaugh map all
of which are overlapped by other groups.
sum-of-products circuit An and-or circuit obtained by
ORing the fundamental products that produce output Is in
a truth table.
SELF-TESTING REVIEW
Read each of the following and provide the missing words.
Answers appear at the beginning of the next question.
1. Digital design often starts by constructing a_
table. By ORing the_products, you get a
sum-of-products equation.
2. (truth, fundamental) A preliminary guide for compar¬
ing the simplicity of logic circuits is to count the
number of input_leads.
3. (gate) A bus is a group of_carrying
digital signals. In the typical microcomputer, the mi¬
croprocessor, memory, and I/O units communicate
via buses.
4. (wires) One way to simplify the sum-of-products
equation is to use boolean algebra. Another way is
the_map.
5. (Karnaugh) A pair eliminates one variable, a
_eliminates two variables, and an octet
eliminates_variables. Because of this,
you should encircle the_first, the quads
next, and the pairs last.
6. (quad, three, octets) nand-nand circuits are equiva¬
lent to and-or circuits. This is important because
_gates are the least expensive gates in the
7400 series.
7. (nand) When a truth table has don’t cares, we enter
X’s on the Karnaugh map. These can be treated as 0s
or Is, whichever leads to a simpler logic circuit.
Chapter 5 Boolean Algebra and Karnaugh Maps 77
PROBLEMS
5-1. What are the fundamental products for each of the
inputs words ABCD = 0010, ABCD = 1101,
ABCD = 1110?
5-2. A truth table has output Is for each of these
inputs:
a. ABCD = 0011
b. ABCD = 0101
c. ABCD = 1000
d. ABCD = 1101
What are the fundamental products?
5-3. Draw the logic circuit for this boolean equation:
Y = ABCD + ABCD + ABCD + ABCD
5-4. Output Is appear in the truth table for these input
conditions: ABCD = 0001, ABCD = 0110, and
ABCD = 1110. What is the sum-of-products
equation?
5-5. Draw the and-or circuit for
Y = ABCD + ABCD + ABCD
How many input gate leads does this circuit have?
5-6. A truth table has output Is for these inputs:
ABCD = 0011, ABCD = 0110, ABCD =
1001, and ABCD = 1110. Draw the Karnaugh
map showing the fundamental products.
5-7. A truth table has four input variables. The first
eight outputs are 0s, and the last eight outputs are
Is. Draw the Karnaugh map.
5-8. Draw the Karnaugh map for the Y 3 output of
Table 5-11. Simplify as much as possible; then
draw the logic circuit.
5-9. Use the Karnaugh map to work out the simplified
logic circuit for the Y 2 output of Table 5-11.
5-10. Repeat Prob. 5-9 for the Y } output.
5-11. Repeat Prob. 5-9 for the Y 0 output.
5-12. Use the Karnaugh map to work out the simplified
logic circuit for the Y 3 output of Table 5-12.
5-13. Repeat Prob. 5-12 for the Y 2 output.
5-14. Repeat Prob. 5-12 for the Y x output.
5-15. Repeat Prob. 5-12 for Y 0 output.
5-16. A + 0 = ?
5_17. A • 1 = ?
5-18. A + 1 = ?
5-19. A • 0 = ?
5-20. Use the duality theorem to derive another boolean
relation from:
A + AB = A + B
5.21. Use the commutative law to complete the follow¬
ing equations.
a. A + B =
b. AB =
5.22 Use the associative law to complete the following
equations.
a. A + (B + C) =
b. A(BC) =
5.23 Use the distributive law to complete the equation
A(B + C) =
TABLE 5-11
A
B
c
D
y 3
Y 2
Y x
n
0
0
0
0
1
0
1
0
0
0
0
1
0
1
0
1
0
0
1
0
0
1
1
1
0
0
1
1
1
0
0
1
0
1
0
0
0
0
1
1
0
1
0
1
1
0
0
0
0
1
1
0
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
1
0
1
1
1
0
1
1
0
1
0
0
1
1
0
0
0
1
1
0
1
1
0
1
1
0
1
0
1
1
1
0
1
1
0
0
1
1
1
1
1
1
0
1
TABLE 5-12
A
B
c
D
Y 3
Y2
Yo
0
0
0
0
1
0
1
0
0
0
0
1
0
1
0
1
0
0
1
0
0
1
1
1
0
0
1
1
1
0
0
1
0
1
0
0
0
0
1
1
0
1
0
1
1
0
0
0
u
1
1
0
1
1
1
0
0
1
1
1 1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
X
X
X
X
1
0
1
1
X
X
X
X
1
1
0
0
X
X
X
X
1
1
0
1
X
X
X
X
1
1
1
0
X
X
X
X
1
1
1
1
X
X
X
X
78
Digital Computer Electronics
Arithmetic-Logic Units
The arithmetic-logic unit (ALU) is the number-crunching
part of a computer. This means not only arithmetic opera¬
tions but logic as well (or, and, not, and so forth). In
this chapter you will learn how the ALU adds and subtracts
binary numbers. Later chapters will discuss the logic
operations.
6-1 BINARY ADDITION
ALUs don’t process decimal numbers; they process binary
numbers. Before you can understand the circuits inside an
ALU, you must learn how to add binary numbers. There
are five basic cases that must be understood before going
on.
Case 1
When no pebbles are added to no pebbles, the total is no
pebbles. As a word equation,
None + none = none
With binary numbers, this equation is written as
0 + 0 = 0
&
Case 2
If no pebbles are added to one pebble, the total is one
pebble:
None + • = 0
In terms of binary numbers,
0+1 = 1
Case 3
Addition is commutative. This means you can transpose
the numbers of the preceding case to get
9 + none = 9
or
1 + 0=1
Case 4
Next, one pebble added to one pebble gives two pebbles:
9 + 9 = 99
As a binary equation,
1 + 1 = 10
To avoid confusion with decimal numbers, read this as
“one plus one equals one-zero.” An alternative way of
reading the equation is “one plus one equals zero, carry
one.”
Case 5
One pebble plus one pebble plus one pebble gives a total
of three pebbles:
9 + 9 + 9 = 999
The binary equation is
1 + 1 + 1 = 11
Read this as “one plus one plus one equals one-one.”
Alternatively, “one plus one plus one equals one, carry
one.”
79
Rules to Remember
EXAMPLE 6-1
The foregoing cases are all you need for more complicated
binary addition. Therefore, memorize these five rules: binary num bers 01010111 and 00110101.
0
+
0 =
0
(6-1)
0
+
1 =
1
(6-2)
1
+
0 =
1
(6-3)
1
+
1 =
10
(6-4)
1 + 1
+
1 =
11
(6-5)
Larger Binary Numbers
Column-by-column addition applies to binary numbers as
well as decimal. For example, suppose you have this
problem in binary addition:
11100
+ 11010
7
Start with the least significant column to get
11100
+ 11010
0
Here, 0 + 0 gives 0.
Next, add the bits of the second column as follows:
11100
+ 11010
10
This time, 0 + 1 results in 1.
The third column gives
11100
+ 11010
110
In this case, 1 + 0 produces 1.
The fourth column results in
11100
+ 11010
0110 (carry 1)
As you see, 1 + 1 equals 0 with a carry of 1.
Finally, the last column gives
11100
+ 11010
110110
Here, 1 + 1 + 1 (carry) produces 11, recorded as 1 with
a carry to the next higher column.
SOLUTION
This is the problem:
01010111
+ 00110101
7
If you add the bits column by column as previously
demonstrated, you will get
01010111
+ 00110101
10001100
Expressed in hexadecimal numbers, the foregoing addi¬
tion is
57
+ 35
8C
For clarity, we can use subscripts:
+ 35 t6
8C 16
In microprocessor work, it is more convenient to use the
letter H to signify hexadecimal numbers. In other words,
the usual way to express the foregoing addition is
57H
+ 35H
8CH
6-2 BINARY SUBTRACTION
To subtract binary numbers, we need to discuss four cases.
Case 1: 0-0 = 0
Case 2: 1-0=1
Case 3: 1-1=0
Case 4: 10-1 = 1
The last result represents
••• = •
which makes sense.
80 Digital Computer Electronics
To subtract larger binary numbers, subtract column by
column, borrowing from the next higher column when
necessary. For instance, in subtracting 101 from 111,
proceed like this:
7 111
- 5 - 101
2 010
TABLE 6-1. HALF-ADDER
A
B
CARRY
SUM
0
0
0
0
0
1
0
1
1
0
0
1
1
1
1
0
Starting on the right, 1 - 1 gives 0; then, 1 - 0 is 1;
finally, 1 — 1 is 0.
Here is another example: subtract 1010 from 1101.
13 1101
- 10 - 1010
3 0011
In the least significant column, 1 — 0 is 1. In the second
column, we have to borrow from the next higher column;
then, 10 — 1 is 1. In the third column, 0 (after borrow)
— 0 is 0. In the fourth column, 1 — 1=0.
Direct subtraction like the foregoing has been used in
computers; however, it is possible to subtract in a different
way. Later sections of this chapter will show you how.
6-3 HALF-ADDERS
Figure 6-1 is a half-adder, a logic circuit that adds 2 bits.
Notice the outputs: SUM and CARRY. The boolean equations
for these outputs are
SUM = A © B (6-6)
CARRY = AB (6-7)
The SUM output is A xor B\ the CARRY output is A and
B. Therefore, SUM is a 1 when A and B are different;
CARRY is a 1 when A and B are Is.
Table 6-1 summarizes the operation. When A and B are
0s, the SUM is 0 with a CARRY of 0. When A is 0 and B
is 1, the SUM is 1 with a CARRY of 0. When A is 1 and
B is 0, the SUM equals 1 with a CARRY of 0. Finally,
when A is 1 and B is 1, the SUM is 0 with a CARRY of L
The logic circuit of Fig. 6-1 does electronically what we
do mentally when we add 2 bits. Applications for the half¬
adder are limited. What we need is a circuit that can add
3 bits at a time.
A B
Fig. 6-1 Half-adder.
6-4 FULL ADDERS
Figure 6-2 shows di full adder, a logic circuit that can add
3 bits. Again there are two outputs, SUM and CARRY. The
boolean equations are
SUM = A © B 0 C (6-8)
CARRY = AB + AC 4- BC (6-9)
ABC
Fig. 6-2 Full adder.
In this case, SUM equals A xor B xor C; CARRY equals
AB or AC or BC . Therefore, SUM is 1 when the number
of input Is is odd; CARRY is a 1 when two or more inputs
are Is.
Table 6-2 summarizes the circuit action. A, B, and C
are the bits being added. If you check each entry, you will
see that the circuit adds 3 bits at a time and comes up with
the correct answer.
TABLE 6-2. FULL ADDER
A
B
c
CARRY
SUM
0
0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
1
0
1
0
0
0
1
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
Chapter 6 Arithmetic-Logic Units
81
Here’s the point. The circuit of Fig. 6-2 does electronically
what we do mentally when we add 3 bits. The full adder
can be cascaded to add large binary numbers. The next
section tells you how.
6-5 BINARY ADDERS
Figure 6-3 shows a binary adder, a logic circuit that can
add two binary numbers. The block on the right (labeled
HA) represents a half-adder. The inputs are A 0 and B 0 \ the
outputs are S 0 (SUM) and C x (CARRY). All other blocks
are full adders (abbreviated FA). Each of these full adders
has three inputs (A„, B n , and C„) and two outputs.
The circuit adds two binary numbers. In other words, it
carries out the following addition:
A3A2A1A0
T B 3 B 2 B 1 B 0
C4S3 S 2 S 1 So
Here’s an example. Suppose A = 1100 and B = 1001.
Then the problem is
1100
+ 1001
?
Figure 6-4 shows the binary adder with the same inputs,
1100 and 1001. The half-adder produces a sum of 1 and
carry of 0, the first full adder produces a sum of 0 and a
carry of 0, the second full adder produces a sum of 1 and
a carry of 0, and the third full adder produces a sum of 0
and a carry of 1. The overall output is 10101, the same
answer we would get with pencil and paper.
By using more full adders, we can build binary adders
of any length. For example, to add 16-bit numbers, we
need 1 half-adder and 15 full adders. From now on, we
will use the abbreviated symbol of Fig. 6-5 to represent a
binary adder of any length. Notice the solid arrows, the
standard way to indicate words in motion. In Fig. 6-5,
words A and B are added to get a sum of S plus a final
CARRY.
A B
S
Fig. 6-5 Symbol for binary adder.
EXAMPLE 6-2
Find the output in Fig. 6-5 if the two input words are
A = 0000 0001 0000 1100
B = 0000 0000 0100 1001
Fig. 6-4 Adding 12 and 9 to get 21.
82 Digital Computer Electronics
SOLUTION
The binary adder adds the two inputs to get
0000 0001 0000 1100
+ 0000 0000 0100 1001
0000 0001 0101 0101
In hexadecimal form, the foregoing addition is
010CH
+ 0049H
0155H
6-6 SIGNED BINARY NUMBERS
The negative decimal numbers are —1, — 2, —3, and so
on. One way to code these as binary numbers is to convert
the magnitude (1, 2, 3, . . .) to its binary equivalent and
prefix the sign. With this approach, —1, —2, and —3
becomes —001, —010, and —Oil. It’s customary to use
0 for the + sign and 1 for the — sign. Therefore, —001,
-010, and -Oil are coded as 1001, 1010, and 1011.
The foregoing numbers have the sign bit followed by the
magnitude bits. Numbers in this form are called signed
binary numbers or sign-magnitude numbers. For larger
decimal numbers you need more than 4 bits. But the idea
is still the same: the leading bit represents the sign and the
remaining bits stand for the magnitude.
EXAMPLE 6-3
Express each of the following as 16-bit signed binary
numbers.
a. + 7
b. -7
c. +25
d. -25
SOLUTION
a. +7 = 0000 0000 0000 0111
b. -7 = 1000 0000 0000 0111
c. +25 = 0000 0000 0001 1001
d. -25 = 1000 0000 0001 1001
No subscripts are used in these equations because it’s clear
from the context that decimal numbers are being expressed
in binary form. Nevertheless, you can use subscripts if you
prefer. The first equation can be written as
+ 7 10 = 0000 0000 0000 0111 2
the next equation as
-7 10 = 1000 0000 0000 0111 2
and so forth.
EXAMPLE 6-4
Convert the following signed binary numbers to decimal
numbers:
a. 0000 0000 0000 1001
b. 1000 0000 0000 1111
c. 1000 0000 0011 0000
d. 0000 0000 1010 0101
SOLUTION
As usual, the leading bit gives the sign and the remaining
bits give the magnitude.
a. 0000 0000 0000 1001 = +9
b. 1000 0000 0000 1111 = -15
c. 1000 0000 0011 0000 = -48
d. 0000 0000 1010 0101 = +165
6-7 2’s COMPLEMENT
Sign-magnitude numbers are easy to understand, but they
require too much hardware for addition and subtraction.
This has led to the widespread use of complements for
binary arithmetic.
Definition
Recall that a high invert signal to a controlled inverter
produces the l’s complement. For instance, if
A = 0111 (6-10a)
the l’s complement is
A = 1000 (6-10/7)
The 2’s complement is defined as the new word obtained
by adding 1 to l’s complement. As an equation,
A' = A + 1 (6-11)
where A' = 2’s complement
A = l’s complement
Here are some examples. If
A = 0111
Chapter 6 Arithmetic-Logic Units S3
the l’s complement is
Back to the Odometer
A = 1000
and the 2’s complement is
A' = 1001
In terms of a binary odometer, the 2’s complement is the
next reading after the l’s complement.
Another example. If
then
A = 0000 1000
and
A = 1111 0111
A' = mi iooo
Double Complement
If you take the 2’s complement twice, you get the original
word back. For instance, if
A = 0111
the 2’s complement is
A' = 1001
If you take the 2’s complement of this, you get
A" = 0111
which is the original word.
In general, this means that
Chapter 1 used an odometer to introduce binary numbers.
The discussion was about positive numbers only. But
odometer readings can also indicate negative numbers.
Here’s how.
If a car has a binary odometer, all bits eventually reset
to 0s. A few readings before and after a complete reset
look like this:
1101
1110
1111
0000 (reset)
0001
0010
0011
1101 is the reading 3 miles before reset, 1110 occurs 2
miles before reset, and 1111 indicates 1 mile before reset.
Then, 0001 is the reading 1 mile after reset, 0010 occurs
2 miles after reset, and 0011 indicates 3 miles after reset.
“Before” and “after” are synonymous with “negative”
and “positive.” Figure 6-6 illustrates this idea with the
number line learned in basic algebra: 0 marks the origin,
positive decimal numbers are on the right, and negative
decimal numbers are on the left. The odometer readings
are the binary equivalent of positive and negative decimal
numbers: 1101 is the binary equivalent of - 3, 1110 stands
for -2, 1111 for - 1; 0000 for 0; 0001 for + 1; 0010 for
+ 2, and 0011 for +3.
The odometer readings of Fig. 6-6 demonstrate how
positive and negative numbers are stored in a typical
microcomputer. Positive decimal numbers are expressed in
sign-magnitude form, but negative decimal numbers are
represented as 2’s complements. As before, positive num¬
bers have a leading sign bit of 0, and negative numbers
have a leading sign bit of 1.
A" = A (6-12)
Read this as “the double complement of A equals A.”
Because of this property, the 2’s complement of a binary
number is equivalent to the negative of a decimal number.
This idea is explained in the following discussion.
2’s Complement Same as Decimal Sign Change
Taking the 2’s complement of a binary number is the same
as changing the sign of the equivalent decimal number. For
example, if
A = 0001 (-hi in Fig. 6-6)
1101 mo 1111 0000 0001 0010 0011
-• - • • - •--•-•-#-
-3 -2 -1 0 +1 +2 +3
Fig. 6-6 Decimal numbers and odometer readings.
84 Digital Computer Electronics
taking the 2’s complement gives
SOLUTION
A' - 1111 (-1 in Fig. 6-6)
Decimal + 5 is expressed in sign-magnitude form:
Similarly, if
+ 5 = 0000 0101
A - 0010 ( + 2 in Fig. 6-6)
On the other hand, —5 appears as the 2’s complement:
then the 2’s complement is
A' = 1110 (-2 in Fig. 6-6)
Again, if
A = 0011 ( + 3 in Fig. 6-6)
the 2’s complement is
A' = 1101 (-3 in Fig. 6-6)
The same principle applies to binary numbers of any
length: taking the 2’s complement of any binary number is
the same as changing the sign of the equivalent decimal
number. As will be shown later, this property allows us to
use a binary adder for both addition and subtraction.
-5 = 1111 1011
EXAMPLE 6-7
What is the 2’s-complement representation of —24 in a
16-bit microcomputer?
SOLUTION
Start with the positive form:
+ 24 = 0000 0000 0001 1000
Then take the 2’s complement to get the negative form:
-24 = mi ini mo iooo
Summary
Here are the main things to remember about 2’s complement
representation:
1. The leading bit is the sign bit; 0 for plus, 1 for minus.
2. Positive decimal numbers are in sign-magnitude form.
3. Negative decimal numbers are in 2’s-complement form.
EXAMPLE 6-5
What is the 2’s complement of this word?
A = 0011 0101 1001 1100
SOLUTION
The 2’s complement is
A' = 1100 1010 0110 0100
EXAMPLE 6-6
What is the binary form of +5 and -5 in 2’s-complement
representation? Express the answers as 8-bit numbers.
EXAMPLE 6-8
What decimal number does this represent in 2’s-complement
representation?
mi oooi
SOLUTION
Start by taking the 2’s complement to get
0000 1111
This represents +15. Therefore, the original number is
1111 0001= -15
6-8 2’s-COMPLEMENT ADDER-
SUBTRACTER
Early computers used signed binary for both positive and
negative numbers. This led to complicated arithmetic cir¬
cuits. Then, engineers discovered that the 2’s-complement
representation could greatly simplify arithmetic hardware.
Chapter 6 Arithmetic-Logic Units 8 5
This is why 2’s-complement adder-subtracters are now the
most widely used arithmetic circuits.
Addition
Figure 6-7 shows a 2’s-complement adder-subtracter, a
logic circuit that can add or subtract binary numbers. Here’s
how it works. When SUB is low, the B bits pass through
the controlled inverter without inversion. Therefore, the
full adders produce the sum
S = A + B (6-13)
Incidentally, as indicated in Fig. 6-7, the final CARRY
is not used. This is because S 3 is the sign bit and S 2 to 5 0
are the numerical bits. The final CARRY therefore has no
significance at this time.
Subtraction
When SUB is high, the controlled inverter produces the l’s
complement. Furthermore, the high SUB adds a 1 to the
first full adder. This addition of 1 to the l’s complement
forms the 2’s complement_of B. In other words, the
controlled inverter produces B, and adding 1 results in B\
The output of the full adders is
S = A + B' (6-14)
which is equivalent to
S = A - B (6-15)
because the 2’s complement is equivalent to a sign change.
EXAMPLE 6-9
A 7483 is a TTL circuit with four full adders. This means
that it can add nibbles (4-bit numbers).
Figure 6-8 shows a TTL adder-subtracter. The CARRY
out (pin 14) of the least significant nibble is used as the
CARRY in (pin 13) for the most significant nibble. This
allows the two 7483s to add 8-bit numbers. Two 7486s
form the controlled inverter needed for subtraction.
Fig. 6-8 TTL adder-subtracter.
86 Digital Computer Electronics
Suppose the circuit has these inputs:
A = 0001 1000
B = 0001 0000
If SUB = 0, what is the output of the adder-subtracter?
SOLUTION
When SUB is 0, the adder-subtracter adds the two inputs
as follows:
0001 1000
+ 0001 0000
0010 1000
Therefore, the output is 0010 1000. Notice that the decimal
equivalent of the foregoing addition is
24
+ 16
40
EXAMPLE 6-10
Repeat the preceding example for SUB = 1.
SOLUTION
When SUB is 1, the adder-subtracter subtracts the inputs
by adding the 2’s complement as follows:
The decimal equivalent is
24
+ -16
8
EXAMPLE 6-11
In Fig. 6-8, what are the largest positive and negative sums
we can get?
SOLUTION
The largest positive output is
0111 1111
which represents decimal +127. The largest negative output
is
1000 0000
which represents — 128. With 8 bits, therefore, all answers
must lie between —128 and +127. If you try to add
numbers with a sum outside this range, you get an overflow
into the sign-bit position, causing an error.
Chapter 12 discusses the overflow problem in more detail.
All you have to remember for now is that an overflow or
error will occur if the true sum lies outside the range of
-128 to +127.
0001 1000
+ 1111 0000
0000 1000
GLOSSARY
ALU Arithmetic-logic unit. The ALU carries out arith¬
metic and logic operations.
binary adder A logic circuit that can add two binary
numbers.
full adder A logic circiut that can add 3 bits.
half-adder A logic circuit that adds 2 bits.
overflow In 2’s-complement representation, a carry into
the sign-bit position, which results in an error. For an 8-
bit adder-substracter, the true sum must lie between —128
and +127 to avoid overflow.
signed binary A system in which the leading bit represents
the sign and the remaining bits the magnitude of the number.
Also called sign magnitude.
2’s complement The new number you get when you take
the Fs complement and then add 1.
Chapter 6 Arithmetic-Logic Units 87
SELF-TESTING REVIEW
Read each of the following and provide the missing words.
Answers appear at the beginning of the next question.
1. The ALU carries out arithmetic and_op¬
erations (or, and, not, etc.). It processes_
numbers rather than decimal numbers.
2. {logic, binary) A half-adder adds-bits. A
full adder adds_bits, producing a SUM
and a_
3. (two, three , CARRY) A binary adder is a logic cicuit
that can add_binary numbers at a time.
The 7483 is a TTL binary adder. It can add two 4-bit
binary numbers.
4. (two) With signed binary numbers, also known as
sign-magnitude numbers, the leading bit stands for
the_and the remaining bits for the
5. (sign, magnitude ) Signed binary numbers require too
much hardware. This has led to the use of_
complements to represent negative numbers. To get
the 2’s complement of a binary number, you first
take the complement, then add
6. (2*s y Vs, 1) If you take the 2’s complement twice,
you get the original binary number back. Because of
this property, taking the-complement of
a binary number is equivalent to changing the sign of
a decimal number.
7. (2’s) In a microcomputer positive numbers are repre¬
sented in_form and negative numbers in
2’s-complement form. The leading bit still represents
the_
8. ( sign-magnitude , sign) A 2’s-complement adder-sub¬
tracter can add or subtract binary numbers. Sign-
magnitude numbers represent-decimal
numbers, and 2’s complements stand for-
decimal numbers. You can tell one from the other by
the leading bit, which represents the-
9. (positive , negative , sign) With 2’s-complement repre¬
sentation and an 8-bit adder-subtracter no overflow is
possible if the true sum is between — 128 and +127.
PROBLEMS
6-L Add these 8-bit numbers:
a. 0001 0000 and 0000 1000
b. 0001 1000 and 0000 1100
c. 0001 1100 and 0000 1110
d. 0010 1000 and 0011 1011
After you have each binary sum, convert it to
hexadecimal form.
6-2. Add these 16-bit numbers:
1000 0001 1100 1001
+ 0011 0011 0001 0111
Express the answer in hexadecimal form.
6-3. In each of the following, convert to binary to do
the addition, then convert the answer back to
hexadecimal:
a. 2CH + 4FH = ?
b. 5EH + 1AH = ?
c. 3BH + 6DH = ?
d. A5H + 2CH = ?
6-4. Convert each of the following decimal numbers to
an 8-bit sign-magnitude number:
a. +27
b. -27
c. + 80
d. -80
After you have the sign-magnitude numbers, convert
them to hexadecimal form.
88 Digital Computer Electronics
6-5. Convert each of these sign-magnitude numbers to
its decimal equivalent:
a. 0001 1110
b. 1000 0111
c. 1001 1100
d. 0011 0001
6-6. The following hexadecimal numbers represent
sign-magnitude numbers. Convert each to its deci
mal equivalent.
a. 8FH
b. 3AH
c. 7FH
d. FFH
6-7. Find the 2’s complements:
a. 0000 0111
b. mi mi
c. nn noi
d. 1110 0001
Express your answers in hexadecimal form.
6-8. Convert each of the following to binary. Then
take the 2’s complement:
a.
4CH
b.
8DH
c.
CBH
d.
FFH
Fig. 6-9
After you have the 2’s complements, convert them
to hexadecimal form.
6-9. An 8-bit microprocessor uses 2’s-complement rep¬
resentation. How do the following decimal num¬
bers appear:
a. -19
b. -48
c. +37
d. -33
Express your answers in binary and hexadecimal
form.
6-10. The output of an ALU is EEH. What decimal
number does this represent in 2’s-complement
representation?
6-11. Suppose the inputs to Fig. 6-9 are A = 3CH and
B = 5FH. What is the output for a low SUB? A
high SUB? Express your final answers in hexa¬
decimal form.
6-12. In Fig. 6-9 which of the following inputs cause an
overflow when SUB is low?
a. 2DH and 4BH
b. 8FH and C3H
c. 5EH and B8H
d. 23H and 14H
6-13. Why are applications for the half-adder limited,
what does the full adder do which makes it more
useful than the half-adder, and what can be done
with a full adder as a result of this feature?
6-14. Since sign-magnitude numbers are fairly easy to
understand, why has the 2’s-complement system
become so widespread?
Chapter 6 Arithmetic-Logic Units 83
Flip-Flops
Gates are decision-making elements. As shown in the
preceding chapter, they can perform binary addition and
subtraction. But decision-making elements are not enough.
A computer also needs memory elements , devices that can
store a binary digit. This chapter is about memory elements
called flip-flops.
7-1 RS LATCHES
A flip-flop is a device with two stable states; it remains in
one of these states until triggered into the other. The RS
latch, discussed in this section, is one of the simplest flip-
flops.
Transistor Latch
In Fig. 7-la each collector drives the opposite base through
a 100-kH resisitor. In a circuit like this, one of the transistors
is saturated and the other is cut off.
For instance, if the right transistor is saturated, its collector
voltage is approximately 0 V. This means that there is no
base drive for the left transistor, so it cuts off and its
collector voltage approaches +5 V. This high voltage
produces enough base current in the right transistor to
sustain its saturation. The overall circuit is latched with the
left transistor cut off (dark shading) and the right transistor
saturated. Q is approximately 0 V.
By a similar argument, if the left transistor is saturated,
the right transistor is cut off. Figure l-\b illustrates this
other state. Q is approximately 5 V for this condition.
Output Q can be low or high, binary 0 or 1. If latched
as shown in Fig. 7-la, the circuit is storing a binary 0
because
Q = 0
On the other hand, when latched as shown in Fig. 1-lb ,
the circuit stores a binary 1 because
0 - 1
Control Inputs
To control the bit stored in the latch, we can add the inputs
shown in Fig. 7-lc. These control inputs will be either low
(0 V) or high ( + 5 V). A high set input S forces the left
transistor to saturate. As soon as the left transistor saturates,
the overall circuit latches and
Q = 1
Once set, the output will remain a 1 even though the S
input goes back to 0 V.
A high reset input R drives the right transistor into
saturation. Once this happens, the circuit latches and
0 = 0
The output stays latched in the 0 state, even though the R
input returns to a low.
In Fig. 7-lc, Q represents the stored bit. A complementary
output Q is available from the collector of the left transistor.
This may or may not be used, depending on the application.
Truth Table
Table 7-1 summarizes the operation of the transistor latch.
With both control inputs low, no change can occur in the
output and the circuit remains latched in its last state. This
condition is called the inactive state because nothing
changes.
TABLE 7-1. TRANSISTOR
LATCH
R
s
Q
Comments
0
0
NC
No change
0
1
1
Set
1
0
0
Reset
1
1
*
Race
90
+5 V +5 V
+5 V
(c)
Fig. 7-1 (a) Latched state; ( b ) alternative state; (c) trigger inputs.
When R is low and S is high, the circuit sets the Q output
to a high. On the other hand, if R is high and S is low, the
Q output resets to a low.
Race Condition
Look at the last entry in Table 7-1. R and S are high
simultaneously. This is called a race condition; it is never
used because it leads to unpredictable operation.
Here’s why. If both control inputs are high, both tran¬
sistors saturate. When the R and S inputs return to low,
both transistors try to come out of saturation. It is a race
between the transistors to see which one desaturates first.
The faster transistor (the one with the shorter saturation
delay time) will win the race and latch the circuit. If the
faster transistor is on the left side of Fig. 7-lc, the Q output
will be low. If the faster transistor is on the right side, the
Q output will go high. In mass production, either transistor
can be faster; therefore, the Q output is unpredictable. This
is why the race condition must be avoided.
Here’s how to recognize a race condition. If simultane¬
ously changing both inputs to a memory element leads to
an unpredictable output, you’ve got a race condition. With
the transistor latch, R = 1 and S = 1 is a race condition
because simultaneously returning R and S to 0 forces Q
into a random state.
From now on, an asterisk in a truth table (see Table
7-1) indicates a race condition, sometimes called a forbidden
or invalid state.
nor Latches
A discrete circuit like Fig. 7-lc is rarely used because we
are in the age of integrated circuits. Nowadays, you build
RS latches with nor gates or nand gates.
Figure l-2a shows how it’s done with nor gates. Figure
l-2b is the De Morgan equivalent. As shown in Table
7-2, a low R and a low S give us the inactive state; the
circuit stores or remembers. A low R and a high S represent
the set state, while a high R and a low S give the reset
state. Finally, a high R and a high S produce a race
condition; therefore, we must avoid R = 1 and S = 1
when using a NOR latch.
Figure 7-2c is a timing diagram; it shows how the input
signals interact to produce the output signal. As you see,
the Q output goes high when S goes high. Q remains high
after S goes low. Q returns to low when R goes high, and
stays low after R returns to low.
Chapter 7 Flip-Flops 91
TABLE 7-2. nor LATCH
TABLE 7-3. nand LATCH
R
5
Q
Comment
0
NC
No change
0
1
1
Set
1
0
Reset
1
1
*
Race
R
s
Q
Comment
0
0
*
Race
0
1
1
Set
1
0
0
Reset
1
1
NC
No change
(a)
(b)
R
s _I
I
Q
(c)
Fig. 7-2 (a) nor latch; ( b) De Morgan equivalent; (c) timing
diagram.
nand Latches
If you prefer using nand gates, you can build an RS latch
as shown in Fig. 7-3 a. Sometimes it is convenient to draw
the De Morgan equivalent shown in Fig. 7-3/?. In either
case, a low R and a high 5 set Q to high; a high R and a
low 5 reset Q to low.
Because of the NAND-gate inversion, the inactive and
race conditions are reversed. In other words, R = 1 and 5
= 1 becomes the inactive state; R = 0 and 5 = 0 becomes
the race condition (see Table 7-3). Therefore, whenever
you use a nand latch, you must avoid having both inputs
low at the same time. (To remember the race condition for
a nand latch, glance at Fig. 7-3/?. If R = 0 and 5 = 0,
then Q — 1 and 0=1; both outputs are the same,
indicating an invalid condition.)
R
1_1
1_1
1
1
1
(c)
Fig. 7-3 (a) nand latch; (/?) De Morgan equivalent; (c) timing
diagram.
Figure'7-3c shows the timing diagram for a nand latch.
R and 5 are normally high to avoid the race condition. Only
one of them goes low at any time. As you see, the Q output
goes high whenever R goes low; the Q output goes low
whenever 5 goes low.
Switch Debouncers
RS latches are often used as switch debouncers. Whenever
you throw a switch from the open to the closed position,
the contacts bounce and the switch alternately makes and
breaks for a few milliseconds before finally settling in the
closed position. One way to eliminate the effects of contact
bounce is to use an RS latch in conjunction with the switch.
The following example explains the idea.
92 Digital Computer Electronics
Fig. 7-4 Switch debouncer.
EXAMPLE 7-1
Figure 1-Aa shows a switch debouncer. What does it do?
SOLUTION
As discussed in Chap. 4, floating TTL inputs are equivalent
to high inputs. With the switch in th e STA RT position, pin
1 is low and pin 5 is high; therefore, CLR is high and CLR
is low. When the switch is thrown to the clear position,
pin 1 goes high, as shown in Fig. 1-Ab. Because of contact
bounce, pin 5 goes alternately low and high for a few
milliseconds before settling in the low state, symbolized
by the ideal pulses of Fig. 7-4b.The first time pin 5 goes
low, the latch sets, CLR going high and CLR going low.
Subsequent bounces have no effect on CLR and CLR because
the latch stays set.
Similarly, when the switch is thrown back to start, pin
1 bounces low and high for a while. The first time pin 1
goes low, CLR goes back to low and CLR to high. Later
bounces have no effect on CLR and CLR.
Registers need clean signals like CLR and CLR of Fig.
1-Ab to operate properly. If the bouncing signals on pins 1
and 5 drove the registers, the operation would be erratic.
This is why you often see RS latches used as switch
debouncers.
7-2 LEVEL CLOCKING
Computers use thousands of flip-flops. To coordinate the
overall action, a square-wave signal called the clock is sent
to each flip-flop. This signal prevents the flip-flops from
changing states until the right time.
Clocked Latch
In Fig. l-5a a pair of nand gates drive a nand latch. S
and R signals drive the input gates. To avoid confusion,
the inner control signals are labeled R' and S'. The nand
latch works as previously described; a low R' and a high
S' set Q to 1, whereas a high R ' and a low S' reset Q to
0. Furthermore, a low R' and S' represent the race condition;
therefore, R' and S' are normally high when the latch is
inactive. Because of the inversion through the input nand
gates, the S input has to drive the upper nand input and
the R input must drive the lower nand input.
Double Inversions Cancel
When analyzing the operation of this and similar circuits,
remember that a double inversion (two bubbles in a series
path) cancels out; this makes it appear as though two and
gates drove or gates, as shown in Fig. 7-5 b. In this way,
you can see at a glance that a high S and high CLK force
Chapter 7 Flip-Flops S3
(c)
Fig. 7-5 (a) Clocked latch; ( b ) equivalent circuit; (c) timing
diagram.
Q to go high. In other words, even though you are looking
at Fig. 7-5a, in your mind you should see Fig. l-5b.
Positive Clocking
In Fig. l-5a the clock is a square-wave signal. Because the
clock (abbreviated CLK) drives both nand gates, a low
CLK prevents S and R from controlling the latch. If a high
S and a low R drive the gate inputs, the latch must wait
until the clock goes high before Q can be set to 1. Similarly,
given a low S and a high R 7 the latch must wait for a high
CLK before Q can reset to 0. This is an example of positive
clocking, making a latch wait until the clock signal is high
before the output can change.
Negative clocking is similar. Visualize an inverter be¬
tween CLK and the input gates of Fig. 7-5a. In this case,
the latch must wait until CLK is low before the output can
change.
Positive and negative clocking are often called level
clocking because the flip-flop responds to the level (high
or low) of the clock signal. Level clocking is the simplest
way to control flip-flops with a clock. Later, we will discuss
more advanced methods called edge triggering and master-
slave clocking.
Race Condition
What about the race condition? When the clock is low in
Fig. 7-5n, R f and S' are high, which is a stable condition.
The only way to get a race condition is to have a high
CLK, high R, and high S. Therefore, normal operation of
this circuit requires that R and S never both be high when
the clock goes high.
Timing Diagram and Truth Table
Figure 7-5c shows the timing diagram. Q goes high when
S is high and CLK goes high. Q returns to the low state
when R is high and CLK goes high. Using a common CLK
signal to drive many flip-flops allows us to synchronize the
operation of the different sections of a computer.
Table 7-4 summarizes the operation of the clocked nand
latch. When the clock is low, the output is latched in its
last state. When the clock goes high, the circuit will set if
S is high or reset if R is high. CLK , R, and S all high is a
race condition, which is never used deliberately.
TABLE 7-4. CLOCKED
nand LATCH
CLK
R
s
Q
0
0
0
NC
0
0
1
NC
0
1
0
NC
0
1
1
NC
1
0
0
NC
1
0
1
1
1
1
0
0
1
1
1
*
94 Digital Computer Electronics
7-3 D LATCHES
Since the RS flip-flop is susceptible to a race condition, we
will modify the design to eliminate the possibility of a race
condition. The result is a new kind of flip-flop known as a
D latch.
Unclocked
Figure 7-6 shows one way to build a D latch. Because of
the inverter, data bit D_ drives the S input of a nand latch
and the complement D drives the R input. Therefore, a
high D sets the latch, and a low D resets it. Table 7-5
summarizes the operation of the D latch. Especially im¬
portant, there is no race condition in this truth table. The
inverter guarantees that S and R will always be in opposite
states; therefore, it’s impossible to set up a race condition
in the D latch.
The D latch of Fig. 7-6 is unclocked; it will set or reset
as soon as D goes high or low. An unclocked flip-flop like
this is almost never used.
TABLE 7-5.
UNCLOCKED
D LATCH
~j> Q
0 0
1 1
Clocked
Figure 1-1 a is level-clocked. A low CLK disables the input
gates and prevents the latch from changing states. In other
words, while CLK is low, the latch is in the inactive state
and the circuit stores or remembers. When CLK is high, D
controls the output. A high D sets the latch, while a low
D resets it.
Table 7-6 summarizes the operation. X represents a don’t-
care condition; it stands for either 0 or 1. While CLK is
low, the output cannot change, no matter what D is. When
CLK is high, however, the output equals the input
Q = D
Figure 1-lb shows a timing diagram. If the clock is low,
the circuit is latched and the Q output cannot be changed.
While the clock is high, however, Q equals D; when D
goes high, Q goes high; when D goes low, Q goes low.
The latch is transparent, meaning that the output follows
the value of D while the clock is high.
TABLE 7-6.
CLOCKED
D LATCH
CLK
D
Q
0
X
NC
1
0
0
1
1
1
Chapter 7 Flip-Flops 95
Disadvantage
Because the D latch is level-clocked, it has a serious
disadvantage. While the clock is high, the output follows
the value of D. Transparent latches may be all right in
some applications but not in the computer circuits we will
be discussing. To be truly useful, the circuit of Fig. 1-1 a
needs a slight modification.
7-4 EDGE-TRIGGERED
D FLIP-FLOPS
Now we’re ready to talk about the most common type of
D flip-flop. What a practical computer needs is a D flip-
flop that samples the data bit at a unique instant.
Edge Triggering
Figure 1-Sa shows an RC circuit at the input of a D flip-
flop. By deliberate design, the RC time constant is much
smaller than the clock’s pulse width. Because of this, the
capacitor can charge fully when CLK goes high; this
exponential charging produces a narrow positive voltage
spike across the resistor. Later, the trailing edge of the
clock pulse results in a narrow negative spike.
The narrow positive spike enables the input gates for an
instant; the narrow negative spike does nothing. The effect
is to activate the input gates during the positive spike,
equivalent to sampling the value of D for an instant. At
this unique time, D and its complement hit the flip-flop
inputs, forcing Q to set or reset.
TABLE 7-7.
EDGE-
TRIGGERED
D FLIP-FLOP
CLK
D
Q
0
X
NC
1
X
NC
i
X
NC
t
0
0
t
1
1
This kind of operation is called edge triggering because
the flip-flop responds only when the clock is changing
states. The triggering in Fig. 7-8a occurs on the positive¬
going edge of the clock; this is why it’s referred to as
positive-edge triggering.
Figure 7-8 b illustrates the action. The crucial idea is that
the output changes only on the rising edge of the clock. In
other words, data is stored only on the positive-going edge.
Table 7-7 summarizes the operation of the positive-edge-
triggered D flip-flop. The up and down arrows represent
the rising and falling edges of the clock. The first three
entries indicate that there’s no output change when the
clock is low, high, or on its negative edge. The last two
entries indicate an output change on the positive edge of
the clock. In other words, input data D is stored only on
the positive-going edge of the clock.
(b)
Fig. 7-8 Edge-triggered D flip-flop.
96 Digital Computer Electronics
Edge Triggering versus Level Clocking
When a circuit is edge-triggered, the output can change
only on the rising (or falling) edge of the clock. But when
the circuit is level-clocked, the output can change while
the clock is high (or low). With edge triggering, the output
can change only at one instant during the clock cycle; with
level clocking, the output can change during an entire half
cycle of the clock.
Preset and Clear
When power is first applied, flip-flops come up in random
states. To get some computers started, an operator has to
push a master reset button. This sends a clear (reset) signal
to all flip-flops. Also, it is necessary in some computers to
preset (synonymous with “set”) certain flip-flops before a
computer run.
Figure 7-9 shows how to include both functions in a D
flip-flop. The edge triggering is the same as previously
described. In addition, the and gates allow us to slip in a
low PRESET or low CLEAR when desired. A low PRESET
forces Q to equal 1; a low CLEAR resets Q to 0.
Table 7-8 summarizes the circuit action. When PRESET
and CLEAR are both low, we get a race condition; therefore,
PRESET and CLEAR should be kept high when inactive.
Take PRESET low by itself and you set the flip-flop; take
CLEAR low by itself and you reset the flip-flop. As shown
in the remaining entries, the output changes only on the
positive-going edge of the clock.
Preset is sometimes called direct set , and clear is some¬
times called direct reset. The word “direct” means un¬
clocked. For instance, the clear signal may come from a
push button; regardless of what the clock is doing, the
output will reset when the operator pushes the clear button.
The preset and clear inputs override the other inputs;
they have first priority. For example, when PRESET goes
low, the Q output goes high and stays there no matter what
the D and CLK inputs are doing. The output will remain
high as long as PRESET is low. Therefore, the normal
procedure in presetting is to take the PRESET low tempo-
Fig. 7-9 Edge-triggered D flip-flop with preset and clear.
TABLE 7-8. D FLIP-FLOP WITH
PRESET AND CLEAR
PRESET CLEAR
CLK
D
Q
0
0
X
X
*
0
1
X
X
1
1
0
X
X
0
1
1
0
X
NC
1
1
1
X
NC
1
1
1
X
NC
1
1
t
0
0
1
1
t
1
1
rarily, then return it to high. Similarly, for the clear function:
take CLEAR low briefly to reset the flip-flop, then take
it back to high to allow the circuit to operate.
Direct-Coupled Edge-Triggered D Flip-Flop
Integrated D flip-flops do not use RC circuits to get narrow
spikes because capacitors are difficult to fabricate on a
chip. Instead, a variety of direct-coupled designs is used.
As an example, Fig. 7-10 shows a positive-edge-triggered
D flip-flop. This direct-coupled circuit has no capacitors,
only nand gates. The analysis is too long and complicated
to go into here, but the idea is the same as previously
discussed. The circuit responds only during the brief instant
the clock switches from low to high. That is, data bit D is
stored only on the positive-going edge of the clock.
Logic Symbol
Figure 7-11 is the symbol of a positive-edge-triggered D
flip-flop. The CLK input has a small triangle, a reminder
of the edge triggering. When you see this schematic symbol,
remember what it means: the D input is stored on the rising
edge of the clock.
PRESET
Chapter 7 Flip-Flops
97
Fig. 7-10 Direct-coupled edge-triggered D flip-flop.
Fig. 7-11 Logic symbol for edge-triggered D flip-flop.
Figure 7-11 also includes preset (PR) and clear ( CLR )
inputs. The bubbles indicate an active low state . In other
words, the preset and clear inputs are high when inactive.
To preset the flip-flop, the preset input must go low
temporarily and then be returned to high. Similarly, to reset
the flip-flop, the clear input must go low, then back to
high.
The same idea applies to circuits discussed later. A
bubble at an input means an active low state: the input has
to go low to produce an effect. When no bubble is present,
the input has to go high to have an effect.
Propagation Delay Time
Diodes and transistors cannot switch states instantaneously.
It always takes a small amount of time to turn a diode on
or off. Likewise, it takes a time for a transistor to switch
from saturation to cutoff or vice versa. For bipolar diodes
and transistors, switching time is in the nanosecond region.
Switching time is the main cause of propagation delay
time t p . This represents the amount of time it takes for the
output of a gate or flip-flop to change states. For instance,
if the data sheet of a D flip-flop indicates a t p of 10 ns, it
takes approximately 10 ns for Q to change states after D
has been sampled by the clock edge.
Propagation delay time is so small that it’s negligible in
many applications, but in high-speed circuits you have to
take it into account. If a flip-flop has a t p of 10 ns, this
means that you have to wait 10 ns before the output can
trigger another circuit.
Setup Time
Stray capacitance at the D input (plus other factors) makes
it necessary for data bit D to be at the input before the CLK
edge arrives. The setup time f setup is the minimum length
of time the data bit must be present before the CLK edge
hits.
For instance, if the data sheet of a D flip-flop indicates
a t setup of 15 ns, the data bit to be stored must be at the D
input at least 15 ns before the CLK edge arrives; otherwise,
the IC manufacturer does not guarantee correct sampling
and storing.
Hold Time
Furthermore, data bit D has to be held long enough for the
internal transistors to switch states. Only after the transition
is assured can we allow data bit D to change. Hold time
t hold is the minimum length of time the data bit must be
present after the CLK edge has struck.
For example, if r setup is 15 ns and r hold is 5 ns, the data
bit has to be at the D input at least 15 ns before the CLK
edge arrives and held at least 5 ns after the CLK edge hits.
98 Digital Computer Electronics
7-5 EDGE-TRIGGERED
JK FLIP-FLOPS
The next chapter shows you how to build a counter, the
electronic equivalent of a binary odometer. When it comes
to circuits that count, the JK flip-flop is the ideal memory
element to use.
Circuit
Figure l-\2a shows one way to build a JK flip-flop. As
before, an RC circuit with a short time constant converts
the rectangular CLK pulse to narrow spikes. Because of the
double inversion through the nand gates, the circuit is
positive-edge-triggered. In other words, the input gates are
enabled only on the rising edge of the clock.
Inactive
The J and K inputs are control inputs; they determine what
the circuit will do on the positive clock edge. When J and
K are low, both input gates are disabled and the circuit is
inactive at all times including the rising edge of the clock.
Reset
When J is low and K is high, the upper gate is disabled;
so there’s no way to set the flip-flop. The only possibility
is reset. When Q is high, the lower gate passes a reset
trigger as soon as the positive clock edge arrives. This
forces Q to become low. Therefore, 7 = 0 and K = 1
means that a rising clock edge resets the flip-flop.
Set
When 7 is high and K is low, the lower gate is disabled;
so it’s impossible to reset the flip-flop_But you can set the
flip-flop as follows. When Q is low, Q is high; therefore,
the upper gate passes a set trigger on the positive clock
edge. This drives Q into the high state. That is, 7 = 1 and
K = 0 means that the next positive clock edge sets the
flip-flop.
Toggle
When 7 and K are both high, it is possible to set or reset
the flip-flop, depending on the current state of the output.
If Q is high, the lower gate passes a reset trigger on the
(b)
Fig. 7-12 (a) Edge-triggered JK flip-flop; ( b ) timing diagram.
Chapter 7 Flip-Flops 99
TABLE 7-9. POSITIVE-
EDGE-TRIGGERED
JK FLIP-FLOP
CLK
J
K
Q
0
X
X
NC
1
X
X
NC
1
X
X
NC
X
0
0
NC
t
0
1
0
t
1
0
1
t
1
1
Toggle
next positive clock edge. On the other hand, when Q is
low, the upper gate passes a set trigger on the next positive
clock edge. Either way, Q changes to the complement of
the last state. Therefore, J = 1 and K = 1 means that the
flip-flop will toggle on the next positive clock edge.
(“Toggle” means switch to opposite state.)
Timing Diagram
The timing diagram of Fig. l-\2b is a visual summary of
the action. When J is high and K is low, the rising clock
edge sets Q to high. On the other hand, when J is low and
K is high, the rising clock edge resets Q to low. When J
and K are high simultaneously, the output toggles on each
rising clock edge.
Truth Table
Table 7-9 summarizes the operation. The circuit is inactive
when the clock is low, high, or on its negative edge.
Likewise, the circuit is inactive when J and K are both
low. Output changes occur only on the rising edge of the
clock, as indicated by the last three entries of the table.
The output either resets, sets, or toggles.
Racing
The JK flip-flop shown in Fig. 7-12a has to be edge-
triggered to avoid oscillations. Why? Assume that the circuit
is level-clocked. In other words, assume that we remove
the RC circuit and run the clock straight into the gates.
With a high /, high K, and high CLK , the output will
toggle. New outputs are then fed back to the input gates.
After two propagation times (input and output gates), the
output toggles again. And once more, new outputs return
to the input gates. In this way, the output can toggle
repeatedly as long as the clock is high. That is, we get
oscillations during the positive half cycle of the clock.
Toggling more than once during a clock cycle is called
racing .
Now assume that we put the RC circuit back in and
return to edge triggering. Propagation delay time prevents
the JK flip-flop from racing. Here’s why. In Fig. 7-12cz the
outputs change after the positive clock edge has struck. By
the time the new Q and Q signals return to the input gates,
the positive spikes have decayed to zero. This is why we
get only one toggle during each clock cycle.
For instance, if the total propagation delay time from
input to output is 20 ns, the outputs change approximately
20 ns after the rising edge of the clock. If the spikes are
narrower than 20 ns, the returning Q and Q arrive too late
to cause false triggering.
Symbols
As previously mentioned, capacitors are too difficult to
fabricate on a chip. This is why manufacturers prefer direct-
coupled designs for edge-triggered JK flip-flops. Such
designs are too complicated to reproduce here, but you can
find them in manufacturers’ IC data books.
Figure 7-13a is the standard symbol for a positive-edge-
triggered JK flip-flop of any design.
Figure 7-13/? is the symbol for a JK flip-flop with the
preset and clear functions. As usual, PR and CLR have
active low states. This means that they are normally high
and taken low temporarily to preset or clear the circuit.
Figure 7-13c is another commercially available JK flip-
flop. The bubble on the clock input is the standard way to
indicate negative-edge triggering. As shown in Table 7-10,
the output can change only on th t falling edge of the clock.
The timing diagram of Fig. 7-13d emphasizes this negative-
edge triggering.
7-6 JK MASTER-SLAVE FLIP-FLOP
Figure 7-14 shows a JK master-slave flip-flop, another way
to avoid racing. A master-slave flip-flop is a combination
of two clocked latches; the first is called the master , and
the second is the slave . Notice that the master is positively
TABLE 7-10. NEGATIVE-
EDGE-TRIGGERED
JK FLIP-FLOP
CLK
J
K
Q
0
X
X
NC
1
X
X
NC
t
X
X
NC
X
0
0
NC
1
0
1
0
1
1
0
1
1
1
1
Toggle
1OO Digital Computer Electronics
(a)
(b)
(c)
J
K
Q
(d)
Fig. 7-13 (a) Positive-edge triggering; ( b ) active low preset and
clear; (c) negative-edge triggering; ( d) timing diagram.
Fig. 7-14 Master-slave JK flip-flop.
clocked but the slave is negatively clocked. This implies
the following:
1. While the clock is high, the master is active and the
slave is inactive.
2. While the clock is low, the master is inactive and the
slave is active.
Set
To start the analysis, let’s assume low Q and high Q. For
an input condition of high J, low K , and high CLK , the
master goes into the set state, producing high S and low R .
Nothing happens to the Q and Q outputs because the slave
is inactive while the clock is high. When the clock goes
low, however, the high S and low R force the slave into
the set state, producing a high Q and a low Q.
There are two distinct steps in setting the final Q output.
First, the master is set while the clock is high. Second, the
slave is set while the clock is low. This action is sometimes
called cocking and triggering. You cock the master during
the positive half cycle of the clock, and you trigger the
slave during the negative half cycle of the clock.
Chapter 7 Flip-Flops 101
Reset
When the slave is set, Q is high and Q is low. For the
input condition of low 7, high K , and high CLK, the master
will reset, forcing S to go low and R to go high. Again,
no changes can occur in Q and Q because the slave is
inactive while the clock is high. When the clock returns to
the low state, the low S and high R force the slave to reset;
this forces Q to go low and Q to go high.
Again, notice the cocking and triggering. This is the key
idea behind the master-slave flip-flop. Every action of the
master with a high CLK is copied by the slave when the
clock goes low.
Toggle
If the 7 and K inputs are both high, the master toggles once
while the clock is high; the slave then toggles once when
the clock goes low. No matter what the master does, the
slave copies it. If the master toggles into the set state, the
slave toggles into the set state. If the master toggles into
the reset state, the slave toggles into the reset state.
Level Clocking
The master-slave flip-flop is level-clocked in Fig. 7-14.
While the clock is high, therefore, any changes in 7 and K
can affect the S and R outputs. For this reason, you normally
keep J and K constant during the positive half cycle of the
clock. After the clock goes low, the master becomes inactive
and you can allow 7 and K to change.
Fig. 7-15 Symbol for master-slave JK flip-flop.
Symbol
Figure 7-15 shows the symbol for a JK master-slave flip-
flop with preset and clear functions. The bubble on the
CLK input reminds us that the output changes when the
clock goes low.
Truth Table
Table 7-11 summarizes the operation of a JK master-slave
flip-flop. A low PR and low CLR produces a race condition;
therefore, PR and CLR are normally kept at a high voltage
102 Digital Computer Electronics
TABLE 7-11. MASTER-SLAVE FLIP-FLOP
PR
CLR
CLK
j
K
Q
0
0
X
X
X
*
0
1
X
X
X
1
1
0
X
X
X
0
1
1
X
0
0
NC
1
1
__n_
0
1
0
1
1
1
0
1
1
1
1
1
Toggle
when inactive. To clear, you take CLR low; to preset, you
take PR low. In either case, you return them to high when
ready to run.
As before, low J and low K produce an inactive state,
regardless of the what the clock is doing. If K goes high
by itself, the next clock pulse resets the flip-flop. If J goes
high by itself, the next clock pulse sets the flip-flop. When
J and K are both high, each clock pulse produces one
toggle.
EXAMPLE 7-2
Figure 7-16a shows a clock generator . What does it do
when HLT is high?
SOLUTION
To begin with, the 555 is an IC that can generate a
rectangular output when connected as shown in Fig. 7-16a.
The frequency of the output is
1.44
; (R a + 2 R b )C
The duty cycle (ratio of high state to period) is
Q - + R B
R a + 2 R b
With the values shown in Fig. 7-16a the frequency of
the output is
/ =
_L44_
(36 kfl + 36 kfl)(0.01 fxF)
= 2 kHz
and the duty cycle is
36 kfl + 18 kfl
36 kfl + 36 kfl
0.75
which is equivalent to 75 percent.
nnnnnn
u
500 /us
p— 375 jus
(b)
Fig. 7-16 Clock generator: (a) circuit; ( b ) 555 output; (c) JK flip-
flop output.
_n
j
“1 | |
-J
— 1 ms
— 0.5 ms
(c)
Figure 7-166 illustrates how the output (pin 3) of the 555
looks. Note how the signal is high for 75 percent of the
cycle. This unsymmetrical output drives the clock input of
a JK master-slave flip-flop.
The JK master-slave flip-flop toggles once per input
cycle; therefore, its output has a frequency of 1 kHz and a
duty cycle of 50 percent. One of the reasons for using the
flip-flop is to get the symmetrical output shown in Fig.
7-16c.
Another reason for using the flip-flop is to control the
starting phase of the clock. A computer run starts with
CLR going momentarily low, then back to high. This resets
the flip-flop, forcing CLK to go low. Therefore, the starting
phase of the CLK signal is always low. You will see the
clock generator of Fig. 7-16a again in Chap. 10; remember
that the CLK signal has a frequency of 1 kHz, a duty cycle
of 50 percent, and starting phase of low.
GLOSSARY
contact bounce The making and breaking of contacts for
a few milliseconds after a switch closes.
edge triggering Changing the output state of a flip-flop
on the rising or falling edge of a clock pulse.
flip-flop A two-state circuit that can remain in either state
indefinitely. Also called a bistable multivibrator. An external
trigger can change the output state.
hold time The minimum amount of time the input signals
must be held constant after the clock edge has struck. After
a clock edge strikes a flip-flop, the internal transistors need
time to change from one state to another. The input control
signals (D, or J and K) must be held constant while these
internal transistors are switching over.
latch The simplest type of flip-flop, consisting of two
cross-coupled nand or nor latches.
level clocking A type of triggering in which the output
of a flip-flop responds to the level (high or low) of the
clock signal. With positive level clocking, for example, the
output can change at any time during the positive half cycle.
master-slave triggering A type of triggering using two
cascaded latches called the master and the slave. The master
is cocked during the positive half cycle of the clock, and
the slave is triggered during the negative half cycle.
propagation delay time The time it takes for the output
of a gate or flip-flop to change after the inputs have changed.
race condition An undesirable condition which may exist
in a system when two or more inputs change simultaneously.
If the final output depends on which input changes first, a
race condition exists.
setup time The minimum amount of time the inputs to a
flip-flop must be present before the clock edge arrives.
toggle Change of the output to the opposite state in a JK
flip-flop.
Chapter 7 Flip-Flops 103
SELF-TESTING REVIEW
Read each of the following and provide the missing words.
Answers appear at the beginning of the next question.
1. A flip-flop is a_element that stores a
binary digit as a low or high voltage. With an RS
latch a high S and a low R sets the output to
_; a low S and a high R _the
output to low.
2. ( memory, high, reset) With a nand latch a low R
and a low S produce a___condition. This is
why R and S are kept high when inactive. One use
for latches is switch debouncers; they eliminate the
effects of_bounce.
3. (race, contact) Computers use thousands of flip-
flops. To coordinate the overall action, a common
signal called the_is sent to each flip-flop.
With positive clocking the clock signal must be
-for the flip-flop to respond. Positive and
negative clocking are also called level clocking be¬
cause the flip-flop responds to the_of the
clock, either high or low.
4. (clock, high, level) In a D latch, data bit D drives the
S input of a latch, and the complement D drives the
R input; therefore, a high D _the latch
and a low D resets it. Since R and S are always in
opposite states in a D latch, the_condi¬
tion is impossible.
5. (sets, race) With a positive-edge-triggered D flip-
flop, the data bit is sampled and stored on the
_edge of the clock pulse. Preset and clear
inputs are often called_set and_
reset. These inputs override the other inputs; they
have first priority. When preset goes low, the Q
output goes_and stays there no matter
what the D and CLK inputs are doing.
6. (rising, direct, direct, high) In a flip-flop, propaga¬
tion delay time is the amount of time it takes for the
_to change after the clock edge has
struck. Setup time is the amount of time an input
signal must be present_the clock edge
strikes. Hold time is the amount of time an input
signal must be present_the clock edge
strikes.
7. (output, before, after) In a positive-edge-triggered JK
flip-flop, a low J and a low K produce the
_state. A high J and a high K mean that
the output will_on the rising edge of the
clock.
8. ( inactive, toggle) With a JK master-slave flip-flop the
master is cocked when the clock is_, and
the slave is triggered when the clock is_
This type of flip-flop is usually level-clocked instead
of edge-triggered. For this reason, J and K are nor¬
mally kept_while the clock is high.
9. (high, low, constant) Since capacitors are too diffi¬
cult to fabricate on an IC chip, manufacturers rely on
various direct-coupled designs for D flip-flops and JK
flip-flops.
PROBLEMS
7-1. The waveforms of Fig. 7-17 drive a clocked RS
latch (Fig. 7 -5a). If Q is low before time A,
a. At what point does Q become a 1?
b. When does Q reset to 0?
CLK
s
R —
Fig. 7-17
7-2. A D flip-flop has these specifications:
^setup i 0 US
Wd = 3 ns
t p = 30 ns
a. How far ahead of the rising clock edge must the
data bit be applied to the D input to ensure
correct storage?
b. After the rising clock edge, how long must you
wait before letting the data bit change?
c. How long after the rising clock edge will Q
change?
104 Digital Computer Electronics
s
°3
°3
<
°2
°2
<
Q ^
<
-LOAD
Q 0
D 0
<
Fig. 7-18
CLK
+5 V
/ n
J U
CLK -
-C
K Q
Fig. 7-19
+5 V
Fig. 7-20
7-3. In Fig. 7-18, the data word to be stored is
S = 1001
a. If LOAD is low, what does Q equal after the
positive clock edge?
b. If LOAD is high, what does Q equal after the
positive clock edge.
7-4. The clock of Fig. 7-19 has a frequency of 1 MHz,
and the flip-flop has a propagation delay time of 25
ns.
a. What is the period of the clock?
b. The frequency of the Q output? Its period?
c. How long after the negative clock edge does the
Q output change?
7-5. The clock has a frequency of 6 MHz in Fig. 7-19.
What is the frequency of the Q output ? This circuit
is sometimes called a divide-by-2 circuit. Explain
why.
7-6. In Fig. 7-20, CLR is taken low temporarily, then
high. Draw the timing diagram. If the clock has a
frequency of 1 MHz, what is the frequency of the
Q output? Is this a divide-by-2 circuit?
7-7. Figure 7-21 shows a nand latch used as a switch
debouncer. With the switch in the stop position,
what do Q and Y equal? If the switch is thrown to
the start position, what do Q and Y equal?
7-8. The clock has a frequency of 1 MHz in Fig. 7-22.
With the switch in the off position, what is the
frequency of the Q output? If the switch is thrown
to the on position, what is the frequency of the Q
output?
Chapter 7 Flip-Flops 105
8
Registers and Counters
A register is a group of memory elements that work together
as a unit. The simplest registers do nothing more than store
a binary word; others modify the stored word by shifting
its bits left or right or by performing other operations to be
discussed in this chapter. A counter is a special kind of
register, designed to count the number of clock pulses
arriving at its input. This chapter discusses some basic
registers and counters used in microcomputers.
8-1 BUFFER REGISTERS
A buffer register is the simplest kind of register; all it does
is store a digital word.
Basic Idea
Figure 8-1 shows a buffer register built with positive-edge-
triggered D flip-flops. The X bits set up the flip-flops for
loading. Therefore, when the first positive clock edge
arrives, the stored word becomes Q3Q2Q1Q0 = X^XjXq.
In chunked notation,
Q = X
The circuit is too primitive to be of any use. What it
needs is some control over the X bits, some way of holding
them off until we’re ready to store them.
Controlled
Figure 8-2 is more like it. This is a controlled buffer register
with an active-high CLR. Therefore, when CLR goes high,
all flip-flops reset and the stored word becomes
Q = 0000
When CLR returns low, the register is ready for action.
LOAD is a control input; it determines what the circuit
does. When LOAD is low, the X bits cannot reach the flip-
flops. At the same time, the inverted signal LOAD is high;
this forces each flip-flop output to feed back to its data
input. When each rising clock edge arrives, data is circulated
or retained. In other words, the register contents are
unchanged when LOAD is low.
When LOAD goes high, the X bits are transmitted to the
data inputs. After a short setup time, the flip-flops are ready
for loading. With the arrival of the positive clock edge, the
X bits are loaded and the stored word becomes
Q3Q2Q1Q0 = X 3 X 2 X j X 0
If LOAD returns to low, the foregoing word is stored
indefinitely; this means that the X bits can change without
affecting the stored word.
EXAMPLE 8 1
Chapter 10 discusses the SAP (simple-as-possible) com¬
puter. This educational computer has three generations,
SAP-1, SAP-2, and SAP-3. Figure 8-3 shows the output
register of the SAP-1 computer. The 74LS173 chips are
controlled buffer registers, similar to Fig. 8-2. What does
the circuit do?
SOLUTION
To begin with, it is an 8 -bit buffer register built with TTL
chips. Each chip handles 4 bits of input word X. The upper
nibble X 7 X 6 X 5 X 4 goes to pins 14, 13, 12, and 11 of C22;
the lower nibble X 3 X 2 X 1 X 0 goes to pins 14, 13, 12 , and
1 1 of the C23.
Output word Q drives an 8 -bit LED display. The upper
nibble Q 7 Q 6 Q 5 Q 4 comes out of pins 3, 4, 5, and 6 of C22;
the lower nibble Q 3 Q 2 QiQo comes out of pins 3, 4, 5, and
6 of C23. The typical high-state output of a 74LS173 is
3.5 V, and the typical LED drop is 1.5 V. Since each
current-limiting resistance is 1 kfl, the high-state current
is approximately 2 mA for each output pin.
106 Digital Computer Electronics
*2 X 1 *0
_I I_I 1_I I_
Fig. 8-1 Buffer register.
X-f x 6 x 5 x 4 x 3 X 2 X, x 0
Note: All resistors are 1 kf2.
Fig. 8-3 SAP-1 output register.
The 74LS173 requires a 5-V supply for pin 16 and a
ground return on pin 8. The SAP-1 output register never
needs clearing; this is why the CLR input (pin 15) is made
inactive by tying it to ground. In a 74LS173, pins 9 and
10 are separate LOAD controls. Because SAP-1 needs only
a single LOAD control, pins 9 and 10 are tied together.
The bubbles on pins 9 and 10 indicate an active low state;
this means that LOAD must be low for the positive clock
edge to store the input word. See Appendix 4 for a more
detailed description of the 74LS173.
The action of the circuit is straightforward. While LOAD
is high, the register contents are unchanged even though
the clock is running. To change the stored word, LOAD
must go low. Then the next rising clock edge loads the X
bits into the register. As soon as this happens, the LED
display shows the new contents.
Chapter 8 Registers and Counters 107
8-2 SHIFT REGISTERS
A shift register moves the stored bits left or right. This bit
shifting is essential for certain arithmetic and logic opera¬
tions used in microcomputers.
Shift Left
Figure 8-4 is a shift-left register. As shown, D m sets up the
right flip-flop, Q 0 sets up the second flip-flop, Q x the third,
and so on. When the next positive clock edge strikes,
therefore, the stored bits move one position to the left.
As an example, here’s what happens with D in = 1 and
Q - 0000
All data inputs except the one on the right are Os. The
arrival of the first rising clock edge sets the right flip-flop,
and the stored word becomes
Q = 0001
This new word means D x now equals 1, as well as D 0 .
When the next positive clock edge hits, the Q x flip-flop sets
and the register contents become
Q = 0011
The third positive clock edge results in
Q - 0111
and the fourth rising clock edge gives
q = mi
Hereafter, the stored word is unchanged as long as
An = 1 .
Suppose D m is now changed to 0. Then, successive clock
pulses produce these register contents:
Q = 1110
Q = 1100
Q = 1000
Q = 0000
As long as D m = 0, subsequent clock pulses have no
further effect.
The timing diagram of Fig. 8-5 summarizes the foregoing
discussion.
Shift Right
Figure 8-6 is a shift-right register. As shown, each Q output
sets up the D input of the preceding flip-flop. When the
108 Digital Computer Electronics
rising clock edge arrives, the stored bits move one position
to the right.
Here’s an example with D in = 1 and
Q = 0000
All data inputs except the one on the left are 0s. The first
positive clock edge sets the left flip-flop and the stored
word becomes
Q = 1000
With the appearance of this word, D 3 and D 2 are Is. The
second rising clock edge gives
Q = 1100
The third clock pulse gives
Q = 1110
and the fourth clock pulse gives
q = mi
8-3 CONTROLLED SHIFT
REGISTERS
A controlled shift register has control inputs that determine
what it does on the next clock pulse.
SHL Control
Figure 8-7 shows how the shift-left operation can be
controlled. SHL is the control signal. When SHL is low,
the inverted signal SHL is high. This forces each flip-flop
output to feed back to its data input. Therefore, the data is
retained in each flip-flop as the clock pulses arrive. In this
way, a digital word can be stored indefinitely.
When SHL goes high, D m sets up the right flip-flop, Q 0
sets up the second flip-flop, Q x the third flip-flop, and so
on. In this mode, the circuit acts like a shift-left register.
Each positive clock edge shifts the stored bits one position
to the left.
Serial Loading
Serial loading means storing a word in the shift register by
entering 1 bit per clock pulse. To store a 4-bit word, we
need four clock pulses. For instance, here’s how to serially
store the word
X = 1010
With SHL high in Fig. 8-7, make D in = 1 for the first
clock pulse, D in = 0 for the second clock pulse, D in = 1
for the third clock pulse, and D in = 0 for the fourth clock
pulse. If the register is clear before the first clock pulse,
the successive register contents look like this:
operation can be included. As an example, the 74198 is a
TTL 8-bit bidirectional shift register. It can broadside load,
shift left, or shift right.
Q = 0001
Q = 0010
Q = 0101
Q = 1010
(.D in = 1: first clock pulse)
(D in = 0: second clock pulse)
(D in = 1: third clock pulse)
(D m = 0: fourth clock pulse)
In this way, data is entered serially into the right end of
the register and shifted left until all 4 bits have been stored.
After the last bit is entered, SHL is taken low to freeze the
register contents.
Parallel Loading
Figure 8-8 is another step in the evolution of shift registers.
The circuit can load X bits directly into the flip-flops, the
same as a buffer register. This kind of entry is called
parallel or broadside loading; it takes only one clock pulse
to store a digital word.
If LOAD and SHL are low, the output of the nor gate
is high and flip-flop outputs return to their data inputs. This
forces the data to be retained in each flip-flop as the positive
clock edges arrive. In other words, the register is inactive
when LOAD and SHL are low, and the contents are stored
indefinitely.
When LOAD is low and SHL is high, the circuit acts like
a shift-left register, as previously described. On the other
hand, when LOAD is high and SHL is low, the circuit acts
like a buffer register because the X bits set up the flip-flops
for broadside loading. (Having LOAD and SHL simulta¬
neously high is forbidden because it’s impossible to do
both operations on a single clock edge.)
By adding more flip-flops we can build a controlled shift
register of any length. And with more gates, the shift-right
8-4 RIPPLE COUNTERS
A counter is a register capable of counting the number of
clock pulses that have arrived at its clock input. In its
simplest form it is the electronic equivalent of a binary
odometer.
The Circuit
Figure 8-9 a shows a counter built with JK flip-flops. Since
the J and K inputs are returned to a high voltage, each flip-
flop will toggle when its clock input receives a negative
edge.
Here’s how the counter works. Visualize the Q outputs
as a binary word
Q = Q3Q2Q1Q0
03 is the most significant bit (MSB), and 0 O is the least
significant bit (LSB). When CLR goes low; all flip-flops
reset. This results in a digital word of
Q = 0000
When CLR returns to high, the counter is ready to go.
Since the LSB flip-flop receives each clock pulse, Q 0 toggles
once per negative clock edge, as shown in the timing
diagram of Fig. 8-9fr. The remaining flip-flops toggle less
often because they receive their negative edges from the
preceding flip-flops.
For instance, when Q 0 goes from 1 back to 0, the Q x
flip-flop receives a negative edge and toggles. Likewise,
x 3 x 2 x, x 0
Fig. 8-8 Shift register with broadside load.
110 Digital Computer Electronics
High
Fig. 8-9 (a) Ripple counter; ( b ) timing diagram.
(b)
when Q x changes from 1 back to 0, the Q 2 flip-flop gets a
negative edge and toggles. And when Q 2 goes from 1 to
0, the Q 3 flip-flop toggles. In other words, whenever a flip-
flop resets to 0, the next higher flip-flop toggles (see Fig.
8 -%).
What does this remind you of? Reset and carry! Each
flip-flop acts like a wheel in a binary odometer; whenever
it resets to 0, it sends a carry to the next higher flip-flop.
Therefore, the counter of Fig. 8-9 a is the electronic
equivalent of a binary odometer.
Counting
If CLR goes low then high, the register contents of Fig.
8-9 a become
Q = 0000
When the first clock pulse hits the LSB flip-flop, Q 0 becomes
a 1. So the first output word is
Q = 0001
When the second clock pulse arrives, Q 0 resets and carries;
therefore, the next output word is
Q - 0010
The third clock pulse advances Q 0 to 1; this gives
Q = 0011
The fourth clock pulse forces the Q 0 flip-flop to reset and
carry. In turn, the Q x flip-flop resets and carries. The
resulting output word is
Q = 0100
The fifth clock pulse gives
Q = 0101
The sixth gives
Q = 0110
and the seventh gives
Q = 0111
On the eighth clock pulse, Q 0 resets and carries, Q x
resets and carries, Q 2 resets and carries, and Q 3 advances
to 1. So the output word becomes
Q = 1000
The ninth clock pulse gives
Q = 1001
The tenth gives
O = 1010
and so on.
Chapter 8 Registers and Counters 111
TABLE 8-1. RIPPLE
COUNTER
Count Q3Q2Q1Q0
0
0
0
0
0
1
0
0
0
1
2
0
0
1
0
3
0
0
1
1
4
0
1
0
0
5
0
1
0
1
6
0
1
1
0
7
0
1
1
1
8
1
0
0
0
9
1
0
0
1
10
1
0
1
0
11
1
0
1
1
12
1
1
0
0
13
1
1
0
1
14
1
1
1
0
15
1
1
1
1
The last word is
Q = Till
corresponding to the fifteenth clock pulse. The next clock
pulse resets all flip-flops. Therefore, the counter resets to
Q = 0000
and the cycle repeats.
Table 8-1 summarizes the operation of the counter. Count
represents the number of clock pulses that have arrived. As
you see, the counter output is the binary equivalent of the
decimal count.
Frequency Division
Each flip-flop in Fig. 8-9 a divides the clock frequency by
a factor of 2. This is why a flip-flop is sometimes called a
divide-by-2 circuit. Since each flip-flop divides the clock
frequency by 2, n flip-flops divide the clock frequency by
2 \
The timing diagram of Fig. 8-9 b illustrates the divide-
by-2 action. Q 0 is one-half the clock frequency, {9, is one-
fourth the clock frequency, Q 2 is one-eighth the clock
frequency, and Q 3 is one-sixteenth of the clock frequency.
In other words,
1 flip-flop divides by 2
2 flip-flops divide by 4
3 flip-flops divide by 8
4 flip-flops divide by 16
and
n flip-flops divide by 2"
Ripple Counter
The counter of Fig. 8-9 a is known as a ripple counter
because the carry moves through the flip-flops like a ripple
on water. In other words, the Q 0 flip-flop must toggle before
the Q x flip-flop, which in turn must toggle before the Q 2
flip-flop, which in turn must toggle before the Q 3 flip-flop.
The worst case occurs when the stored word changes from
0111 to 1000, or from 1111 to 0000. In either case, the
carry has to move all the way to the MSB flip-flop. Given
a t p of 10 ns per flip-flop, it takes 40 ns for the MSB to
change.
By adding more flip-flops to the left end of Fig. 8-9 a we
can build a ripple counter of any length. Eight flip-flops
give an 8-bit ripple counter, twelve flip-flops result in a
12-bit ripple counter, and so on.
Controlled Counter
A controlled counter counts clock pulses only when com¬
manded to do so. Figure 8-10 shows how it’s done. The
COUNT signal can be low or high. Since it conditions the
J and K inputs, COUNT controls the action of the counter,
forcing it to either do nothing or to count clock pulses.
When COUNT is low, the J and K inputs are low;
therefore, all flip-flops remain latched in spite of the clock
pulses driving the counter.
On the other hand, when COUNT is high, the J and K
inputs are high. In this case, the counter works as previously
described; each negative clock edge increments the stored
count by 1.
EXAMPLE 8-2
As mentioned earlier, the program and data are stored in
the memory before a computer run. The program is a list
of instructions telling the computer how to process the data.
COUNT
Fig. 8-10 Controlled ripple counter.
212 Digital Computer Electronics
Fig. 8-11 SAP-1 program counter.
Every microcomputer has a program counter to keep track
of the instruction being executed.
Figure 8-11 shows part of the program counter used in
SAP-1. What does it do?
SOLUTION
To begin with, let’s find out why the CLR and CLK signals
are shown as complements. Signals are often available in
complemented and uncomplemented form. The switch
debouncer of Fig. l-4a has two outputs, CLR and CLR. In
SAP-1 the CLR signal goes to any circuit that uses an active
high clear and the CLR signal to any circuit with an active
low clear. This is why CLR goes to the counter of Fig.
8-11; it has an active low clear. A similar idea applies to
the clock signal.
The 74107 is a dual JK master-slave flip-flop. The SAP-
1 program counter uses two 74107s. Although not shown,
pin 14 ties to the 5-V supply, and pin 7 is the chip ground.
Because master-slave flip-flops are used, a high CLK cocks
the master and a low CLK triggers the slave.
Before a comp uter r un, the operator pushes a clear button
that sends a low CLR to the program counter. This resets
its count to
Q = 0000
When the operator releases the button, CLR goes high and
the computer run begins.
After the first instruction has been fetched from the
memory, COUNT goes high for one clock pulse and the
count becomes
Q = 0001
This count indicates that the first instruction has been
fetched from the memory. (Later you will see how the
computer executes the first instruction.)
After the first instruction has been executed, the computer
fetches the second instruction in the memory. Once again,
COUNT goes high for one clock pulse, producing a new
count of
Q = 0010
The program counter now indicates that the second instruc¬
tion has been fetched from the memory.
Each time a new instruction is fetched from the memory,
the program counter is incremented to produce the next
higher count. In this way, the computer can keep track of
which instruction it’s working on.
8-5 SYNCHRONOUS COUNTERS
When the carry has to propagate through a chain of n flip-
flops, the overall propagation delay time is nt p . For this
reason ripple counters are too slow for some applications.
To get around the ripple-delay problem, we can use a
synchronous counter.
The Circuit
Figure 8-12 shows one way to build a synchronous counter
with positive-edge-triggered flip-flops. This time, clock
pulses drive all flip-flops in parallel. Because of the
simultaneous clocking, the correct binary word appears
after one propagation delay time rather than four.
The least significant flip-flop has its J and K inputs tied
to a high voltage; therefore, it responds to each positive
clock edge. But the remaining flip-flops can respond to the
positive clock edge only under certain conditions. As shown
in Fig. 8-12, the g, flip-flop toggles on the positive clock
edge only when g 0 is a 1. The g 2 flip-flop toggles only
when Q x and g 0 are Is. And the Q 3 flip-flop toggles only
when Q 2 , Q u and g 0 are Is. In other words, a flip-flop
toggles on the next positive clock edge if all lower bits are
Is.
Chapter 8 Registers and Counters 113
High
-TLTLTL
CLR
Fig. 8-12 Synchronous counter.
Here’s the counting action. A low CLR resets the counter
to
Q = 0000
When the CLR line goes high, the counter is ready to go.
The first positive clock edge sets Q 0 to get
Q = 0001
Since Q 0 is now 1, the Q x flip-flop is conditioned to toggle
on the next positive clock edge.
When the second positive clock edge arrives, Q x and (2o
simultaneously toggle and the output word becomes
Q = 0010
The third positive clock edge advances the count by 1:
Q = 0011
Because Q x and Q 0 are now Is, the Q 2 , Q u and Q 0 flip-
flops are conditioned to toggle on the next positive clock
edge. When the fourth positive clock edge arrives, Q 2 , Q i,
and Q g toggle simultaneously, and after one propagation
delay time the output word becomes
Q = 0100
The successive Q words are 0101, 0110, 0111, and so
on up to 1111 (equivalent to decimal 15). The next positive
clock edge resets the counter, and the cycle repeats.
By adding more flip-flops and gates we can build
synchronous counters of any length. The advantage of a
synchronous counter is its speed; it takes only one propa¬
gation delay time for the correct binary count to appear
after the clock edge hits.
Controlled Counter
Figure 8-13 shows how to build a controlled synchronous
counter. A low COUNT disables all flip-flops. When
COUNT is high, the circuit becomes a synchronous counter;
each positive clock edge advances the count by 1.
8-6 RING COUNTERS
Instead of counting with binary numbers, a ring counter
uses words that have only a single high bit.
Circuit
Figure 8-14 is a ring counter built with D flip-flops. The
Q 0 output sets up the D x input, the Q x output sets up the
D 2 input, and so on. Therefore, a ring counter resembles a
COUNT
-TLTLTL
CLR
Fig. 8-13 Controlled synchronous counter.
114
Digital Computer Electronics
Fig. 8-14 Ring counter.
CLR
shift-left register because the bits are shifted left one position
per positive clock edge. But the circuit differs because the
final output is fed back to the D 0 input. This kind of action
is called rotate left; bits are shifted left and fed back to the
input.
When CLR goes low then back to high, the initial output
word is
Q = 0001
The first positive clock edge shifts the MSB into the LSB
position; the other bits shift left one position. Therefore,
the output word becomes
Q = 0010
The second positive clock edge causes another rotate left
and the output word changes to
Q = 0100
After the third positive clock edge, the output word is
Q = 1000
The fourth positive clock edge starts the cycle over because
the rotate left produces
Q = 0001
The stored 1 bit follows a circular path, moving left
through the flip-flops until the final flip-flop sends it back
to the first flip-flop. This is why the circuit is called a ring
counter.
More Bits
Add more flip-flops and you can build a ring counter of
any length. With six flip-flops we get a 6-bit ring counter.
Again, the CLR signal resets all flip-flops except the LSB
flip-flop. Therefore, the successive ring words are
Q
= 000001
(0)
Q
= 000010
(1)
Q
= 000100
(2)
Q
= 001000
(3)
Q
= 010000
(4)
Q
= 100000
(5)
Each of the foregoing words has only 1 high bit. The
initial word stands for decimal 0 and the final word for
decimal 5. If a ring counter has n flip-flops, therefore, the
final ring word represents decimal n — 1.
Applications
Ring counters cannot compete with ripple and synchronous
counters when it comes to ordinary counting, but they are
invaluable when it’s necessary to control a sequence of
operations. Because each ring word has only 1 high bit,
you can activate one of several devices.
For instance, suppose the six small boxes (A to F) of
Fig. 8-15 are digital circuits that can be turned on by a
high Q bit. When CLR goes low, Q 0 goes high and activates
device A. After CLR returns to high, successive clock
pulses turn on each device for a short time. In other words,
as the stored 1 bit shifts left, it turns on B to F in sequence,
and then the cycle starts over.
Many digital circuits participate during a computer run.
To fetch and execute instructions, a computer has to activate
Fig. 8-15 Controlling a sequence of operations
Chapter 8 Registers and Counters 11 5
C36
74107
C37
74107
C38
74107
CLK
CLR
h
T 4
Note: Pin 14 is connected to +5 V, and pin 7 is grounded.
Fig. 8-16 SAP-1 ring counter.
these circuits at precisely the right time and in the right
sequence. This is where ring counters shine; they produce
the ring words for timing different operations during a
computer run.
EXAMPLE 8-3
Figure 8-16 shows the ring counter used in the SAP-1
computer. T 6 to T { are called timing signals because they
control a sequence of digital operations. What does this
ring counter do?
SOLUTION
The 74107 is a dual JK master-slave flip-flop, previously
used in the SAP-1 program counter (Example 8-2). The
flip-flops are connected in a rotate-left mode. Since the
74107 does not have a preset input, the Q 0 flip-flop is
inverted so that its Q output drives the J input of the Q {
flip-flop. In this way, a low CLR produces the initial timing
word
T 6 T 5 T 4 T 3 T 2 T t = 000001
In chunked form
T = 000001
Because of the master-slave action, a complete clock
pulse is needed to produce the next ring word. After CLR
returns high, the successive clock pulses produce the timing
words
T = 000010
T = 000100
T = 001000
T = 010000
T = 100000
Then the cycle repeats.
EXAMPLE 8-4
The clock frequency in Fig. 8-16 is 1 kHz. CLR goes low
then high. Show the timing diagram.
SOLUTION
Figure 8-17 is the timing diagram. Since the clock has a
frequency of 1 kHz, it has a period of 1 ms. This is the
amount of time between successive negative clock edges.
Each negative clock edge produces the next ring word.
When its turn comes, each timing signal goes high for 1
ms.
Notice that the CLK signal of Fig. 8-17 is the input to
the r ing counter of Fig. 8-16, whereas the complement
CLK is the input to the program counter of Fig. 8-11. This
half-cycle difference is deliberate. The reason is given in
Chap. 10, which explains how the timing signals of Fig.
8-17 control circuits that fetch and execute each program
instruction.
8-7 OTHER COUNTERS
The modulus of a counter is the number of output states it
has. A 4-bit ripple counter has a modulus of 16 because it
has 16 distinct states numbered from 0000 to 1111. By
changing the design we can produce a counter with any
desired modulus.
Mod-10 Counter
Figure 8-18a shows a way to build a modulus-10 (or mod-
10) counter. The circuit counts from 0000 to 1001, as
before. However, on the tenth clock pulse, the counter
116 Digital Computer Electronics
Fig. 8-17 SAP-1 clock and timing pulses.
generates its own clear signal and the count jumps back to
0000. In other words, the count sequence is
Q
= 0000
(0)
Q
- 0001
(1)
Q
= 0010
(2)
Q
= 0011
(3)
Q
= 0100
(4)
Q
= 0101
(5)
Q
= 0110
(6)
Q
= 0111
(7)
Q
= 1000
(8)
Q
= 1001
(9)
Q
= 0000
(0)
As you see, the circuit skips states 10 to 15 (1010 through
1111). The counting sequence is summarized by the state
diagram of Fig. 8-18fr.
Why does the counter skip the states from 10 to 15?
Beca use of the and gate, the counter can be reset by a low
CLR or a low Y. Initially, CLR goes low to produce
Q - 0000
When CLR returns to high, the counter is ready for action.
The output of the nand gate is
y = oiOi
This output is high for the first nine states (0000 to 1001).
Nothing unusual happens when the circuit is counting from
0 to 9. On the tenth clock pulse, however, the Q word
becomes
Q = 1010
Chapter 8 Registers and Counters 11 7
which means that Q 3 and Q x are high. Almost immediately,
Y goes low, forcing the counter to reset to
Q = 0000
Y then goes high, and the counter is ready to start over.
Since it takes 10 clock pulses to reset the counter, the
output frequency of the Q 3 flip-flop is one-tenth of the clock
frequency. This is why a mod-10 counter is also known as
a divide-by-10 circuit.
A mod-10 counter like Fig. 8-18 a is often called a decade
counter. Because it counts from 0 to 9, it is a natural choice
in BCD applications like frequency counters, digital volt¬
meters, and electronic wristwatches.
To get any other modulus, we can use the same basic
idea. For instance, to get a mod-12 counter, we can drive
the nand gate of Fig. 8-18 a with Q 3 and Q 2 . Then the
circuit counts from 0 to 11 (0000 to 1011). On the next
clock pulse, Q 3 and Q 2 are high, which clears the counter.
(What is the modulus if Q 3 and go drive the nand gate?)
Down Counter
All the counters discussed so far have counted upward,
toward higher numbers. Figure 8-19 shows a down counter;
it counts from 1111 to 0000. Each flip-flop toggles when
its clock input goes from 1 to 0. This is equivalent to an
uncomplemented output going from 0 to 1. For instance,
the Q\ flip-flop toggles when <2o goes from 1 to 0; this is
equivalent to Q 0 going from 0 to 1.
A preset signal generated elsewhere is available in either
uncomplemented or complemented form; PRE goes to all
circuits with an active-high preset; PRE goes to all cir cuits
with an active-low preset. Initially, the preset signal PRE
goes low in Fig. 8-19, producing an output word of
Q = 1111 (15)
When PRE goes high, the action starts. Notice that Q 0
toggles once per clock pulse. In the following discussion,
a positive toggle means a change from 0 to 1, a negative
toggle means a change from 1 to 0.
The first clock pulse produces a negative toggle in Q 0 ;
nothing else happens:
Q = 1110 (14)
The second clock pulse produces a positive toggle in Q 0 ,
which produces a negative toggle in Q x :
Q = 1101 (13)
On the third clock pulse, Q 0 toggles negatively, and
Q = 1100 (12)
On the fourth clock pulse, Q 0 toggles positively, Q } toggles
positively, and Q 2 toggles negatively:
Q - 1011 (11)
You should have the idea by now. The circuit is counting
down, from 15 to 0. When it reaches 0,
Q = 0000
On the next clock pulse, all flip-flops toggle positively to
and the cycle repeats.
Up-Down Counter
Figure 8-20 shows how to build an up-down counter. The
flip-flop outputs are connected to steering networks. An
UP control signal produces either down counting or up
counting. If the UP signal is low, Q 2 , Q u and Q 0 are
transmitted to the clock inputs; this results in a down
counter. On the other hand, when UP is high, Q 2 , Q u and
Q 0 drive the clock inputs and the circuit becomes an up
counter.
Presettable Counter
In a presettable counter , the count starts at a number greater
than zero. Figure 8-2la shows a presettable counter; the
count begins with P 3 P 2 P]Po, a number between 0000 and
1111.
To start the analysis, look at the LOAD control line.
When it is low, all nand gates have high outputs; therefore,
118 Digital Computer Electronics
Fig. 8-20 Up-down counter.
Fig. 8-21 Presettable counter.
the preset and clear inputs of all flip-flops are inactive. In counter to P 3 P 2 P,P 0 . As an example, suppose the preset
this case, the circuit counts upward, as previously described. input is
The data inputs P 3 to P 0 have no effect because the nand P 3 P 2 P,P 0 = 0110
gates are disabled.
When the LOAD line is high, the data inputs and their Because of the two left nand gates, the low P 3 produces
complements pass through the nand gates and preset the a high preset and a low clear for the Q 3 flip-flop; this clears
Chapter 8 Registers and Counters 119
Q 3 to a 0. By a similar argument, the high P 2 sets Q 2 , the
high P x sets Q u and the low P 0 clears Q 0 . Therefore, the
counter is preset to
Q = 0110
When LOAD returns to low, the circuit reverts to a
counter. Successive clock pulses produce
Q = 0111
Q = 1000
Q = 1001
up to a maximum count of
Q = 1111
The next clock pulse resets the counter to
Q = 0000
In summary,
1. When LOAD is low, the circuit counts.
2. When LOAD is high, the counter presets to P 3 P 2 PiP 0 .
Programmable Modulus
The most important use of a presettable counter is pro¬
gramming a modulus. Here’s the idea. Let’s add the nor
gate of Fig. 8-216 to the presettable counter of Fig. 8-21 a.
Then the Q outputs drive the nor gate, and the nor gate
controls the LOAD line of the presettable counter. Because
a nor gate recognizes a word with all 0s and disregards all
others, LOAD is high for Q = 0000 and low for all other
words. This means that the circuit presets when Q = 0000
and counts when Q is 0001 to 1111.
If the preset input is 0110, successive clock pulses
produce 0111, 1000, 1001, . . . , reaching a maximum
value of
Q = 1111
The next clock pulse resets the count to
Q = 0000
Almost immediately, however, the NOR-gate outputs goes
high, and the data inputs preset the counter to
Q = 0110
In other words, the counter effectively skips states 0 to 5,
illustrated by the state diagram of Fig. 8-2 lc.
Figure 8-21c shows 10 distinct states; by presetting 0110,
we have programmed the counter to become a mod-10
counter. If we change the preset input, we get a different
modulus. In general,
M = N - P (8-1)
where M = modulus of preset counter
N — natural modulus
P = preset count
The natural modulus equals 2" where n is the number of
flip-flops in the counter. So four flip-flops give a natural
modulus of 16, eight give a natural modulus of 256, and
so on.
As an example, if you preset 82 into a preset counter
with eight flip-flops, the modulus is
M = 256 - 82 = 174
In other words, this preset counter is equivalent to a divide-
by-174 circuit.
TTL Counters
Table 8-2 lists some TTL counters. The 7490 is an industry
standard, a widely used decade counter. This ripple counter
has two sections, a divide-by-2 and a divide-by-5. This
allows you to divide by 2, to divide by 5, or to cascade
both sections to divide by 10.
The 7492 is a mod-12 ripple counter, organized in two
sections by divide-by-2 and divide-by-6. This allows you
to divide by 2, divide by 6, or cascade to divide by 12.
The 7493 is a mod-16 ripple counter, with two sections of
divide-by-2 and divide-by-8.
The 74160 and 74161 are presettable synchronous counters,
the first being a decade counter and the second a divide-
by-16 counter. Finally, the 74190 and 74191 are up-down
presettable counters.
This is a sample of basic TTL counters; others are listed
in Appendix 3.
TABLE 8-2. TTL COUNTERS
Number
Type
7490
Decade
7492
Divide-by-12
7493
Divide-by-16
74160
Presettable decade
74161
Presettable divide-by-16
74190
Up-down presettable decade
74191
Up-down presettable divide-by-16
120 Digital Computer Electronics
8-8 THREE-STATE REGISTERS
TABLE 8-3. NORMALLY
OPEN
The three-state switch, a development of the early 1970s,
has greatly simplified computer wiring and design because
it’s ideal for bus-organized computers (the common type
nowadays).
+ 5 v
ENABLE
(a)
D
in
D
out
(bj
D
in
D
out
fc)
Fig. 8-22 (a) Three-state switch; ( b ) floating or high-impedance
state; (c) output equals input.
Three-State Switch
Figure 8-22 a is an example of a three-state switch. The
ENABLE input can be low or high. When it’s low, transistor
A cuts off and transistor B saturates. This pulls the base of
transistor C down to ground, opening its base-emitter diode.
As a result, D out floats. This floating state is equivalent to
an open switch (Fig. 8-22 b).
On the other hand, when ENABLE is high, transistor A
saturates and transistor B cuts off. Now, the transistor C
acts like an emitter follower, and the overall circuit is
equivalent to a closed switch (Fig. 8-22c). In this case,
flout = D in
This means that D out is low or high, the same as D m .
Table 8-3 summarizes the action. When ENABLE is low,
D m is a don’t care and D oul is open or floating. When
ENABLE is high, the circuit acts like a noninverting buffer
because D out equals D m .
ENABLE
D m
flout
0
X
Open
1
0
0
1
1
1
Commercial three-state switches are much more compli¬
cated than Fig. 8-22 a (a totem-pole output and other
enhancements are added). But simple as it is, Fig. 8-22 a
captures the key idea of a three-state switch; the output can
be in any of three states: low, high, or floating (sometimes
called the high-impedance state because the Thevenin
impedance is high).
Three-state switches are also known as Tri-state switches.
(Tri-state is a trademark name used by National Semicon¬
ductor, the originator of three-state TTL logic.)
(b)
Fig. 8-23 (a) Normally open switch; (b) normally closed switch.
Normally Open Switch
Figure 8-23 a is the symbol for a three-state noninverting
buffer. When you see this symbol, remember the action: a
low ENABLE means that the output is floating; a high
ENABLE means that the output is 0 or 1, the same as the
input. Think of this switch as normally open; to close it,
you have to apply a high ENABLE.
In the 7400 series, the 74126 is a quad three-state
normally open switch. This means four switches like Fig.
8-23a in one package. The SAP-1 computer uses five
74126s.
Normally Closed Switch
Figure 8-23 b is different. This is the symbol for a normally
closed switch because the control input DISABLE is active
low. In other words, the switch is closed when DISABLE
is low, and open when DISABLE is high. Table 8-4
summarizes the operation.
The 74125 is a quad three-state normally closed switch
(four switches like Fig. 8-23 b in one package).
Chapter 8 Registers and Counters 121
TABLE 8-4. NORMALLY
CLOSED
DISABLE
D m
D out
0
0
0
0
1
1
1
X
Open
Three-State Buffer Register
The main application of three-state switches is to convert
the two-state output of a register to a three-state output.
For instance, Fig. 8-24 shows a three-state buffer register,
so called because of the three-state switches on the output
lines. When ENABLE is low, the Y outputs float. But when
ENABLE is high, the Y outputs equal the Q outputs;
therefore,
Y = Q
You already know how the rest of the circuit works; it’s
the controlled buffer register discussed earlier. When LOAD
is low, the contents of the register are unchanged. When
LOAD is high, the next positive clock edge loads X 3 X 2 X 1 X 0
into the register.
8-9 BUS-ORGANIZED COMPUTERS
A bus is a group of wires that transmit a binary word. In
Fig. 8-25, vertical wires W 3 , W 2 , W l9 and W 0 are a bus;
these wires are a common transmission path between the
three-state registers. The input data bits for register A come
from the W bus; at the same time, the three-state output of
register A connects back to the W bus. Similarly, the other
registers have their inputs and outputs connected to the W
bus.
In Fig. 8-25 all control signals are in uncomplemented
form; this means that the registers have active high inputs.
In other words, a load input (L A to L D ) must be high to set
up for loading, and an enable signal (E A to E D ) must be
high to connect an output to the bus.
Register Transfers
The beauty of bus organization is the ease of transferring
a word from one register to another. To begin with, the
same clock signal drives all registers, but nothing happens
until you apply high control inputs. In other words, as long
as all LOAD and ENABLE inputs are low, the registers are
isolated from the bus.
To transfer a word from one register to another, make
the appropriate control inputs high. For instance, here’s
how to transfer the contents of register A to the register D.
Make E A and L D high; then the contents of register A appear
on the bus and register D is set up for loading. When the
next positive clock edge arrives, word A is stored in register
D.
Here is another example. Suppose the following words
are stored in the registers:
A = 0011
B = 0110
C - 1001
D = 1100
Fig. 8-24 Three-state buffer register.
122 Digital Computer Electronics
W bus
Fig. 8-25 Registers connected to bus.
To transfer word C into register B, make E c and L B high.
The high E c closes the three-state switches of register C,
placing word C on the bus. The high L B sets up register B
for loading. When the next positive clock edge arrives,
word C is stored in register B, and the new words are
A = 0011
B = 1001
C = 1001
D = 1100
The whole point of bus organization (connecting the
registers to a common word path) is to simplify the wiring
and operation of computers. As you will see in Chap. 10,
SAP-1 is a bus-organized computer of incredible simplicity
made possible by the three-state switch.
Simplified Drawings
Figure 8-25 shows a 4-bit bus. The same idea applies to
any number of bits. For example, a 16-bit bus has 16 wires,
each carrying 1 bit of a word. By connecting the inputs
and outputs of 16-bit registers to this bus, we can transfer
16-bit words from one register to another.
Drawings get very messy unless we simplify the appear¬
ance of the bus. Figure 8-26 shows an abbreviated form of
Fig. 8-25. The solid arrows represents words going into
and out of registers. The solid bar represents the W bus.
EXAMPLE 8-5
Figure 8-27 shows part of the SAP-1 computer. Describe
the circuitry.
Chapter 8 Registers and Counters 123
13
SOLUTION
SOLUTION
As discussed in Sec. 6 - 8 , the 7483 is a 4-bit adder. The
two 7483s of Fig. 8-27 are the ALU of the SAP-1 computer.
The inputs to this ALU are the words
A = A 7 A 5 A 5 A 4 A 3 A 2 A ] Aq
B = ByBgBjB^jB.BiBo
A pair of 7486s allow us to complement the B input for
subtraction.
The sum (Su low) or difference (Sy high) appears at the
output (pins 15, 2 , 6 , 9 of C16 and pins 15, 2, 6 , 9 of
Cl7). Three-state switches (Cl 8 and Cl9) connect the ALU
output to the W bus when E v is high. If E v is low, the
74126s are open and the ALU output is isolated from the
bus.
EXAMPLE 8-6
Figure 8-28 shows the instruction register (C 8 and C9) of
the SAP-1 computer. What does this 8 -bit register do?
Example 8-1 introduced the 74LS173. As you may recall,
pins 9 and 10 are tied together and control the LOAD
function. Because of the bubble, a low L, is needed to set
up the registers for loading. When L, is low, the next
positive clock edge loads the data on the bus into the
instruction register.
The output of the instruction register is split; the upper
nibble I 7 I 6 I 5 I 4 goes to the instruction decoder , a circuit that
will be discussed in Chap. 10. The lower nibble out of the
instruction register goes back to the W bus.
The 74LS173 is a 4-bit three-state buffer register; it has
internal three-state switches controlled by pins 1 and 2 .
The bubbles on pins 1 and 2 indicate active-low inputs;
therefore, the output of C9 is connected to the bus when
E, is low and disconnected when E, is high.
Notice that pins 1 and 2 of C 8 are grounded; this means
that the upper nibble is always a two-state output. In other
words, the 74LS173 can be used as an ordinary two-state
register by grounding pins 1 and 2. (This was done in
Example 8 - 1 , where we used two 74LS173s for the output
register to drive an 8 -bit LED display.)
W bus
Fig. 8-28 SAP-1 instruction register.
_ GLOSSARY __
buffer register A register that temporarily stores a word modulus The number of stable states a counter has.
during data processing. parallel entry Loading all bits of a word in parallel during
bus A group of wires used as a common word path by one clock pulse. Also called broadside loading,
several registers. presettable counter A counter that allows you to preset a
Chapter 8 Registers and Counters 1 25
number from which the count begins. Sometimes called a
programmable counter.
register A group of memory elements that store a word.
ring counter A counter producing words with 1 high bit,
which shifts one position per clock pulse.
ripple counter A counter with cascaded flip-flops. This
means that the carry has to propagate in series through the
flip-flops.
serial entry Loading a word into a shift register 1 bit per
clock pulse
shift register A register that can shift the stored bits one
position to the left or right.
synchronous counter A counter in which the clock drives
each flip-flop to eliminate the ripple delay.
three-state switch A noninverting buffer that can be closed
or opened by a control signal. Also called a Tri-state switch.
SELF-TESTING REVIEW
Read each of the following and provide the missing words.
Answers appear at the beginning of the next question.
1. When the LOAD input of a buffer register is active,
the input word is stored on the next positive-
edge. If LOAD then becomes inactive, the input
word can change without effecting the-
word.
2. (clock, stored) A shift register moves the-
left or right. Serial loading means storing a word in a
shift register by entering-bit per clock
pulse. With parallel or broadside loading, it takes
only one_pulse to load the input word.
3. (bits, 1, clock) One flip-flop divides the clock fre¬
quency by a factor of-Two flip-flops
divide by 4, three flip-flops by 8, and four flip-flops
by_In general, n flip-flops divide by 2 n .
4. (2, 16) In a ripple counter, the carry has to propagate
through all the flip-flops to reach the MSB flip-flop.
The overall propagation delay time is-A
controlled counter counts-pulses only
when the COUNT signal is active. The clock signal
drives each flip-flop of a-counter.
5. (nt p , clock, synchronous) Instead of counting with
binary numbers, a ring counter uses words that have
a single high_A ring counter is ideal for
timing a sequence of digital operations.
6. (bit) The modulus of a counter is the number of
stable output_it has. A mod-10 counter
can divide the clock frequency by a factor of-
7. (states, 10) An up-down counter can count up or
down. A presettable counter starts the count from a
_number. This allows us to program the
_If the modulus is M, a presettable
counter is equivalent to a divide-by-M circuit.
8. (preset, modulus) A three-state switch has an output
that is either low, high, or-Two types
are available; normally open and normally closed.
The main use of three-state switches is to convert the
_output of a register to a three-state out¬
put.
9. (floating , two-state) A bus is a group of wires used
by three-state registers as a common word path. Bus-
organized computers, the common type nowadays,
have several registers connected to one or more
buses. Instructions and data travel along these buses
as they move from one register to another.
PROBLEMS
8-1. Figure 8-29 shows an output register. Before time
A the data word to be loaded is
X = 1000 1101
and the LED display is
Q = 0001 0111
a. What is the LED display at time D?
b. What is the LED display at time F?
8-2. The data sheet of a 74173 gives these values:
^setup = 17 ns (L 0 input)
tsetup = 10 ns (Data)
r hold = 2 ns (L 0 input)
4oid = 10 ns (Data)
a. In Fig. 8-29, how far ahead of point E must
the X bits be applied to ensure accurate loading?
b. Suppose the clock has a frequency of 1 MHz
126 Digital Computer Electronics
Fig. 8-29
Note: All resistors are 1 kH.
and the X bits are applied at the point D. Is the
setup time sufficient for the data inputs?
c. How long must you wait after point E before
removing the X bits or letting them change?
8-3. Each output pin of a 74173 can source up to 5.2
mA. In Fig. 8-29 suppose the high output voltage
is 3.5 V and the LED drop is 1.5 V. To get more
light out of the LEDs, we want to reduce the
current-limiting resistors. What is the minimum
allowable resistance?
Fig. 8-30
8-4. A 74199 is an 8-bit shift-left register with a single
control signal, as shown in Fig. 8-30. When
SHIFT I LOAD is low, the circuit loads the X word
on the next positive clock edge. When SHIFTI
LOAD is high, the register shifts the bits to the
left.
a. To clear the register, should CLR be low or
high? When you are ready to run, what should
CLR be?
b. Is the X word loaded on the positive or negative
edge of the clock?
c. IfX = 0100 1011, D in = 0, and SHIFT/LOAD
= 0, what does the Q output word equal after
two positive clock edges?
d. If X = 0100 1011, D in = 0, and SHIFTi
LOAD = 1, what does the Q output word
equal after two positive clock edges?
8-5. The clock frequency is 2 MHz. How long will it
take to serially load the shift register of Fig.
8-30?
8-6. In Fig. 8-30, Q = 0001 0110. If SHIFTlLOAD is
high and D m is high, what does Q equal after
three clock pulses?
8-7. Data from a satellite is received in serial form (1
bit after another). If this data is coming at a
5-MHz rate and if the clock frequency is 5 MHz,
how long will it take to serially load a word in a
32-bit shift register?
8-8. A ripple counter has 16 flip-flops, each with a
propagation delay time of 25 ns. If the count is
q = oin mi mi mi
how long after the next active clock edge before
Q = 1000 0000 0000 0000
8-9. What is the maximum decimal count for the
counter of the preceding problem?
8-10. When pins 1 and 12 of a 7490 are tied together as
shown in Fig. 8-31, the divide-by-2 and divide-
by-5 sections are cascaded to get a mod-10
counter. Pin 14 is the input and pin 11 is the
output of each 7490. As a result, each 7490 acts
like a divide-by-10 circuit and the overall circuit
divides by 1,000.
Chapter 8 Registers and Counters 1 27
+5 V
+5 V
+5 V
Fig. 8-31
A
B
C
If the clock has a frequency of 5 MHz, what is
the frequency of A? Of 5? Of Cl
8-11. The clock signal driving a 6-bit ring counter has a
frequency of 1 MHz. How long is each timing bit
high? How long does it take to cycle through all
the ring words?
It-
—
-[
—\
—
O
- =1
_r
_J 0
r
>--
. 1 _
_ )
^_ J 2
_
1 _
-1
_
_ )
T
9 -
.__
_ )
A T
i -
LJ— 4
I A T
<
i
>-
_
LJ 5
[ A_ T
1 >-
<
-L__
9
—
_
\ ) 6
1 ^ T
(>
<
►
<
t- 1 —
\ _ )
"LTLTL
rz
q 2 q 2 a, 0, o 0 a
Synchronous counter
0
-r
- CLR
Fig. 8-32
8-12. Figure 8-32 shows another way to produce ring
words. After the circuit is cleared,
Q = Q2Q1Q0 = 000
Since the and gates are a l-of-8 decoder,
the first timing word is
T = 0000 0001
What does T equal for each of the follow¬
ing:
a. Q = 001
b. Q = 010
c. Q = 101
d. Q = 111
8-13. If the clock frequency is 5 MHz in Fig. 8-32,
how long does it take to produce all the ring
words? How long is each timing bit high?
60 Hz
S M H
Fig. 8-33
8-14. In a digital clock, the 60-Hz line frequency is
divided down to lower frequencies, as shown in
Fig. 8-33. What are the frequency and period of
the S output? Of the M output? Of the H output?
8-15. You have an unlimited number of the following
ICs to work with: 7490, 7492, and 7493. Which
of these would you use to build the divide-by-60
circuits of Fig. 8-33?
8-16. A presettable counter has eight flip-flops. If the
preset number is 125, what is the modulus?
8-17. Given a presettable 8-bit counter, what number
would you preset to get a divide-by-120 circuit?
8-18. In Fig. 8-34, we want to transfer the contents of
register D to register C. Which are the ENABLE
and LOAD inputs you should make high?
8-19. Look at Fig. 8-35 and answer each of these ques¬
tions.
a. To add the inputs and put the answer on the
bus, what should S v and E v be?
b. To subtract the inputs and put the answer on
the bus, what should S v and E v be?
c. To isolate the ALU from the bus, what should
E v be?
128 Digital Computer Electronics
Memories
The memory of a computer is where the program and data
are stored before the calculations begin. During a computer
run, the control section may store partial answers in the
memory, similar to the way we use paper to record our
work. The memory is therefore one of the most active parts
of a computer, storing not only the program and data but
processed data as well.
The memory is equivalent to thousands of registers, each
storing a binary word. The latest generation of computers
relies on semiconductor memories because they are less
expensive and easier to work with than core memories. A
typical microcomputer has a semiconductor memory with
up to 655,360 memory locations, each capable of storing
l byte of information.
9-1 ROMS
A read-only memory (ROM) is the simplest kind of memory.
It is equivalent to a group of registers, each permanently
storing a word. By applying control signals, we can read
the word in any memory location. (“Read” means to make
the contents of the memory location appear at the output
terminals of the ROM.)
Diode ROM
Figure 9-1 shows one way to build a ROM. Each horizontal
row is a register or memory location. The R 0 register
Fig. 9-1 Simple diode ROM.
130
TABLE 9-1. DIODE ROM
Register
Address
Word
Ro
0
0111
R.
1
1000
r 2
2
1011
r 3
3
1100
r 4
4
0110
r 5
5
1001
r 6
6
0011
r 7
7
1110
contains three diodes, the R, register has one diode, and
so on. The output of the ROM is the word
D= D 3 D 2 D,D 0
In switch position 0, a high voltage turns on the diodes
in the R 0 register; all other diodes are off. This means that
a high output appears at D 2 , D,, and D 0 . Therefore, the
word stored at memory location 0 is
D = 0111
What happens if the switch is moved to position 1 ? The
diode in the R, register conducts, forcing D, to go high.
Because all other diodes are off, the output from the ROM
becomes
D = 1000
So the contents of memory location 1 are 1000.
As you move the switch to other positions, you will read
the contents of the other memory locations. Table 9-1
shows these contents, which you can check by analyzing
Fig. 9-1.
With discrete circuits we can change the contents of a
memory location by adding or removing diodes. With
integrated circuits, the manufacturer stores the words at the
time of fabrication. In either case, the words are permanently
stored once the diodes are wired in place.
Addresses
The address and contents of a memory location are two
different things. As shown in Table 9-1, the address of a
memory location is the same as the subscript of the register
storing the word. This is why register 0 has an address of
0 and contents of 0111; register 1 has an address of 1 and
contents of 1000; register 2 has an address of 2 and contents
of 1011; and so on.
The idea of addresses applies to ROMs of any size. For
example, a ROM with 256 memory locations has decimal
addresses running from 0 to 255. A ROM with 1,024
memory locations has decimal addresses from 0 to 1,023.
On-Chip Decoding
Rather than switch-select the memory location, as shown
in Fig. 9-1, IC manufacturers use on-chip decoding. Figure
9-2 gives you the idea. The three input pins (A 2 , A ls and
A 0 ) supply the binary address of the stored word. Then a
1 -of-8 decoder produces a high output to one of the registers.
For instance, if
ADDRESS = A 2 A,A 0 = 100
the l-of-8 decoder applies a high voltage to the R 4 register,
and the ROM output is
D = 0110
If you change the address word to
ADDRESS =110
you will read the contents of memory location 6, which is
D = 0011
The circuit of Fig. 9-2 is a 32-bit ROM organized as 8
words of 4 bits each. It has three address (input) lines and
four data (output) lines. This is a very small ROM compared
with commercially available ROMs.
Number of Address Lines
With on-chip decoding, n address lines can select 2" memory
locations. For instance, we need 3 address lines in Fig.9-2
to access 8 memory locations. Similarly, 4 address lines
can access 16 memory locations, 8 address lines can access
256 memory locations, and so on.
9-2 PROMS AND EPROMS
With a ROM, you have to send a list of data to be stored
in the different memory locations to the manufacturer, who
then produces a mask (a photographic template of the
circuit) used in mass production of your ROMs. In fabri¬
cating ROMs the manufacturer may use bipolar transistors
or MOSFETs. But the idea is still basically the same; the
transistors or MOSFETs act like the diodes of Fig. 9-2.
Programmable
A programmable ROM (PROM) is different. It allows the
user to store the data. An instrument called a PROM
programmer does the storing by “burning in.” (Fusible
links at the bit locations can be burned open by high
currents.) With a PROM programmer, the user can burn in
the program and data. Once this has been done, the
programming is permanent. In other words, the stored
contents cannot be erased.
Chapter 9 Memories 131
Fig. 9-2 ROM with on-chip decoding.
Erasable other words, the EPROM is ultraviolet-light-erasable and
The erasable PROM (EPROM) uses MOSFETs. Data is electrically reprogrammable.
stored with a PROM programmer. Later, data can be erased The EPROM is helpful in design and development. The
with ultraviolet light. The light passes through a window user can erase and store until the program and data are
in the IC package to the chip, where it releases stored perfected. Then the program and data can be sent to an IC
charges. The effect is to wipe out the stored contents. In manufacturer who makes a ROM mask for mass production.
132 Digital Computer Electronics
EEPROM
Another type of reprogrammable ROM device is the
EEPROM (Electrically Erasable Programmable Read Only
Memory), which is nonvolatile like EPROM but does not
require ultraviolet light to be erased. It can be completely
erased or have certain bytes changed, using electrical pulses.
Individual bytes (or any number of bytes) can be changed
using a programmer designed for use with EEPROMs.
Individual bytes can also be changed by the host circuit
after the EEPROM has been installed.
EEPROM is useful when data being gathered by the
circuit must be stored by the system. Writing to EEPROM
is slower than writing to RAM, so it cannot be used in
high-speed circuits.
Unlimited READ cycles are possible; however, EEPROM
will eventually wear out from repeated ERASE cycles.
Since the life of typical EEPROMS allows thousands of
erase cycles, this is usually not a problem.
There are matching EEPROM replacements for most
EPROMs. The EEPROM uses an 8 digit in the part number
whereas EPROM uses a 7 digit. For example, the 2816
EEPROM can replace the 2716 EPROM.
Manufactured Devices
With large-scale integration, manufacturers can fabricate
ROMs, PROMs, and EPROMs that store thousands of
words. For instance, the 8355 is a 16,384-bit ROM orga¬
nized as 2,048 words of 8 bits each. It has 11 address lines
and 8 data lines.
As another example, the 2764 is 65,536-bit EPROM
organized as 8,192 words of 8 bits each. It has 13 address
lines and 8 data lines.
Access Time
The access time of a memory is the time it takes to read a
stored word after applying address bits. Since bipolar
transistors are faster than MOSFETs, bipolar memories
have faster access times than MOS memories. For instance,
the 3636 is a bipolar PROM with an access time of 80 ns;
the 2716 is a MOS EPROM with an access time of 450 ns.
You have to pay for the speed; a bipolar memory is more
expensive than a MOS memory, so it’s up to the designer
to decide which type to use in a specific application.
Three-State Memories
By adding three-state switches to the data lines of a memory
we can get a three-state output. As an example, Fig. 9-3
shows a 16,384-bit ROM organized as 2,048 words of 8
bits each. It has 11 address lines and 8 data lines. A low
ENABLE opens all switches and floats the output lines. On
the other hand, a high ENABLE allows the addressed word
to reach the final output.
Most of the commercially available ROMs, PROMs, and
EPROMs have three-state outputs. In other words, they
have built-in three-state switches that allow you to connect
or disconnect the output lines from a data bus. More will
be said about this later.
Nonvolatile Memory
ROMs, PROMs, and EPROMs are nonvolatile memories.
This means that they retain the stored data even when the
power to the device is shut off. Not all memories are like
this, as will be explained in Sec. 9-3.
EXAMPLE 9-1
A 16 X 8 ROM stores these words in its first four locations:
R 0 = 1110 0010
R : = 0011 1100
R, = 0101 0111
R, = ion mi
Express the stored contents
in hexadecimal notation.
SOLUTION
In hexadecimal shorthand, the stored contents are
R 0 = E2H
R : = 3CH
R, = 57H
R, = BFH
9-3 RAMS
A random-access memory (RAM), or a read-write memory,
is equal to a group of addressable registers. After supplying
an address, you can read the stored contents of the memory
location or write new contents into the memory location.
Core RAMs
The core RAM was the workhorse of earlier computers. It
has the advantage of being nonvolatile; even though you
shut off the power, a core RAM continues to store data.
The disadvantage of core RAMs is that they are expensive
and harder to work with than semiconductor memories.
Semiconductor RAMs
Semiconductor RAMs may be static or dynamic. The static
RAM uses bipolar or MOS flip-flops; data is retained
indefinitely as long as power is applied to the flip-flops.
On the other hand, a dynamic RAM uses MOSFETs and
capacitors that store data. Because the capacitor charge
leaks off, the stored data must be refreshed (recharged)
every few milliseconds. In either case, the RAMs are
volatile; turn off the power and you lose the stored data.
Chapter 9 Memories 133
Sense
line
Control
line
-A_
X
I
Storage
capacitor
(b)
Fig. 9-4 (a) Static cell; ( b) dynamic cell.
RAMs than dynamic RAMs. The remainder of this book
emphasizes static RAMs.
Three-State RAMs
Many of the commercially available RAMs, either static or
dynamic, have three-state outputs. In other words, the
manufacturer includes three-state switches on the chip so
that you can connect or disconnect the output lines of the
RAM from a data bus.
Fig. 9-5 Static RAM with inverted control inputs.
Static RAM
Figure 9-4a shows one of the flip-flops used in a static
MOS RAM. Q x and Q 2 act like switches. Q 3 and Q 4 are
active loads, meaning that they behave like resistors. The
circuit action is similar to the transistor latch discussed in
Sec. 7-1. Either gi conducts and Q 2 is cut off or vice versa.
A static RAM will contain thousands of flip-flops like this,
one for each stored bit. As long as power is applied, the
flip-flop remains latched and can store the bit indefinitely.
Dynamic RAM
Figure 9-4 b shows one of the memory elements (called
cells) in a dynamic RAM. When the sense and control lines
go high, the MOSFET conducts and charges the capacitor.
When the sense and control lines go low, the MOSFET
opens and the capacitor retains its charge. In this way, it
can store 1 bit. A dynamic RAM may contain thousands
of memory cells like Fig. 9-46. Since only a single MOSFET
and capacitor are needed, the dynamic RAM contains more
memory cells than a comparable static RAM, In other
words, a dynamic RAM has more memory locations than
a static RAM of the same physical size.
The disadvantage of the dynamic RAM is the need to
refresh the capacitor charge every few milliseconds. This
complicates the design problem because more circuitry is
needed. In short, it’s much simpler to work with static
Figure 9-5 shows a static RAM and typical input signals.
The ADDRESS bits select the memory location; control
signals WE and CE select a write, read, or do nothing
operation. WE is known as the write-enable signal , and CE
is called the chip-enable signal. Notice that the control
inputs are active low.
Table 9-2 summarizes the operation of the static RAM.
Here’s what happens. A low CE and low WE produce a
write operation. This means that the input data D in is stored
in the addressed memory location. The three-state output
data lines are floating during this write operation.
When CE is low and WE is high, we get a read operation.
The contents of the addressed memory location appear on
the data output lines because the internal three-state switches
are closed at this time. _
The final possibility is CE high. This is a holding pattern
where nothing happens. Internal data at all memory locations
is frozen or unchanged. Notice that the output data lines
are floating.
TABLE 9-2. STATIC RAM
CE
WE
Operation
Output
0
0
Write
Floating
0
1
Read
Connected
1
X
Hold
Floating
134 Digital Computer Electronics
Bubble Memories
A bubble memoiy sandwiches a thin film of magnetic
material between two permanent bias magnets. Logical Is
and Os are represented by magnetic bubbles in this thin
film. The details of how a bubble memory works are too
complicated to go into here. What is worth knowing is that
bubble memories are nonvolatile and capable of storing
huge amounts of data. For instance, the INTEL 7110 is a
bubble memory that can store approximately 1 million bits.
One disadvantage is they have slow access times.
EXAMPLE 9-2
Figure 9-6 shows the pin configuration of a 74189, a
Schottky TTL static RAM with three-state outputs. This
64-bit RAM is organized as 16 words of 4 bits each. It has
an access time of 35 ns. What are the different pin functions?
3 Ycc
□ a 2
□ > 4 ,
□ 4 0
□ D 0
□ Dq
3 D }
3 D,
Fig. 9-6 Pinout for 74189.
GND □
SOLUTION
To begin with, 4 address bits can access 2 4 = 16 words.
This is why the 74189 needs 4 address bits to select the
desired memory location.
The ADDRESS bits go to pin 1 (A 3 ), pin 15 (A 2 ), pin
14 (Aj), and pin 13 (A 0 ). The data inputs are pin 4 (Z) 3 ),
pin 6 (D 2 ), pin 10 (D{), and pin 12 ( D 0 ). Because of the
TTL design, the data is stored as the complement of the
input bits. Thisjs why the data outputs are pin 5 (Z) 3 ), pin
7 (D 2 ), pin 9 (D)), and pin 11 ( D 0 ).
The chip enable is pin 2, and the write enable is pin 3.
These control signals work as previously described. CZf and
WE must be low for a write operation; C£ must be low
and WE high for a read, and CE must be high to do nothing.
Pin 16 gets the supply voltage, which is +5 V, and pin
8 is grounded.
memory. This means that we can store 16 words of 8 bits
each. The bubbles on the output data pins (pins 5, 7, 9,
11) remind us that the stored data bits are the complements
of the input data bits.
Addressing the Memoiy
The address bits come from an address-switch register (A 3 ,
A 2 , A u A 0 ). By setting the switches we can input any
address from 0000 to 1111. As noted at the bottom of Fig.
9-7, an up address switch is equal to a 1. Therefore, the
address with all switches up is 1111.
Setting Up Data
The data inputs come from the two other switch registers.
The upper input nibble is Z) 7 , D 6 , D 5 , and D 4 . The lower
input nibble is D 3 , Z) 2 , D u and D 0 . By setting the data
switches we can input any data word from 0000 0000 to
1111 1111, equivalent to 00H to FFH. The note at the
bottom of Fig. 9-7 indicates that an up data switch produces
an input 0 or an output 1. In other words, a data switch
must be up to store a 1.
Programming the Memory
To program the memory (this means to store instruction
and data words), the run-prog switch must be in the prog
position. This grounds pin 2 (CE) of each 74189. When
the read-write switch is thrown to write, pin 3 (WE ) is
grounded and the complement of the input data word is
written into the addressed memory location.
For instance, suppose we want to store the following
words:
Address
Data
0000
0000 1111
0001
0010 1110
0010
0001 1101
0011
1110 1000
Begin by placing the run-prog switch in the prog position.
To store the first data word at address 0000, set the switches
as follows:
Address Data
DDDD DDDD UUUU
9-4 A SMALL TTL MEMORY
Figure 9-7 shows a modified version of the SAP-1 memory.
Two 74189s (see Appendix 4) are used to get a 16 X 8
where D stands for down and U for up. When the read-
write switch is thrown to write, 0000 1111 is written into
memory location 0000. The read-write switch is then
returned to read in preparation for the next write operation.
Chapter 9 Memories 13 5
W bus
Fig. 9-7 Modified SAP-1 read-write memory.
To load the second word at address 0001, set the address
and data switches as follows:
Address Data
DDDU DDUD UUUD
When the read-write switch is thrown to write, the data
word 0010 1110 is stored at memory location 0001.
Continuing like this, we can program the memory with
the remaining words.
The SAP-1 memory is slightly different from Fig. 9-7
and will be discussed in Chap. 10. What we have discussed
here, however, gives you an example of how a program
and data can be entered into a memory before a computer
run.
9-5 HEXADECIMAL ADDRESSES
During a computer run, the CPU sends binary addresses to
the memory, where read or write operations occur. These
address words may contain 16 or more bits. There’s no
need for us to get bogged down with long strings of binary
numbers. We can chunk those 0s and Is into neat strings
of hexadecimal numbers. Using hexadecimal shorthand is
standard in microprocessor work.
Typical microcomputers have an address bus with 16
address lines. The words on this bus have the binary format
of
ADDRESS = XXXX XXXX XXXX XXXX
For convenience, we can chunk this into its equivalent
hexadecimal form. For instance, instead of writing
ADDRESS = 0101 1110 0111 1100
we can write
ADDRESS = 5E7CH
The 16 address lines can access 2 16 memory locations,
equivalent to 65,536 words. The hexadecimal addresses are
from 0000H to FFFFH. In microcomputers using 8-bit
microprocessors, 1 byte is stored in each memory location.
Figure 9-8 illustrates how to visualize such a memory. The
first memory location has an address of 0000H, the second
memory location an address of 0001H, the third an address
136 Digital Computer Electronics
of 0002H, and so on. Moving toward higher memory, we
eventually reach FFFDH, FFFEH, and FFFFH.
Notice that 1 byte is stored in each memory location.
This is common in products using an 8-bit microprocessor
like the Z80 and 6808. In other words, it is common for
8-bit microprocessor—based products to have a maximum
memory of 64K (IK = 1,024 bytes).
0000H
0001H
0002H
FFFDH
FFFEH
FFFFH
Fig. 9-8 Memory layout.
byte
byte
byte
byte
byte
byte
GLOSSARY
access time The time it takes to read the contents of a
memory location after it has been addressed.
address A way of specifying the location of data in
memory, similar to a house address.
dynamic memory A memory that relies on a MOSFET
switch to charge a capacitor. This memory is highly volatile
because not only must the power be kept on, but the
capacitor charge must also be refreshed every few milli¬
seconds.
EPROM Erasable programmable read-only memory, a
device that is ultraviolet-erasable and electrically repro¬
grammable.
nonvolatile A type of memory in which the stored data
is not lost when the power is turned off.
PROM Programmable read-only memory. With a PROM
programmer, you can burn in your own programs and data.
RAM Random-access memory. It is also called a read-
write memory because you can read the contents of a
memory location or write new contents into it.
ROM Read-only memory. (ROM rhymes with Mom.)
This device provides nonvolatile storage of programs and
data. You can access any memory location by supplying
its address.
static RAM A volatile memory using bipolar or MOSFET
flip-flops. It is easy to work with. Refreshing data is
unnecessary. You simply supply address and control bits
for a read or write operation.
volatile A type of memory in which data stored in the
memory is lost when the power is turned off.
SELF TESTING REVIEW
Read each of the following and provide the missing words.
Answers appear at the beginning of the next question.
1. The memory of a computer is where the_
and-are stored before the calculations
begin. During a computer run, partial answers may
also be stored in the_
2. {program . data , memory) A read-only memory or
-is equivalent to a group of memory
locations, each permanently storing a word. The
-is the only one who can store programs
and data in a ROM.
3. (ROM, manufacturer) The_and contents
of a memory location are two different things. Be¬
cause the address is in binary form, the manufac¬
turer uses on-chip decoding to access the memory
location. With on-chip decoding, n address lines
can access_memory locations.
4. (address, 2 n ) The PROM allows users to store their
own programs and data. An instrument called a
PROM-does the storing or burning in.
Once this is done, the programming is permanent.
5. (programmer) The_is ultraviolet-light-
erasable and electrically programmable. This allows
the user to erase and store until programs and data
are perfected.
6. (EPROM) The-time of a memory is the
Chapter 9 Memories 137
time it takes to read the contents of a memory
location. Bipolar memories are faster than-
memories but more expensive.
7. (access, MOS) ROMs, PROMs, and EPROMs are
_memories. This means that they retain
stored data even though the power is turned off.
Core RAMs are also_, but they are be¬
coming obsolete.
8. ( nonvolatile, nonvolatile ) Semiconductor RAM
memories may be static or-Both are
volatile. The first type uses bipolar or MOS flip-
flops, which means that data is stored as long as
power is applied. The second type uses MOSFETs
and capacitors to store data, which must be
_every few milliseconds.
9. ( dynamic, refreshed) The memory cell of a dynamic
RAM is simpler and smaller than the memory cell
of a_RAM. Because of this, the dy¬
namic RAM can contains more memory cells than a
_RAM of the same chip size.
10. (static, static ) The_bits of a static RAM
select the memory location. The write enable (WE)
and chip enable (CE) select a write, read, or do-
nothing. When WE and CE are both low, you_get a
_operation. When WE is high and CE is
low, you get a_operation. CE high is
the inactive state.
11. (address, write, read) During a computer run, the
CPU sends binary addresses to the-,
where read or write operations occur. Typical mi¬
crocomputers have an address bus with-
bits.
12. (memory, 16) An address bus with 16 bits can
access a maximum of 65,536 memory locations.
The hexadecimal addresses of these memory loca¬
tions are from 0000H to FFFFH. First-generation
microcomputers store 1 byte in each memory loca¬
tion, which implies a maximum memory of 64K.
PROBLEMS
9-1. How many memory locations can 14 address bits
access?
9-2. The 2708 is an 8,192-bit EPROM organized as a
1,024 x 8 memory. How many address pins does
it have?
9-3. The 2732 is a 4,096 X 8 EPROM. How many
address lines does it have?
9-4. An 8156 is a 2,048-bit static RAM with 256
words of 8 bits each. How many address lines
does this RAM have?
9-5. Use U (up) and D (down) to program the TTL
memory of Fig. 9-9 with the following data:
Address
Data
0000
1000 1001
0001
0111 1100
0010
0011 0110
0011
0010 0011
0100
0001 0111
0101
oioi mi
0110
1110 1101
0111
mi iooo
Show your answer by converting each 0 to a D
and each 1 to a U.
9-6. The following data is to be programmed into the
TTL memory of Fig. 9-9:
Address
Data
OH
EEH
1H
5CH
2H
26H
3H
6AH
4H
FDH
5H
15H
6H
94H
7H
C3H
Convert these hexadecimal addresses and contents
to ups (U) and downs (D) as described in Sec.
9-4.
9-7. Address 2000H contains the byte 3FH. What is
the decimal equivalent of 3FH?
9-8. In a 32K memory, the hexadecimal addresses are
from 0000H to 7FFFH. What is the decimal
equivalent of the highest address?
9-9. What is the highest address in a 48K memory?
Express the answer in hexadecimal and decimal
form.
9-10. A byte is stored at hexadecimal location 6F9EH.
What is the decimal address? (Use Appendix 2.)
138 Digital Computer Electronics
W bus
10
12
10 kEL
+5 V-
10 kft
+5 V- V\Ar
WRITE
15
14
13
C6
74189
WE CE
16
-+5 V
8
n
V ^ V ^
X
READ
11
10
12
10 kil
+5 V •
AAA/ — f — +5 V
-AAAr-*
“f-WV—f
15
14
10
13
C7
74189
WE
CE
V V P 9
16
■ +5 V
11
i
* RUN
PROG
Notes: 1. Address switches: Up = 1
2. Data switches: Up = Input 0 = Output 1
Fig. 9-9
9-11. Here is some data stored in a memory:
Address Data
8E00H 2FH
8E01H D4H
8E02H CFH
8E03H 6EH
8E04H 53H
8E05H 7AH
a. What is the decimal equivalent of each stored
byte? (Use Appendix 2.)
b. What is the decimal equivalent of the highest
address?
9-12. Suppose there are four different memories with
the following capacities:
Memory A = 16K
Memory B = 32K
Memory C = 48K
Memory D = 64K
a. How many bytes can memory C store? Express
the answer in decimal.
b. What is the highest decimal address in memory
A?
c. We want to store a byte at address C300H.
Which memory must we use?
d. What is the highest hexadecimal address for
each memory?
9-13. What kind of memory can be programmed and
then erased with ultraviolet light, so that it can be
reprogrammed?
9-14. What kind of memory can be programmed and
then erased with electrical pulses, so that it can be
reprogrammed?
9-15. What kind of nonvolatile memory can have indi¬
vidual bytes reprogrammed without erasing the
entire chip?
All memories start with hexadecimal address
0000H.
Chapter 9 Memories 139
_ PART 2 _
_SAP_
(SIMPLE-AS-POSSIBLE) COMPUTERS
SAP-1
The SAP (Simple-As-Possible) computer has been designed
for you, the beginner. The main purpose of SAP is to
introduce all the crucial ideas behind computer operation
without burying you in unnecessary detail. But even a
simple computer like SAP covers many advanced concepts.
To avoid bombarding you with too much all at once, we
will examine three different generations of the SAP com¬
puter.
SAP-1 is the first stage in the evolution toward modem
computers. Although primitive, SAP-1 is a big step for a
beginner. So, dig into this chapter; master SAP-1, its
architecture, its programming, and its circuits. Then you
will be ready for SAP-2.
10-1 ARCHITECTURE
Figure 10-1 shows the architecture (structure) of SAP-1, a
bus-organized computer. All register outputs to the W bus
are three-state; this allows orderly transfer of data. All other
register outputs are two-state; these outputs continuously
drive the boxes they are connected to.
The layout of Fig. 10-1 emphasizes the registers used in
SAP-1. For this reason, no attempt has been made to keep
all control circuits in one block called the control unit, all
input-output circuits in another block called the I/O unit,
etc.
Many of the registers of Fig. 10-1 are already familiar
from earlier examples and discussions. What follows is a
brief description of each box; detailed explanations come
later.
Program Counter
The program is stored at the beginning of the memory with
the first instruction at binary address 0000, the second
instruction at address 0001, the third at address 0010, and
so on. The program counter , which is part of the control
unit, counts from 0000 to 1111. Its job is to send to the
memory the address of the next instruction to be fetched
and executed. It does this as follows.
The program counter is reset to 0000 before each computer
run. When the computer run begins, the program counter
sends address 0000 to the memory. The program counter
is then incremented to get 0001. After the first instruction
is fetched and executed, the program counter sends address
0001 to the memory. Again the program counter is incre¬
mented. After the second instruction is fetched and executed,
the program counter sends address 0010 to the memory. In
this way, the program counter is keeping track of the next
instruction to be fetched and executed.
The program counter is like someone pointing a finger
at a list of instructions, saying do this first, do this second,
do this third, etc. This is why the program counter is
sometimes called a pointer; it points to an address in
memory where something important is being stored.
Input and MAR
Below the program counter is the input and MAR block. It
includes the address and data switch registers discussed in
Sec. 9-4. These switch registers, which are part of the input
unit, allow you to send 4 address bits and 8 data bits to
the RAM. As you recall, instruction and data words are
written into the RAM before a computer run.
The memory address register (MAR) is part of the SAP-
1 memory. During a computer run, the address in the
program counter is latched into the MAR. A bit later, the
MAR applies this 4-bit address to the RAM, where a read
operation is performed.
The RAM
The RAM is a 16 x 8 static TTL RAM. As discussed
in Sec. 9-4, you can program the RAM by means of the
address and data switch registers. This allows you to store
a program and data in the memory before a computer run.
During a computer run, the RAM receives 4-bit addresses
from the MAR and a read operation is performed. In this way,
the instruction or data word stored in the RAM is placed
on the W bus for use in some other part of the computer.
140
W bus
CpEpL M CE L,E,L a E a SyEyLgL^
Fig. 10-1 SAP -1 architecture.
Instruction Register
The instruction register is part of the control unit. To fetch
an instruction from the memory the computer does a memory
read operation. This places the contents of the addressed
memory location on the W bus. At the same time, the
instruction register is set up for loading on the next positive
clock edge.
The contents of the instruction register are split into two
nibbles. The upper nibble is a two-state output that goes
directly to the block labeled "‘Controller-sequencer.” The
lower nibble is a three-state output that is read onto the W
bus when needed.
Controller-Sequencer
The lower left block contains the controller-sequencer.
Before each computer run, a CLR signal is sent to the
program counter and a CLR signal to the instruction register.
This resets the program counter to 0000 and wipes out the
last instruction in the instruction register.
A clock signal CLK is sent to all buffer registers; this
synchronizes the operation of the computer, ensuring that
things happen when they are supposed to happen. In other
words, all register transfers occur on the positive edge of
a common CLK signal. Notice that a CLK signal also goes
to the program counter.
The 12 bits that come out of the controller-sequencer
form a word controlling the rest of the computer (like a
supervisor telling others what to do.) The 12 wires carrying
the control word are called the control bus.
The control word has the format of
CON = C p E p L m CE LjE^Ea S^Lo
This word determines how the registers will react to the
next positive CLK edge. For instance, a high E P and a low
Chapter 10 SAP-1 141
L m mean that the contents of the program counter are latched
into the MAR on the next positive clock edge. As another
example, a low CE and a low L A mean that the addressed
RAM word will be transferred to the accumulator on the
next positive clock edge. Later, we will examine the timing
diagrams to see exactly when and how these data transfers
take place.
Accumulator
The accumulator (A) is a buffer register that stores inter¬
mediate answers during a computer run. In Fig. 10-1 the
accumulator has two outputs. The two-state output goes
directly to the adder-subtracter. The three-state output goes
to the W bus. Therefore, the 8-bit accumulator word
continuously drives the adder-subtracter; the same word
appears on the W bus when E A is high.
The Adder-Subtracter
SAP-1 uses a 2’s-complement adder-subtracter. When S v
is low in Fig. 10-1, the sum out of the adder-subtracter is
S = A + B
When S v is high, the difference appears:
A = A + B
(Recall that the 2’s complement is equivalent to a decimal
sign change.)
The adder-subtracter is asynchronous (unclocked); this
means that its contents can change as soon as the input
words change. When E v is high, these contents appear on
the W bus.
B Register
The B register is another buffer register. It is used in
arithmetic operations. A low L B and positive clock edge
load the word on the W bus into the B register. The two-
state output of the B register drives the adder-subtracter,
supplying the number to be added or subtracted from the
contents of the accumulator.
Output Register
Example 8-1 discussed the output register. At the end of a
computer run, the accumulator contains the answer to the
problem being solved. At this point, we need to transfer
the answer to the outside world. This is where the output
register is used. When E A is high and L 0 is low, the next
positive clock edge loads the accumulator word into the
output register.
The output register is often called an output port because
processed data can leave the computer through this register.
In microcomputers the output ports are connected to inter¬
face circuits that drive peripheral devices like printers,
cathode-ray tubes, teletypewriters, and so forth. (An inter¬
face circuit prepares the data to drive each device.)
Binary Display
The binary display is a row of eight light-emitting diodes
(LEDs). Because each LED connects to one flip-flop of the
output port, the binary display shows us the contents of the
output port. Therefore, after we’ve transferred an answer
from the accumulator to the output port, we can see the
answer in binary form.
Summary
The SAP-1 control unit consists of the program counter,
the instruction register, and the controller-sequencer that
produces the control word, the clear signals, and the clock
signals. The SAP-1 ALU consists of an accumulator, an
adder-subtracter, and a B register. The SAP-1 memory has
the MAR and a 16 x 8 RAM. The I/O unit includes the
input programming switches, the output port, and the binary
display.
10-2 INSTRUCTION SET
A computer is a useless pile of hardware until someone
programs it. This means loading step-by-step instructions
into the memory before the start of a computer run. Before
you can program a computer, however, you must learn its
instruction set , the basic operations it can perform. The
SAP-1 instruction set follows.
LDA
As described in Chap. 9, the words in the memory can be
symbolized by R 0 , R } , R 2 , etc. This means that R 0 is stored
at address OH, R, at address 1H, R 2 at address 2H, and so
on.
LDA stands for “load the accumulator.” A complete
LDA instruction includes the hexadecimal address of the
data to be loaded. LDA 8H, for example, means “load the
accumulator with the contents of memory location 8H.”
Therefore, given
r 8 = mi oooo
the execution of LDA 8H results in
a= mi oooo
Similarly, LDA AH means “load the accumulator with
the contents of memory location AH,” LDA FH means
“load the accumulator with the contents of memory location
FH,” and so on.
142 Digital Computer Electronics
ADD
ADD is another SAP-1 instruction, A complete ADD
instruction includes the address of the word to be added.
For instance, ADD 9H means “add the contents of memory
location 9H to the accumulator contents”; the sum replaces
the original contents of the accumulator.
Here’s an example. Suppose decimal 2 is in the accu¬
mulator and decimal 3 is in memory location 9H. Then
A = 0000 0010
R 9 = 0000 0011
During the execution of ADD 9H, the following things
happen. First, R 9 is loaded into the B register to get
B = 0000 0011
and almost instantly the adder-subtracter forms the sum of
A and B
SUM = 0000 0101
Second, this sum is loaded into the accumulator to get
A = 0000 0101
The foregoing routine is used for all ADD instructions;
the addressed RAM word goes to the B register and the
adder-subtracter output to the accumulator. This is why the
execution of ADD 9H adds R 9 to the accumulator contents,
the execution of ADD FH adds R F to the accumulator
contents, and so on.
SUB
SUB is another SAP-1 instruction. A complete SUB in¬
struction includes the address of the word to be subtracted.
For example, SUB CH means “subtract the contents of
memory location CH from the contents of the accumulator”;
the difference out of the adder-subtracter then replaces the
original contents of the accumulator.
For a concrete example, assume that decimal 7 is in the
accumulator and decimal 3 is in memory location CH. Then
A = 0000 0111
R c = 0000 0011
The execution of SUB CH takes place as follows. First,
R c is loaded into the B register to get
B = 0000 0011
and almost instantly the adder-subtracter forms the differ¬
ence of A and B:
DIFF = 0000 0100
Second, this difference is loaded into the accumulator and
A = 0000 0100
The foregoing routine applies to all SUB instructions;
the addressed RAM word goes to the B register and the
adder-subtracter output to the accumulator. This is why the
execution of SUB CH subtracts R c from the contents of
the accumulator, the execution of SUB EH subtracts R E
from the accumulator, and so on.
OUT
The instruction OUT tells the SAP-1 computer to transfer
the accumulator contents to the output port. After OUT has
been executed, you can see the answer to the problem being
solved.
OUT is complete by itself; that is, you do not have to
include an address when using OUT because the instruction
does not involve data in the memory.
HLT
HLT stands for halt. This instruction tells the computer to
stop processing data. HLT marks the end of a program,
similar to the way a period marks the end of a sentence.
You must use a HLT instruction at the end of every SAP-
1 program; otherwise, you get computer trash (meaningless
answers caused by runaway processing).
HLT is complete by itself; you do not have to include a
RAM word when using HLT because this instruction does
not involve the memory.
Memory-Reference Instructions
LDA, ADD, and SUB are called memory-reference instruc¬
tions because they use data stored in the memory. OUT
and HLT, on the other hand, are not memory-reference
instructions because they do not involve data stored in the
memory.
Mnemonics
LDA, ADD, SUB, OUT, and HLT are the instruction set
for SAP-1. Abbreviated instructions like these are called
mnemonics (memory aids). Mnemonics are popular in
computer work because they remind you of the operation
that will take place when the instruction is executed. Table
10-1 summarizes the SAP-1 instruction set.
The 8080 and 8085
The 8080 was the first widely used microprocessor. It has
72 instructions. The 8085 is an enhanced version of the
8080 with essentially the same instruction set. To make
SAP practical, the SAP instructions will be upward com-
Chapter 10 SAP-1 1 43
TABLE 10-1. SAP-1 INSTRUCTION SET
the contents of memory location 9H, and so the accumulator
contents become
Mnemonic
Operation
LDA
Load RAM data into accumulator
ADD
Add RAM data to accumulator
SUB
Subtract RAM data from accumulator
OUT
Load accumulator data into output
register
HLT
Stop processing
patible with the 8080/8085 instruction set. In other words,
the SAP-1 instructions LDA, ADD, SUB, OUT, and HLT
are 8080/8085 instructions. Likewise, the SAP-2 and SAP-
3 instructions will be part of the 8080/8085 instruction set.
Learning SAP instructions is getting you ready for the 8080
and 8085, two widely used microprocessors.
EXAMPLE 10-1
Here’s a SAP-1 program in
mnemonic form:
Address
Mnemonics
OH
LDA 9H
1H
ADD AH
2H
ADD BH
3H
SUB CH
4H
OUT
5H
HLT
The data in higher memory
is
Address
Data
6H
FFH
7H
FFH
8H
FFH
9H
01H
AH
02H
BH
03H
CH
04H
DH
FFH
EH
FFH
FH
FFH
What does each instruction do?
SOLUTION
The program is in the low memory, located at addresses
OH to 5H. The first instruction loads the accumulator with
A = 01H
The second instruction adds the contents of memory location
AH to the accumulator contents to get a new accumulator
total of
A = 01H + 02H = 03H
Similarly, the third instruction add the contents of memory
location BH
A = 03H + 03H = 06H
The SUB instruction subtracts the contents of memory
location CH to get
A = 06H — 04H = 02H
The OUT instruction loads the accumulator contents into
the output port: therefore, the binary display shows
0000 0010
The HLT instruction stops the data processing.
10-3 PROGRAMMING SAP-1
To load instruction and data words into the SAP-1 memory
we have to use some kind of code that the computer can
interpret. Table 10-2 shows the code used in SAP-1. The
number 0000 stands for LDA, 0001 for ADD, 0010 for
SUB, 1110 for OUT, and 1111 for HLT. Because this code
tells the computer which operation to perform, it is called
an operation code (op code).
As discussed earlier, the address and data switches of
Fig. 9-7 allow you to program the SAP-1 memory. By
design, these switches produce a 1 in the up position (U)
TABLE 10-2. SAP-1
OP CODE
Mnemonic
Op code
LDA
0000
ADD
0001
SUB
0010
OUT
1110
HLT
mi
144 Digital Computer Electronics
SOLUTION
and a 0 in the down position (D). When programming the
data switches with an instruction, the op code goes into the
upper nibble, and the operand (the rest of the instruction)
into the lower nibble.
For instance, suppose we want to store the following
instructions:
Address Instruction
OH LDA FH
1H ADD EH
2H HLT
First, convert each instruction to binary as follows:
LDA FH = 0000 1111
ADD EH = 0001 1110
HLT = 1111 XXXX
In the first instruction, 0000 is the op code for LDA, and
1111 is the binary equivalent of FH. In the second instruc¬
tion, 0001 is the op code for ADD, and 1110 is the binary
equivalent of EH. In the third instruction, 1111 is the op
code for HLT, and XXXX are don't cares because the HLT
is not a memory-reference instruction.
Next, set up the address and data switches as follows:
Address Data
DDDD DDDD UUUU
DDDU DDDU UUUD
DDUD UUUU XXXX
After each address and data word is set, you press the write
button. Since D stores a binary 0 and U stores a binary 1,
the first three memory locations now have these contents:
Here is the program of Example 10-1:
Address
Instruction
OH
LDA 9H
1H
ADD AH
2H
ADD BH
3H
SUB CH
4H
OUT
5H
HLT
This program is in assembly language as it now stands. To
get it into machine language, we translate it to 0s and Is
as follows:
Address Instruction
0000 0000 1001
0001 0001 1010
0010 0001 1011
0011 00101100
0100 1110 XXXX
oioi mi xxxx
Now the program is in machine language.
Any program like the foregoing that’s written in machine
language is called an object program . The original program
with mnemonics is called a source program . In SAP-1 the
operator translates the source program into an object program
when programming the address and data switches.
A final point. The four MSBs of a SAP-1 machine-
language instruction specify the operation, and the four
LSBs give the address. Sometimes we refer to the MSBs
as the instruction field and to the LSBs as the address field.
Symbolically,
Instruction = XXXX XXXX
Address Contents
0000 0000 1111
0001 0001 1110
ooio mi xxxx
A final point. Assembly language involves working with
mnemonics when writing a program. Machine language
involves working with strings of 0s and Is. The following
examples bring out the distinction between the two lan¬
guages.
Instruction field
Address field —
EXAMPLE 10-3
How would you program SAP-1 to solve this arithmetic
problem?
16 + 20 4- 24 - 32
The numbers are in decimal form.
EXAMPLE 10-2
Translate the program of Example 10-1 into SAP-1 machine
language.
SOLUTION
One way is to use the program of the preceding example,
storing the data (16, 20, 24, 32) in memory locations 9H
Chapter 10 SAP-1 145
to CH. With Appendix 2, you can convert the decimal data
into hexadecimal data to get this assembly-language version:
Address
Contents
OH
LDA 9H
1H
ADD AH
2H
ADD BH
3H
SUB CH
4H
OUT
5H
HLT
6H
XX
7H
XX
8H
XX
9H
10H
AH
14H
BH
18H
CH
20H
The machine-language version is
Address
Contents
0000
0000 1001
0001
0001 1010
0010
0001 1011
0011
0010 1100
0100
1110XXXX
0101
1111 XXXX
0110
XXXX XXXX
0111
XXXX XXXX
1000
XXXX XXXX
1001
0001 0000
1010
0001 0100
1011
0001 1000
1100
0010 0000
Notice that the program
is stored ahead of the data. In
other words, the program
is in low memory and the data
in high memory. This is
essential in SAP-1 because the
program counter points to address 0000 for the first instruc¬
tion, 0001 for the second instruction, and so forth.
EXAMPLE 10-4
Chunk the program and data of the preceding example by
converting to hexadecimal shorthand.
SOLUTION
Address
Contents
OH
09H
1H
1AH
2H
1BH
3H
2CH
4H
EXH
5H
FXH
6H
XXH
7H
XXH
8H
XXH
9H
10H
AH
14H
BH
18H
CH
20H
This version of the program and data is still considered
machine language.
Incidentally, negative data is loaded in 2’s-complement
form. For example, — 03H is entered as FDH.
10-4 FETCH CYCLE
The control unit is the key to a computer’s automatic
operation. The control unit generates the control words that
fetch and execute each instruction. While each instruction
is fetched and executed, the computer passes through
different timing states (T states), periods during which
register contents change. Let’s find out more about these T
states.
Ring Counter
Earlier, we discussed the SAP-1 ring counter (see Fig.
8-16 for the schematic diagram). Figure 10-2a symbolizes
the ring counter, which has an output of
T = T 6 T 5 T 4 T 3 T 2 T {
At the beginning of a computer run, the ring word is
T = 000001
Successive clock pulses produce ring words of
T = 000010
T = 000100
T = 001000
T = 010000
T = 100000
Then, the ring counter resets to 000001, and the cycle
repeats. Each ring word represents one T state.
Figure 10-27? shows the timing pulses out of the ring
counter. The initial state T x starts with a negative clock
edge and ends with the next negative clock edge. During
this T state, the 7\ bit out of the ring counter is high.
During the next state, T 2 is high; the following state has
a high T 3 ; then a high 7 4 ; and so on. As you can see, the
1 46 Digital Computer Electronics
(a)
CLK
CLR
r ’J I_| L
T 2 r '
7-6 _
(b)
Fig. 10-2 Ring counter: (a) symbol; ( b ) clock and timing signals.
ring counter produces six T states. Each instruction is
fetched and executed during these six T states.
Notice that a positive CLK edge occurs midway through
each T state. The importance of this will be brought out
later.
Address State
The T j state is called the address state because the address
in the program counter (PC) is transferred to the memory
address register (MAR) during this state. Figure 10-3 a
shows the computer sections that are active during this state
(active parts are light; inactive parts are dark).
During the address state, E P and L M are active; all other
control bits are inactive. This means that the controller-
sequencer is sending out a control word of
CON = C p E p L m CE LjEjLaEa S^LJlo
= 0 1 0 1 1110 0011
during this state.
Increment State
Figure 10-3 b shows the active parts of SAP-1 during the
T 2 state. This state is called the increment state because the
program counter is incremented. During the increment state,
the controller-sequencer is producing a control word of
CON = C p E p L m CE LjEjLaEa SuEuLbLq
= 101 1 1110 0011
As you see, the C P bit is active.
Memory State
The r 3 state is called the memory state because the addressed
RAM instruction is transferred from the memory to the
instruction register. Figure 10-3c shows the active parts of
SAP-1 during the memory state. The only active control
bits during this state are CE and L h and the word out of
the controller-sequencer is
CON = C P E P L M CE L t E t L a E a SuEuLbLo
= 0010 0110 0011
Chapter 10 SAP-1 147
Fetch Cycle
The address, increment, and memory states are called the
fetch cycle of SAP-1. During the address state, E P and L M
are active; this means that the program counter sets up the
MAR via the W bus. As shown earlier in Fig. 10-2 b, a
positive clock edge occurs midway through the address
state; this loads the MAR with the contents of the PC.
C P is the only active control bit during the increment
state. This sets up the program counter to count positive
clock edges. Halfway through the increment state, a positive
clock edge hits the program counter and advances the count
by 1. _ _
During the memory state, CE and L, are active. Therefore,
the addressed RAM word sets up the instruction register
via the W bus. Midway through the memory state, a positive
clock edge loads the instruction register with the addressed
RAM word.
10-5 EXECUTION CYCLE
The next three states (T 4 , T 5 , and T 6 ) are the execution
cycle of SAP-1. The register transfers during the execution
cycle depend on the particular instruction being executed.
For instance, LDA 9H requires different register transfers
than ADD BH. What follows are the control routines for
different SAP-1 instructions.
LDA Routine
For a concrete discussion, let’s assume that the instruction
register has been loaded with LDA 9H:
IR = 0000 1001
During the T 4 state, the instruction field 0000 goes to the
controller-sequencer, where it is decoded; the address field
1001 is loaded into the MAR. Figure 10-4a shows the
active parts of SAP-1 during the T 4 state. Note that E, and
L m are active; all other control bits are inactive.
During the T s state, CE and L A go low. This means that
the addressed data word in the RAM will be loaded into
the accumulator on the next positive clock edge (see Fig.
10-46).
T 6 is a no-operation state. During this third execution
state, all registers are inactive (Fig. 10-4c). This means
that the controller-sequencer is sending out a word whose
bits are all inactive. Nop (pronounced no op) stands for
“no operation." The T 6 state of the LDA routine is a nop.
Figure 10-5 shows the timing diagram for_the fetch and
LDA routines. During the T ] state, E P and L M are active;
the positive clock edge midway through this state will
transfer the address in the program counter to the MAR.
During the T 2 state, C P is active and the program counter
is incremented on the positive clock edge. During the T 3
state, CE and L, are active; when the positive clock edge
occurs, the addressed RAM word is transferred to the
instruction register. The LDA execution starts with the T 4
state, where L M and E, are active; on the positive clock
edge the address field in the instruction register is transferred
to the MAR. During the T 5 state, CE and L A are active;
this meahs that the addressed RAM data word is transferred
to the accumulator on the positive clock edge. As you
know, the T b state of the LDA routine is a nop.
ADD Routine
Suppose at the end of the fetch cycle the instruction register
contains ADD BH:
IR = 0001 1011
During the T 4 state the instruction field goes to the controller-
sequencer and the address field to the MAR (see Fig.
10-6a). During this state d and L M are active.
Control bits CE and L B are active during the T 5 state.
This allows the addressed RAM word to set up the B
148 Digital Computer Electronics
A
CON
CON
(a) (b)
Fig. 10-4 LDA routine: (a) T 4 state; ( b ) T 5 state; (c) T 6 state.
m
■its
■
i
m
lii
1:
m
me an
s
’
m
I
sm
» mmm-
I
1
/'/JL'§1
ff|jj§
CON
(c)
Fig. 10-5 Fetch and LDA timing diagram.
CON
CON
< a > (b) ( C )
Fig. 10-6 ADD and SUB routines: (a) T A state; (b) T s state; (c)
T 6 state.
Chapter 10 SAP-1 149
register (Fig. 10-66). As usual, loading takes place midway
through the state when the positive clock edge hits the CLK
input of the B register.
During the T 6 state, E v and L A are active; therefore, the
adder-subtracter sets up the accumulator (Fig. 10-6c).
Halfway through this state, the positive clock edge loads
the sum into the accumulator.
Incidentally, setup time and propagation delay time
prevent racing of the accumulator during this final execution
state. When the positive clock edge hits in Fig. 10-6c, the
accumulator contents change, forcing the adder-subtracter
contents to change. The new contents return to the accu¬
mulator input, but the new contents don’t get there until
two propagation delays after the positive clock edge (one
for the accumulator and one for the adder-subtracter). By
then it’s too late to set up the accumulator. This prevents
accumulator racing (loading more than once on the same
clock edge).
Figure 10-7 shows the timing diagram for the fetch and
ADD routines. The fetch routine is the same as before: the
T x state loads the PC address into the MAR; the T 2 state
increments the program counter; the T 3 state sends the
addressed instruction to the instruction register.
During the T 4 state, Ej and L M are active; on the next
positive clock edge, the address field in the instruction
register goes to the MAR. During the T 5 state, CE and L B
are active; therefore, the addressed RAM word is loaded
into the B register midway through the state. During the T 6
state, Ejj and L A are active; when the positive clock edge
hits, the sum out of the adder-subtracter is stored in the
accumulator.
SUB Routine
The SUB routine is similar to the ADD routine. Figure
10-6 a and b show the active parts of SAP-1 during the T 4
and T 5 states. During the T 6 state, a high Su is sent to the
adder-subtracter of Fig. 10-6c. The timing diagram is almost
identical to Fig. 10-7. Visualize S v low during the T x to T 5
states and S^high during the T 6 state.
OUT Routine
Suppose the instruction register contains the OUT instruction
at the end of a fetch cycle. Then
IR = 1110 XXXX
Fig. 10-7 Fetch and ADD timing diagram.
The instruction field goes to the controller-sequencer for
decoding. Then the controller-sequencer sends out the
control word needed to load the accumulator contents into
the output register.
Figure 10-8 shows the active sections of SAP-1 during
the execution of an OUT instruction. Since E A and L 0 are
active, the next positive clock edge loads the accumulator
contents into the output register during the T 4 state. The T 5
and r 6 states are nops.
Figure 10-9 is the timing diagram for the fetch and OUT
routines. Again, the fetch cycle is same: address state,
increment state, and memory state. During the T 4 state, E A
and L 0 are active; this transfers the accumulator word to
the output register when the positive clock edge occurs.
150 Digital Computer Electronics
CE
L,
Fig. 10-9 Fetch and OUT timing diagram.
HLT
HLT does not require a control routine because no registers
are involved in the execution of an HLT instruction. When
the IR contains
IR = 1111 XXXX
the instruction field 1111 signals the controller-sequencer
to stop processing data. The controller-sequencer stops the
computer by turning off the clock (circuitry discussed later).
Machine Cycle and Instruction Cycle
SAP-1 has six T states (three fetch and three execute).
These six states are called a machine cycle (see Fig.
10-10a). It takes one machine cycle to fetch and execute
each instruction. The SAP-1 clock has a frequency of 1
kHz, equivalent to a period of 1 ms. Therefore, it takes 6
ms for a SAP-1 machine cycle.
SAP-2 is slightly different because some of its instructions
take more than one machine cycle to fetch and execute.
Figure 10-10/? shows the timing for an instruction that
requires two machine cycles. The first three T states are
the fetch cycle; however, the execution cycle requires the
next nine T states. This is because a two-machine-cycle
instruction is more complicated and needs those extra T
states to complete the execution.
The number of T states needed to fetch and execute an
instruction is called the instruction cycle . In SAP-1 the
instruction cycle equals the machine cycle. In SAP-2 and
other microcomputers the instruction cycle may equal two
or more machine cycles, as shown in Fig. 10-10/?.
The instruction cycles for the 8080 and 8085 take from
one to five machine cycles (more on this later).
EXAMPLE 10-5
The 8080/8085 programming manual says that it takes
thirteen T states to fetch and execute the LDA instruction.
(a)
(b)
Fig. 10-10 (a) SAP-1 instruction cycle; (Z?) instruction cycle with
two machine cycles.
Chapter 10 SAP-1 151
If the system clock has a frequency of 2.5 MHz, how long
is an instruction cycle?
SOLUTION
The period of the clock is
T = - =---= 400 ns
/ 2.5 MHz
Therefore, each T state lasts 400 ns. Since it takes thirteen
T states to fetch and execute the LDA instruction, the
instruction cycle lasts for
13 X 400 ns = 5,200 ns = 5.2 p,s
EXAMPLE 10-6
Figure 10-11 shows the six T states of SAP-1. The positive
clock edge occurs halfway through each state. Why is this
important?
SOLUTION
SAP-1 is a bus-organized computer (the common type
nowadays). This allows its registers to communicate via
the W bus. But reliable loading of a register takes place
only when the setup and hold times are satisfied. Waiting
half a cycle before loading the register satisfies the setup
time; waiting half a cycle after loading satisfies the hold
time. This is why the positive clock edge is designed to
strike the registers halfway through each T state (Fig.
10 - 11 ).
There’s another reason for waiting half a cycle before
loading a register. When the ENABLE input of the sending
register goes active, the contents of this register are suddenly
dumped on the W bus. Stray capacitance and lead inductance
prevent the bus lines from reaching their correct voltage
levels immediately. In other words, we get transients on
the W bus and have to wait for them to die out to ensure
valid data at the time of loading. The half-cycle delay
before clocking allows the data to settle before loading.
10-6 THE SAP-1 MICROPROGRAM
We will soon be analyzing the schematic diagram of the
SAP-1 computer, but first we need to summarize the
execution of SAP-1 instructions in a neat table called a
microprogram.
Microinstructions
The controller-sequencer sends out control words, one
during each T state or clock cycle. These words are like
directions telling the rest of the computer what to do.
Because it produces a small step in the data processing,
each control word is called a microinstruction. When looking
at the SAP-1 block diagram (Fig. 10-1), we can visualize
a steady stream of microinstructions flowing out of the
controller-sequencer to the other SAP-1 circuits.
Macroinstructions
The instructions we have been programming with (LDA,
ADD, SUB, . . .) are sometimes called macroinstructions
to distinguish them from microinstructions. Each SAP-1
macroinstruction is made up of three microinstructions. For
example, the LDA macroinstruction consists of the mi¬
croinstructions in Table 10-3. To simplify the appearance
of these microinstructions, we can use hexadecimal chunk¬
ing as shown in Table 10-4.
Table 10-5 shows the SAP-1 microprogram, a listing of
each macroinstruction and the microinstructions needed to
carry it out. This table summarizes the execute routines for
the SAP-1 instructions. A similar table can be used with
more advanced instruction sets.
10-7 THE SAP-1 SCHEMATIC
DIAGRAM
In this section we examine the complete schematic diagram
for SAP-1. Figures 10-12 to 10-15 show all the chips,
wires, and signals. You should refer to these figures
throughout the following discussion. Appendix 4 gives
additional details for some of the more complicated chips.
edge + edge + edge
i 1 l
+ edge + edge + edge
1 i i
Fig. 10-11 Positive clock edges occur midway through T states.
1 52 Digital Computer Electronics
TABLE 10-3
Macro
State
Cp Ep L m
CE
Li Ej L a E a
SuEuLbLq
Active
LDA
t 4
0 0 0
1
10 10
0 0 11
L m , Ej
t 5
0 0 1
0
110 0
0 0 11
CE, L a
t 6
0 0 1
1
1110
0 0 11
None
TABLE 10-4
Macro
State
CON
Active
LDA
T 4
1A3H
La/5 Ej
t 5
2C3H
CE, L a
t 6
3E3H
None
TABLE 10-5. SAP-1 MICROPROGRAMf
Macro
State
CON
Active
LDA
t a
1A3H
L m , Ei
t 5
2C3H
CE, L a
t 6
3E3H
None
ADD
t 4
1A3H
L m , Ej
t 5
2E1H
CE, L b
t 6
3C7H
Ea9 E(J
SUB
t 4
1A3H
L M , Ej
T s
2E1H
CE, L b
t 6
3CFH
L A9 S v , Ejj
OUT
t 4
3F2H
Ea* E q
T s
3E3H
None
T 6
3E3H
None
+ CON =
C p E p L m CE
l,e,l a e a
SuEuLbLo.
Program Counter
Chips Cl, C2, and C3 of Fig. 10-12 are the program
counter. Chip Cl, a 74LS107, is a dual JK master-slave
flip-flop, that produces the upper 2 address bits. Chip C2,
another 74LS107, produces the lower 2 address bits. Chip
C3 is a 74LS126, a quad three-state normally open switch;
it gives the program counter a three-state output.
At the start of a computer run, a low CLR resets the
program counter to 0000. During the T } state, a high E P
places the address on the W bus. During the T 2 state, a
high C P is applied to the prog ram counter; midway through
this state, the negative CLK edge (equivalent to positive
CLK edge) increments the program counter.
The program counter is inactive during the T 3 to T 6 states.
MAR
Chip C4, a 74LS173, is a 4-bit buffer register; it serves as
the MAR. Notice that pins 1 and 2 are grounded; this
converts the three-state output to a two-state output. In
other words, the output of the MAR is not connected to
the W bus, and so there’s no need to use the three-state
output.
2-to-l Multiplexer
Chip C5 is a 74LS157, a 2-to-l nibble multiplexer. The
left nibble (pins 14, 11, 5, 2) comes from the address
switch register (SO- The right nibble (pins 13, 10, 6, 3)
comes from the MAR. The run-prog switch (S 2 ) selects
the nibble to reach to the output of C5. When S 2 is in the
prog position, the nibble out of the address switch register
is selected. On the other hand, when S 2 is the run position,
the output of the MAR is selected.
16 x 8 RAM
Chips C6 and C7 are 74189s. Each chip is a 16 x 4 static
RAM. Together, they give us a 16 X 8 read-write memory ;.
S 3 is the data switch register (8 bits), and S 4 is the read-
write switch (a push-button switch). To program the mem¬
ory, S 2 is put in the prog position; this takes the CE input
low (pin 2). The address and data switches are then set to
the correct address and data words. A momentary push of
the read-write switch takes WE low (pin 3) and loads the
memory.
After the program and data are in memory, the run-
prog switch (S 2 ) is put in the run position in preparation
for the computer run.
Instruction Register
Chips C8 and C9 are 74LS173s. Each chip is a 4-bit three-
state buffer register. The two chips are the instruction
register. Grounding pins 1 and 2 of C8 converts the three-
state output to a two-state output, I 7 I 6 I 5 I 4 . This nibble goes
to the instruction decoder in the controller-sequencer. Signal
Ej controls the output of C9, the lower nibble in the
instruction register. When Ej is low, this nibble is placed
on the W bus.
Chapter 10 SAP-1 153
74LS107 74LS107
I_I
154 Digital Computer Electronics
Chapter 10 SAP-1 155
Fig. 10-12 SAP-1 program counter, memory, and instruction register.
W bus
156 Digital Computer Electronics
Chapter 10 SAP-1 157
Fig. 10-13 A and B registers, adder-subtracter, and output circuits.
Accumulator
Chips CIO and Cll, 74LS173s, are the accumulator (see
Fig. 10-13). Pins 1 and 2 are grounded on both chips to
produce a two-state output for the adder-subtracter. Chips
C12 and Cl3 are 74LS126s; these three-state switches place
the accumulator contents on the W bus when E A is high.
Adder-subtracter
Chips C14 and C15 are 74LS86s. These exclusive-or
gates are a controlled inverter. When Sy is low, the contents
of the B register are transmitted. When S v is high, the l’s
complement is transmitted and a 1 is added to the LSB to
form the 2’s complement.
Chips C16 and C17 are 74LS83s. These 4-bit full adders
combine to produce an 8-bit sum or difference. Chips C18
and C19, which are 74LS126s, convert this 8-bit answer
into a three-state output for driving the W bus.
B Register and Output Register
Chips C20 and C21, which are 74LS173s, form the B
register. It contains the data to be added or subtracted from
the accumulator. Grounding pins 1 and 2 of both chips
produces a two-state output for the adder-subtracter.
Chips C22 and C23 are 74LS173s and form the output
register. It drives the binary display and lets us see the
processed data.
Clear-Start Debouncer
In Fig. 10-14, the clear-start debouncer p roduc es two
outputs: CLR for the instruction re giste r and CLR for the
program counter and ring counter. CLR also goes to C29,
the clock-start flip-flop. S 5 is a push-button switch. When
depressed, it goes to the clear position, generating a high
CLR and a low CLR. When S 5 is released, it retur ns to the
start position, producing a low CLR and a high CLR.
Notice that half of C24 is used for the dear-start debouncer
and the other half for the single-step debouncer. Chip C24
is a 7400, a quad 2-input nand gate.
Single-Step Debouncer
SAP-1 can run in either of two modes, manual or automatic.
In the manual mode, you press and release S 6 to generate
one clock pulse. When S 6 is depressed, CLK is high; when
released, CLK is low. In other words, the single-step
debouncer of Fig. 10-14 generates the T states one at a
time as you press and release the button. This allows you
to step through the different T states while troubleshooting
or debugging. (Debugging means looking for errors in your
program. You troubleshoot hardware and debug software.)
Manual-Auto Debouncer
Switch S 7 is a single-pole double-throw (SPDT) switch that
can remain in either the manual position or the auto
position. When in manual, the single-step button is active.
When in auto, the computer runs automatically. Two of
the nand gates in C26 are used to debounce the manual-
auto switch. The other two nand C26 gates are part of a
nand-nand network that steers the si ngle-s tep clock or the
automatic clock to the final CLK and CLK outputs.
Clock Buffers
The output of pin 11, C26, drives the clock buffers. As
you see in Fig. 10-14, two inverters are used to pro duce
the final CLK output and one inverter to produce the CLK
output. Unlike most of the other chips, C27 is standard
TTL rather than a low-power Schottky (see SAP-1 Parts
List, Appendix 5). Standard TTL is used because it can
drive 20 low-power Schottky TTL loads, as indicated in
Table 4-5.
If you check the data sheets of the 74LS107 and 74LS173
for input currents, you will be able to count the following
low-power Schottky (LS) TTL loads on the clock and clear
signals:
CLK = 19 LS loads
CLK = 2 LS loads
CLR = 1 LS load
CLR = 20 LS loads
This means that the CLK and CLK signals out of C27
(standard TTL) are adequate to dri ve the low-power Schottky
TTL loads. Also, the CLR and CLR signals out of C24
(standard TTL) can drive their loads.
Clock Circuits and Power Supply
Chip C28 is a 555 timer. This IC produces a rectangular
2-kHz output with a 75 percent duty cycle. As previously
discussed, a start-the-clockflip-flop (C29) divides the signal
down to 1 kHz and at the same time produces a 50 percent
duty cycle.
The power supply consists of a full-wave bridge rectifier
working into a capacitor-input filter. The dc voltage across
the 1,000-jJiF capacitor is approximately 20 V. Chip C30,
an LM340T-5, is a voltage regulator that produces a stable
output of +5 V.
Instruction Decoder
Chip C31, a hex inverter, produces complements of the
op-code bits, I 7 I 6 I 5 l 4 (see Fig. 10-15). Then chips C32,
C33, and C34 decode the op code to produce five output
signals: LDA , ADD , SUB , OUT, and HLT. Remember:
158 Digital Computer Electronics
only one of these is active at a time. (HLT is active low;
all the others are active high.)
When the HLT instruct ion is in the instruction register ,
bits I 7 I 6 I 5 I 4 are 1111 and HLT is low. This signal returns
to C25 (single-step clock) and C29 (automatic clock). In
either manual or AUTO mode, the clock stops and the
computer run ends.
Ring Counter
The ring counter, sometimes called a state counter , consists
of three chips, C36, C37, and C38. Each of these chips is
a 74LS107, a dual JK master-slave flip-flop. This counter
is reset when the clear-start button (S 5 ) is pressed. The Q 0
flip-flop is inverted so that its Q output (pin 6, C38) drives
Chapter 10 SAP-1 159
RING COUNTER
160 Digital Computer Electronics
Fig. 10-15 Instruction decoder, ring counter, and control matrix.
the J input of the Q x flip-flop (pin 1, C38). Because of this,
the T x output is initially high.
The CLK signal drives an active low input. This means
that the negative edge of the CLK signal initiates each T
state. Half a cycle later, the positive edge of the CLK signal
produces register loading, as previously described.
Control Matrix
The LDA , ADD, SUB, and OUT signals from the instruction
decoder drive the control matrix, C39 to C48. At the same
time, the ring-counter signals, T, to T 6 , are driving the
matrix (a circuit receiving two groups of bits from different
sources). The matrix produces CON, a 12-bit microinstruc¬
tion that tells the rest of the computer what to do.
In Fig. 10-15, T, goes high, then T 2 , then T 3 , and so on.
Analyze the control matrix and here is what you will find.
A high T } produces a high E P and a low L M (address state);
a high T 2 results in ahigh C P (increment state); and a high
T 3 produces a low CE and a low Lj (memory state). The
first three T states, therefore, are always the fetch cycle in
SAP-1. In chunked notation, the CON words for the fetch
cycle are
State
CON
Active Bits
r,
5E3H
Epi L m
t 2
BE3H
C P
t 3
263H
CE, Lj
During the execution states, T A through T e go high in
succession. At the same time, only one of the decoded
signals (LDA through OUT) is high. Because of this, the
matrix automatically steers active bits to the correct output
control lines.
For instance, when LDA is high, the only enabled 2-
input nand gates are the first, fourth, seventh, and tenth.
When J 4 is high, it activates the first and seventh nand
gates, resulting in low L M and low % (load MAR with
address field). When T 5 is high, it activates the fourth and
tenth nand gates, producing a low CE and a low L A (load
RAM data into accumulator). When T 6 goes high, none of
the control bits are active (nop).
You should analyze the action of the control matrix
during the execution states of the remaining possibilities:
high ADD, high SUB , and high OUT. Then you will agree
the control matrix can generate the ADD, SUB, and OUT
microinstructions shown in Table 10-5 (SAP-1 micropro¬
gram).
Operation
Before each computer run, the operator enters the program
and data into the SAP-1 memory. With the program in low
memory and the data in high memory, the operator presses
and releases the clear button. The CLK and CLK signals
drive the registers and counters. The microinstruction out
of the controller-sequencer determines what happens on
each positive CLK edge.
Each SAP-1 machine cycle begins with a fetch cycle. T,
is the address state, T 2 is the increment state, and T 3 is the
memory state. At the end of the fetch cycle, the instruction
is stored in the instruction register. After the instruction
field has been decoded, the control matrix automatically
generates the correct execution routine. Upon completion
of the execution cycle, the ring counter resets and the next
machine cycle begins.
The data processing ends when a HLT instruction is
loaded into the instruction register.
10-8 MICROPROGRAMMING
The control matrix of Fig. 10-15 is one way to generate
the microinstructions needed for each execution cycle. With
larger instruction sets, the control matrix becomes very
complicated and requires hundreds or even thousands of
gates. This is why hardwired control (matrix gates soldered
together) forced designers to look for an alternative way to
produce the control words that run a computer.
Microprogramming is the alternative. The basic idea is
to store microinstructions in a ROM rather than produce
them with a control matrix. This approach simplifies the
problem of building a controller-sequencer.
Storing the Microprogram
By assigning addresses and including the fetch routine, we
can come up with the SAP-1 microinstructions shown in
Table 10-6. These microinstructions can be stored in a
control ROM with the fetch routine at addresses OH to 2H,
the LDA routine at addresses 3H to 5H, the ADD routine
at 6H to 8H, the SUB routine at 9H to BH, and the OUT
routine at CH to EH.
To access any routine, we need to supply the correct
addresses. For instance, to get the ADD routine, we need
to supply addresses 6H, 7H, and 8H. To get the OUT
routine, we supply addresses CH, DH, and EH. Therefore,
accessing any routine requires three steps:
1. Knowing the starting address of the routine
2. Stepping through the routine addresses
3. Applying the addresses to the control ROM.
Address ROM
Figure 10-16 shows how to microprogram the SAP-1
computer. It has an address ROM, a presettable counter,
and a control ROM. The address ROM contains the starting
addresses of each routine in Table 10-6. In other words,
Chapter 10 SAP-1 161
TABLE 10-6. SAP-1 CONTROL ROM
Address
Contents!
Routine
Active
OH
5E3H
Fetch
E P , L m
1H
BE3H
C P
2H
263H
CE, L,
3H
1A3H
LDA
Lm 9 Ei
4H
2C3H
CE, L a
5H
3E3H
None
6 H
1A3H
ADD
Lm , Ei
7H
2E1H
ce,l b
8 H
3C7H
La , Ejj
9H
1A3H
SUB
Lm> Ej
AH
2E1H
CE, Lq
BH
3CFH
L a , $u, Eu
CH
3F2H
OUT
e a , l 0
DH
3E3H
None
EH
3E3H
None
FH
X
X
Not used
f CON =
CpE P L M CE LjELaEa
„ SuEuLbLq.
t~j ^6 ^5 ^4
Microinstruction
Fig. 10-16 Microprogrammed control of SAP-1.
the address ROM contains the data listed in Table 10-7.
As shown, the starting address of the LDA routine is 0011,
the starting address of the ADD routine is 0110, and so on.
When the op-code bits I 7 I 6 I 5 I 4 drive the address ROM,
the starting address is generated. For instance, if the ADD
TABLE 10-7. ADDRESS ROM
Address
Contents
Routine
0000
oou
LDA
0001
0110
ADD
0010
1001
SUB
0011
xxxx
None
0100
xxxx
None
0101
xxxx
None
0110
xxxx
None
0111
xxxx
None
1000
xxxx
None
1001
xxxx
None
1010
xxxx
None
1011
xxxx
None
1100
xxxx
None
1101
xxxx
None
1110
1100
OUT
1111
xxxx
None
instruction is being executed, I 7 I 6 I 5 l 4 is 0001. This is the
input to the address ROM; the output of this ROM is 0110.
Presettable Counter
When T 3 is high, the load input of the presettable counter
is high and the counter loads the starting address from the
address ROM. During the other T states, the counter counts.
Initially, a high CLR signal from the dear-start debouncer
is differentiated to get a narrow positive spike. This resets
the counter. When the computer run begins, the counter
output is 0000 during the T x state, 0001 during the T 2 state,
and 0010 during the T 3 state. Every fetch cycle is the same
because 0000 , 0001 , and 0010 come out of the counter
during states T X9 T 2 , and T 3 .
The op code in the instruction register controls the
execution cycle. If an ADD instruction has been fetched,
the I 7 I 6 I 5 I 4 bits are 0001. These op-code bits drive the
address ROM, producing an output of 0110 (Table 10-7).
This starting address is the input to the presettable counter.
When T 3 is high, the next negative clock edge loads 0110
into the presettable counter. The counter is now preset, and
counting can resume at the starting address of the ADD
routine. The counter output is 0110 during the T A state,
0111 during the T s state, and 1000 during the T 6 state.
When the T x state begins, the leading edge of the T x
signal is differentiated to produce a narrow positive spike
which resets the counter to 0000 , the starting address of
the fetch routine. A new machine cycle then begins.
162 Digital Computer Electronics
Control ROM
The control ROM stores the SAP-1 microinstructions.
During the fetch cycle, it receives addresses 0000, 0001,
and 0010. Therefore, its outputs are
5E3H
BE3H
263H
These microinstructions, listed in Table 10-6, produce the
address state, increment state, and memory state.
If an ADD instruction is being executed, the control
ROM receives addresses 0110, 0111, and 1000 during the
execution cycle. Its outputs are
1A3H
2E1H
3C7H
These microinstructions carry out the addition as previously
discussed.
For another example, suppose the OUT instruction is
being executed. Then the op code is 1110 and the starting
address is 1100 (Table 10-7). During the execution cycle,
the counter output is 1100, 1101, and 1110. The output of
the control ROM is 3F2H, 3E3H, and 3E3H (Table 10-6).
This routine transfers the accumulator contents to the output
port.
Variable Machine Cycle
The microinstruction 3E3H in Table 10-6 is a nop. It occurs
once in the LDA routine and twice in the OUT routine.
These nops are used in SAP-1 to get a fixed machine cycle
for all instructions. In other words, each machine cycle
takes exactly six T states, no matter what the instruction.
In some computers a fixed machine cycle is an advantage.
But when speed is important, the nops are a waste of time
and can be eliminated.
One way to speed up the operation of SAP-1 is to skip
any T state with a nop. By redesigning the circuit of Fig.
10-16 we can eliminate the nop states. This will shorten
the machine cycle of the LDA instruction to five states (T x ,
T 2 , T 3 , r 4 , and F 5 ). It also shortens the machine cycle of
the OUT instruction to four T states (T u T 2 , T 3 , and T 4 ).
Figure 10-17 shows one way to get a variable machine
cycle. With an LDA instruction, the action is the same as
before during the T x to T 5 states. When the T 6 state begins,
the control ROM produces an output of 3E3H (the nop
microinstruction). The nand gate detects this nop instantly
and produces a low output signal NOP. NOP is fed back
to the ring counter through an and gate, as shown in Fig.
10-18. This resets the ring counter to the T } state, and a
new machine cycle begins. This reduces the machine cycle
of the LDA instruction from six states to five.
Microinstruction
Fig. 10-17 Variable machine cycle.
Fig. 10-18
With the OUT instruction, the first nop occurs in the T 5
state. In this case, just after the T 5 state begins, the control
ROM produces an output of 3 E3H, which is detected by
the nand gate. The low NOP signal then resets the ring
counter to the T x state. In this way, we have reduced the
machine cycle of the OUT instruction from six states to
four.
Chapter 10 SAP-1 163
Variable machine cycles are commonly used with micro¬
processors. In the 8085, for example, the machine cycles
take from two to six T states because all unwanted nop
states are ignored.
Advantages
One advantage of microprogramming is the elimination of
the instruction decoder and control matrix; both of these
become very complicated for larger instruction sets. In
other words, it’s a lot easier to store microinstructions in a
ROM than it is to wire an instruction decoder and control
matrix.
Furthermore, once you wire an instruction decoder and
control matrix, the only way you can change the instruction
set is by disconnecting and rewiring. This is not necessary
with microprogrammed control; all you have to do is change
the control ROM and the starting-address ROM. This is a
big advantage if you are trying to upgrade equipment sold
earlier.
Summary
In conclusion, most modem microprocessors use micropro¬
grammed control instead of hardwired control. The micro¬
programming tables and circuits are more complicated than
those for SAP-1, but the idea is the same. Microinstructions
are stored in a control ROM and accessed by applying the
address of the desired microinstruction.
GLOSSARY
address state The T x state. During this state, the address
in the program counter is transferred to the MAR.
accumulator The place where answers to arithmetic and
logic operations are accumulated. Sometimes called the A
register.
assembly language The mnemonics used in writing a
program.
B register An auxiliary register that stores the data to be
added or subtracted from the accumulator.
fetch cycle The first part of the instruction cycle. During
the fetch cycle, the address is sent to the memory, the
program counter is incremented, and the instruction is
transferred from the memory to the instruction register.
increment state The T 2 state. During this state, the pro¬
gram counter is incremented.
instruction cycle All the states needed to fetch and execute
an instruction.
instruction register The register that receives the instruc¬
tion from the memory.
instruction set The instructions a computer responds to.
LDA Mnemonic for load the accumulator.
machine cycle All the states generated by the ring counter.
machine language The strings of Os and Is used in a
program.
macroinstruction One of the instructions in the instruction
set.
MAR Memory address register. This register receives the
address of the data to be accessed in memory. The MAR
supplies this address to the memory.
memory-reference instruction An instruction that calls
for a second memory operation to access data.
memory state The T 3 state. During this state, the instruc¬
tion in the memory is transferred to the instruction register.
microinstruction . A control word out of the controller-
sequencer. The smallest step in the data processing.
nop No operation. A state during which nothing happens.
output register The register that receives processed data
from the accumulator and drives the output display of SAP-
1. Also called an output port.
object program A program written in machine language.
op code Operation code. That part of the instruction which
tells the computer what operation to perform.
program counter A register that counts in binary. Its
contents are the address of the next instruction to be fetched
from the memory.
RAM Random-access memory. A better name is read-
write memory. The RAM stores the program and data
needed for a computer run.
source program A program written in mnemonics.
SELF-TESTING REVIEW
Read each of the following and provide the missing words
Answers appear at the beginning of the next question.
1. The_counter, which is part of the con¬
trol unit, counts from 0000 to 1111. It sends to the
memory the_of the next instruction.
2. (program , address) The MAR, or_reg¬
ister, latches the address from the program counter.
A bit later, the MAR applies this address to the
_, where a read operation is performed.
3. (memory-address, RAM ) The instruction register is
164 Digital Computer Electronics
part of the control unit. The contents of the
-register are split into two nibbles. The
upper nibble goes to the_
4. ( instruction, controller-sequencer) The controller-
sequencer produces a 12-bit word that controls the
rest of the computer. The 12 wires carrying this
_word are called the control
5. ( control , bus) The_is a buffer register
that stores sums or differences. Its two-state output
goes to the adder-subtracter. The_pro¬
duces the sum when S v is low and the difference
when S v is high. The output register is sometimes
called an output_
6. (- accumulator, adder-subtracter , port) The SAP-1
_set is LDA, ADD, SUB, OUT, and
HLT. LDA, ADD, and SUB are called_
instructions because they use data stored in the
memory.
7. ( instruction , memory-reference) The 8080 was the
first widely used microprocessor. The_is
an enhanced version of the 8080 with essentially the
same instruction set.
8. (8085) LDA, ADD, SUB, OUT, and HLT are
coded as 4-bit strings of Os and Is. This code is
called the_code. _language
uses mnemonics when writing a program._
language uses strings of Os and Is.
9. ( op , Assembly , Machine) SAP-1 has_ T
states, periods during which register contents
change. The ring counter, or_counter,
produces these T states. These six T states represent
one machine cycle. In SAP-1 the instruction cycle
has only one machine cycle. In microprocessors like
the 8080 and the 8085, the_cycle may
have from one to five machine cycles.
10. (six, state , instruction) The controller-sequencer
sends out control words, one during each T state
or clock cycle. Each control word is called a
_Instructions like LDA, ADD, SUB,
etc. are called_Each SAP-1 macroin¬
struction is made up of three_
11 . ( microinstruction , macroinstructions , microinstruc¬
tions) With larger instruction sets, the control ma¬
trix becomes very complicated. This is why hard¬
wired control is being replaced by_The
basic idea is to store the_in a control
ROM.
12. ( microprogramming , microinstructions) SAP-1 uses
a fixed machine cycle for all instructions. In other
words, each machine cycle takes exactly six T
states. Microprocessors like the 8085 have variable
machine cycles because all unwanted nop states are
eliminated.
PROBLEMS
10-1. Write a SAP-1 program using mnemonics (simi¬
lar to Example 10-1) that will display the result
of
5 + 4-6
Use addresses DH, EH, and FH for the data.
10-2. Convert the assembly language of Prob. 10-1
into SAP-1 machine language. Show the answer
in binary form and in hexadecimal form.
10-3. Write an assembly-language program that per¬
forms this operation:
8 + 4 — 3 + 5- 2
Use addresses BH to FH for the data.
10-4. Convert the program and data of Prob. 10-3 into
machine language. Express the result in both
binary and hexadecimal form.
10-5. Figure 10-19 shows the timing diagram for the
ADD instruction. Draw the timing diagram for
the SUB instruction.
b+-■ r >+• r =+- + r * +-H
“LT1
i
l
_m
i
i
LTU
1
i
ru
ru
n
i
i
u
i
i
ru
i
1
~L2J
i
1 L
- 1 "
L
""L-
j
r
L
i
i
i i
i i
Li
Li
j
j
r
“L
n
L
_r
Fig. 10-19
Chapter 10 SAP-1 165
C5 2 TO 1
74LS157 MULTIPLEXER
A S+
Fig. 10-20
W bus
Fig. 10-21
CLEAR/
START
r
SINGLE
STEP
MANUAL/
AUTO
5
9
> LOW
l_10
> HIGH
f V2
13
1
> MANUAL
> AUTO
r^T
+5 V O-
36 kil ’
L?——Tc25\>—■
CLOCK
BUFFERS
11 I 5|V^ 6
CLOCK
CIRCUIT
C28
6 NE555 5
vlH_
/ w
_Li — N
C26 1
- >
HLT
10 ^
1
3
O- j
Q -
12 _<] C29
4
- K
Q
2 1
0.01 F ]
0.01 juP
POWER
SUPPLY
C30
1000/iF LM 340-5
Fig. 10-22
170 Digital Computer Electronics
RING COUNTER
Fig. 10-23
10 - 6 . Suppose an 8085 uses a clock frequency of 3
MHz. The ADD instruction of an 8085 takes
four T states to fetch and execute. How long is
this?
10 - 7 . What are the SAP-1 microinstructions for the
LDA routine? For the SUB routine? Express the
answers in binary and hexadecimal form.
10 - 8 . Suppose we want to transfer the contents of the
accumulator to the B register. This requires a
new microinstruction. What is this microinstruc¬
tion? Express your answer in hexadecimal and
binary form.
10 - 9 . Look at Fig. 10-20 and answer the following
questions:
a. Are the contents of the program counter
changed on the positive or negative edge of
the CLK signal? At this instant, is the CLK
signal on its rising or falling edge?
b. To increment the program counter, does C P
have to be low or high?
c. To clear the program counter, does CLR have
to be low or high?
d. To place the contents of the program counter
on the W bus, should E P be low or high?
10 - 10 . Refer to Fig. 10-21:
a. If L a is high, what happens to the accumulator
contents on the next positive clock edge?
b. If A = 0010 1100 and B = 1100 1110, what
is on the W bus if E A is high?
c. If A = 0000 1111, B = 0000 0001, and
Su — 1, what is on the W bus when E v is
high?
10 - 11 . Answer the following questions for Fig. 10-22:
a. With S 5 in the clear position, is the CLR
output low or high?
b. With S 6 in the low position, is the output low
or high for pin 11, C24?
c. To have a clock signal at pin 3 of C29, should
HLT be low or high?
10 - 12 . Refer to Fig. 10-23 to answer the following:
a. If I 7 I 6 I 5 I 4 = 1110, only one of the output pins
in C35 is high. Which pin is this? (Disregard
pins 10 and 12.)
b. CLR goes low. Which is the timing signal {T x
to T 6 ) that goes high?
c. LDA and T 5 are high. Is the voltage low or
high at pin 6, C45?
d. ADD and T A are high. Is the signal low or
high at pin 12, C45?
172 Digital Computer Electronics
SAP-2
SAP-1 is a computer because it stores a program and data
before calculations begin; then it automatically carries out
the program instructions without human intervention. And
yet, SAP-1 is a primitive computing machine. It compares
to a modem computer the way a Neanderthal human would
compare to a modem person. Something is missing, some¬
thing found in every modem computer.
SAP-2 is the next step in the evolution toward modem
computers because it includes jump instructions. These new
instructions force the computer to repeat or skip part of a
program. As you will discover, jump instructions open up
a whole new world of computing power.
11-1 BIDIRECTIONAL REGISTERS
To reduce the wiring capacitance of SAP-2, we will run
only one set of wires between each register and the bus.
Figure 11-1 a shows the idea. The input and output pins are
shorted; only one group of wires is connected to the bus.
Does this shorting the input and output pins ever cause
trouble? No. During a computer run, either LOAD or
ENABLE may be active, but not both at the same time. An
active LOAD means that a binary word flows from the bus
to the register input; during a load operation, the output
lines are floating. On the other hand, an active ENABLE
means that a binary word flows from the register to the
bus; in this case, the input lines float.
The IC manufacturer can internally connect the input and
output pins of a three-state register. This not only reduces
the wiring capacitance; it also reduces the number of I/O
pins. For instance, Fig. 11-1 b has four I/O pins instead of
eight.
Figure 11-lc is the symbol for a three-state register with
internally connected input and output pins. The double¬
headed arrow reminds us that the path is bidirectional ; data
can move either way.
11-2 ARCHITECTURE
Figure 11-2 shows the architecture of SAP-2. All register
outputs to the W bus are three-state; those not connected
to the bus are two-state. As before, the controller-sequencer
sends control signals (not shown) to each register. These
control signals load, enable, or otherwise prepare the register
for the next positive clock edge. A brief description of each
box is given now.
Input Ports
SAP-2 has two input ports, numbered 1 and 2. A hexade¬
cimal keyboard encoder is connected to port 1. It allows
us to enter hexadecimal instructions and data through port
1. Notice that the hexadecimal keyboard encoder sends a
READY signal to bit 0 of port 2. This signal indicates when
the data in port 1 is valid.
Also notice the SERIAL IN signal going to pin 7 of port
2. A later example will show you how to convert serial
input data to parallel data.
Program Counter
This time, the program counter has 16 bits; therefore, it
can count from
PC = 0000 0000 0000 0000
to
pc = mi mi nil nil
This is equivalent to 0000H to FFFFH, or decimal 0 to
65,535. _
A low CLR signal resets the PC before each computer
run; so the data processing starts with the instruction stored
in memory location 0000H.
173
Bus
MAR and Memory
During the fetch cycle, the MAR receives 16-bit addresses
from the program counter. The two-state MAR output then
addresses the desired memory location. The memory has a
2K ROM with addresses of 0000H to 07FFH. This ROM
contains a program called a monitor that initializes the
computer on power-up, interprets the keyboard inputs, and
so forth. The rest of the memory is a 62K RAM with
addresses from 0800H to FFFFH.
Memory Data Register
The memory data register (MDR) is an 8-bit buffer register.
Its output sets up the RAM. The memory data register
receives data from the bus before a write operation, and it
sends data to the bus after a read operation.
Instruction Register
Because SAP-2 has more instructions than SAP-1, we will
use 8 bits for the op code rather than 4. An 8-bit op code
can accommodate 256 instructions. SAP-2 has only 42
174 Digital Computer Electronics
instructions, so there will be no problem coding them with
8 bits. Using an 8-bit op code also allows upward compat¬
ibility with the 8080/8085 instruction set because it is based
on an 8-bit op code. As mentioned earlier, all SAP
instructions are identical with 8080/8085 instructions.
Controller-Sequencer
The controller-sequencer produces the control words or
microinstructions that coordinate and direct the rest of the
computer. Because SAP-2 has a bigger instruction set, the
controller-sequencer has more hardware. Although the CON
word is bigger, the idea is the same: the control word or
microinstruction determines how the registers react to the
next positive clock edge.
Accumulator
The two-state output of the accumulator goes to the ALU;
the three-state output to the W bus. Therefore, the 8-bit
word in the accumulator continuously drives the ALU, but
this same word appears on the bus only when E A is active.
W bus
ACKNOWLEDGE
READY
SERIAL IN ■
Fig. 11-2 SAP-2 block architecture.
Input
port
2
PC
MAR
\^6|
V
64 K
Memory
TV
JjL
MDR
IR
V 7
CON
Hexadecimal
keyboard
encoder
\
8
/
V
8 N
>
/
8-^
-T 1
16
o
■N
z_
M-
16
~A
Controller/
sequencer
25
ACCUMULATOR
■
pi
ALU
\
ABHI
2
1
/
■
3KK
TMP
\ Z
vV
B
/ \
00
C
FLAGS
Output
\
port
8 >
3
0
7
•
vl
Hexadecimal
display
SERIAL OUT
■ ACKNOWLEDGE
ALU and Flags
Standard ALUs are commercially available as integrated
circuits. These ALUs have 4 or more control bits that
determine the arithmetic or logic operation performed on
words A and B. The ALU used in SAP-2 includes arithmetic
and logic operations.
In this book a flag is a flip-flop that keeps track of a
changing condition during a computer run. The SAP-2
computer has two flags. The sign flag is set when the
accumulator contents become negative during the execution
of some instructions. The zero flag is set when the accu¬
mulator contents become zero.
TMP, B, and C Registers
Instead of using the B register to hold the data being added
or subtracted from the accumulator, a temporary (TMP)
register is used. This allows us more freedom in using the
B register. Besides the TMP and B registers, SAP-2 includes
a C register. This gives us more flexibility in moving data
during a computer run.
Chapter 11 SAP-2 175
Output Ports
SAP-2 has two output ports, numbered 3 and 4. The
contents of the accumulator can be loaded into port 3,
which drives a hexadecimal display. This allows us to see
the processed data.
The contents of the accumulator can also be sent to port
4. Notice that pin 7 of port 4 sends an ACKNOWLEDGE
signal to the hexadecimal encoder. This ACKNOWLEDGE
signal and the READY signal are part of a concept called
handshaking, to be discussed later.
Also notice the SERIAL OUT signal from pin 0 of port
4; one of the examples will show you how to convert
parallel data in the accumulator into serial output data.
11-3 MEMORY-REFERENCE
INSTRUCTIONS
The SAP-2 fetch cycle is the same as before. T, is the
address state, T 2 is the increment state, and T 3 is the memory
state. All SAP-2 instructions therefore use the memory
during the fetch cycle because a program instruction is
transferred from the memory to the instruction register.
During the execution cycle, however, the memory may
or may not be used; it depends on the type of instruction
that has been fetched. A memory-reference instruction
(MRI) is one that uses the memory during the execution
cycle.
The SAP-2 computer has an instruction set with 42
instructions. What follows is a description of the memory-
reference instructions.
LDA and STA
LDA has the same meaning as before: load the accumulator
with the addressed memory data. The only difference is
that more memory locations can be accessed in SAP-2
because the addresses are from 0000H to FFFFH. For
example, LDA 2000H means to load the accumulator with
the contents of memory location 2000H.
To distinguish the different parts of an instruction, the
mnemonic is sometimes called the op code and the rest of
the instruction is known as the operand. With LDA 2000H,
LDA is the op code and 2000H is the operand. Therefore,
“op code” has a double meaning in microprocessor work;
it may stand for the mnemonic or for the binary code used
to represent the mnemonic. The intended meaning is clear
from the context.
STA is a mnemonic for store the accumulator . Every
STA instruction needs an address. STA 7FFFH means to
store the accumulator contents at memory location 7FFFH.
the execution of STA 7FFFH stores BAH at address 7FFFH.
MVI
MVI is the mnemonic for move immediate. It tells the
computer to load a designated register with the byte that
immediately follows the op code. For instance,
MVI A,37H
tells the computer to load the accumulator with 37H. After
this instruction has been executed, the binary contents of
the accumulator are
A = 0011 0111
You can use MVI with the A, B, and C registers. The
formats for these instructions are
MVI A,byte
MVI B,byte
MVI C,byte
Op Codes
Table 11-1 shows the op codes for the SAP-2 instruction
set. These are the 8080/8085 op codes. As you can see,
3A is the op code for LDA, 32 is the op code for STA,
etc. Refer to this table in the remainder of this chapter.
EXAMPLE 11-1
Show the mnemonics for a program that loads the accu¬
mulator with 49H, the B register with 4AH, and the C
register with 4BH; then have the program store the accu¬
mulator data at memory location 6285H.
SOLUTION
Here’s one program that will work:
Mnemonics
MVI A,49H
MVI B,4AH
MVI C,4BH
STA 6285H
HLT
The first three instructions load 49H, 4AH, and 4BH into
the A, B, and C registers. STA 6285H stores the accumulator
contents at 6285H.
Note the use of HLT in this program. It has the same
meaning as before: halt the data processing.
176 Digital Computer Electronics
TABLE 11-1. SAP-2 OP CODES
Instruction
Op Code
Instruction
Op Code
ADD B
80
MOV B,A
47
ADD C
81
MOV B,C
41
ANA B
A0
MOV C,A
4F
ANA C
A1
MOV C,B
48
ANI byte
E6
MVI A,byte
3E
CALL address
CD
MVI B,byte
06
CMA
2F
MVI C,byte
0E
DCR A
3D
NOP
00
DCR B
05
ORA B
B0
DCR C
0D
ORA C
B1
HLT
76
ORI byte
F6
IN byte
DB
OUT byte
D3
INR A
3C
RAL
17
INR B
04
RAR
IF
INR C
OC
RET
C9
JM address
FA
STA address
32
JMP address
C3
SUB B
90
JNZ address
C2
SUB C
91
JZ address
CA
XRA B
A8
LDA address
3A
XRA C
A9
MOV A,B
78
XRI byte
EE
MOV A,C
79
instruction, notice that the op code goes into the first address
and the byte into the second address. This is true of all 2-
byte instructions: op code into the first available memory
location and byte into the next.
The instruction
STA 6285H
is a 3-byte instruction (1 byte for the op code and 2 for the
address). The op code for STA is 32H. This byte goes into
the first available memory location, which is 2006H. The
address 6285H has 2 bytes. The lower byte 85H goes into
the next memory location, and the upper byte 62H into the
next location.
Why does the address get programmed with the lower
byte first and the upper byte second? This is a peculiarity
of the original 8080 design. To keep upward compatibility,
the 8085 and some other microprocessors use the same
scheme: lower byte into lower memory, upper byte into
upper memory.
The last instruction HLT has an op code of 76H, stored
in memory location 2009H.
In summary, the MVI instructions are 2-byte instructions,
the STA is a 3-byte instruction, and the HLT is a 1-byte
instruction.
11-4 REGISTER INSTRUCTIONS
EXAMPLE 11-2
Translate the foregoing program into 8080/8085 machine
language using the op codes of Table 11-1. Start with
address 2000H.
SOLUTION
Memory-reference instructions are relatively slow because
they require more than one memory access during the
instruction cycle. Furthermore, we often want to move data
directly from one register to another without having to go
through the memory. What follows are some of the SAP-
2 register instructions, designed to move data from one
register to another in the shortest possible time.
Address
Contents
Symbolic
MOV
2000H
3EH
MVI A,49H
MOV is the mnemonic for move. It tells the computer to
2001H
49H
move data from one register to another. For instance,
2002H
06H
MVI B,4AH
2003H
4AH
MOV A,B
2004H
0EH
MVI C,4BH
2005H
4BH
tells the computer to move the data in the B register to the
2006H
32H
STA 6285H
accumulator. The operation is nondestructive, meaning that
2007H
85H
the data in B is copied but not erased. For example, if
2008H
62H
2009H
76H
HLT
A = 34H and B= 9DH
There are a couple of new ideas in this machine-language
program. With the
MVI A,49H
then the execution of MOV A,B results in
A = 9DH
B = 9DH
Chapter 11 SAP-2 177
You can move data between the A, B, and C registers.
The formats for all MOV instructions are
MOV A,B
MOV A,C
MOV B,A
MOV B,C
MOVC,A
MOV C,B
These instructions are the fastest in the SAP-2 instruction
set, requiring only one machine cycle.
ADD and SUB
ADD stands for add the data in the designated register to
the accumulator. For instance,
ADD B
means to add the contents of the B register to the accu¬
mulator. If
A = 04H and B= 02H
then the execution of ADD B results in
A = 06H
Similarly, SUB means subtract the data in the designated
register from the accumulator. SUB C will subtract the
contents of the C register from the accumulator.
The formats for the ADD and SUB instructions are
ADD B
ADD C
SUBB
SUB C
INR and DCR
Many times we want to increment or decrement the contents
of one of the registers. INR is the mnemonic for increment;
it tells the computer to increment the designated register.
DCR is the mnemonic for decrement, and it instructs the
computer to decrement the designated register. The formats
for these instructions are
INR A
INR B
INR C
DCR A
DCR B
DCR C
As an example, if
B = 56H and C = 8AH
then the execution of INR B results in
B= 57H
and the execution of a DCR C produces
C = 89H
EXAMPLE 11-3
Show the mnemonics for adding decimal 23 and 45. The
answer is to be stored at memory location 5600H. Also,
the answer incremented by 1 is to be stored in the C register.
SOLUTION
As shown in Appendix 2, decimal 23 and 45 are equivalent
to 17H and 2DH. Here is a program that will do the job:
Mnemonics
MVI A,17H
MVI B,2DH
ADD B
STA 5600H
INR A
MOVC, A
HLT
EXAMPLE 11-4
To hand-assemble a program means to translate a source
program into a machine-language program by hand rather
than machine. Hand-assemble the program of the preceding
example starting at address 2000H.
SOLUTION
Address
Contents
Symbolic
2000H
3EH
MVI A,17H
2001H
17H
2002H
06H
MVI B,2DH
2003H
2DH
2004H
80H
ADD B
2005 H
32H
STA 5600H
2006H
00H
2007H
56H
2008H
3CH
INR A
2009H
4FH
MOV C,A
200AH
76H
HLT
Notice that the ADD, INR, MOV, and HLT instructions
are 1-byte instructions; the MVI instructions are 2-byte
instructions, and the STA is a 3-byte instruction.
178 Digital Computer Electronics
11-5 JUMP AND CALL
INSTRUCTIONS
SAP-2 has four jump instructions; these can change the
program sequence. In other words, instead of fetching the
next instruction in the usual way, the computer may jump
or branch to another part of the program.
JMP
To begin with, JMP is the mnemonic for jump; it tells the
computer to get the next instruction from the designated
memory location. Every JMP instruction includes an address
that is loaded into the program counter. For instance,
JMP 3000H
tells the computer to get the next instruction from memory
location 3000H.
2000H - 2000H
negative, the sign flag will be set; otherwise, the sign flag
is cleared. Symbolically,
0 if A ^ 0
1 if A < 0
where 5 stands for sign flag. The sign flag will remain set
or clear until another operation that affects the flag.
JM is a mnemonic for jump if minus; the computer will
jump to a designated address if and only if the sign flag is
set. As an example, suppose a JM 3000H is stored at
2005H. After this instruction has been fetched,
PC = 2006H
If S = 1, the execution of JM 3000H loads the program
counter with
PC = 3000H
Since the program counter now points to 3000H, the next
instruction will come from 3000H.
If the jump condition is not met (5 = 0), the program
counter is unchanged during the execution cycle. Therefore,
when the next fetch cycle begins, the instruction is fetched
from 2006H.
Figure 11-3b symbolizes the two possibilities for a JM
instruction. If the minus condition is satisfied, the computer
jumps to 3000H for the next instruction. If the minus
condition is not satisfied, the program falls through to the
next instruction.
(a) (b)
Fig. 11-3 {a) Unconditional jump; (b) conditional jump.
Here is what happens. Suppose JMP 3000H is stored at
2005H, as shown in Fig. 11-3 a. At the end of the fetch
cycle, the program counter contains
PC = 2006H
During the execution cycle, the JMP 3000H loads the
program counter with the designated address:
PC = 3000H
When the next fetch cycle begins, the next instruction
comes from 3000H rather than 2006H (see Fig. 11-3a).
JM
SAP-2 has two flags called the sign flag and the zero flag.
During the execution of some instructions, these flags will
be set or reset, depending on what happens to the accu¬
mulator contents. If the accumulator contents become
JZ
The other flag affected by accumulator operations is the
zero flag. During the execution of some instructions, the
accumulator will become zero. To record this event, the
zero flag is set; if the accumulator contents do not go to
zero, the zero flag is reset. Symbolically,
^ _ f 0 when A ^ 0
| 1 when A = 0
JZ is the mnemonic for jump if zero; it tells the computer
to jump to the designated address only if the zero flag is
set. Suppose a JZ 3000H is stored at 2005H. If Z = 1
during the exection of JZ 3000H, the next instruction is
fetched from 3000H. On the other hand, if Z = 0, the next
instruction will come from 2006H.
JNZ
JNZ stands for jump if not zero. In this case, we get a jump
when the zero flag is clear and no jump when it is set.
Suppose a JNZ 7800H is stored at 2100H. If Z = 0, the
next instruction will come from 7800H; however, if Z =
1, the program falls through to the instruction at 2101H.
Chapter 11 SAP-2 179
JM, JZ, and JNZ are called conditional jumps because
the program jump occurs only if certain conditions are
satisfied. On the other hand, JMP is unconditional ; once
this instruction is fetched, the execution cycle always jumps
the program to the specified address.
CALL and RET
A subroutine is a program stored in the memory for possible
use in another program. Many microcomputers have sub¬
routines for finding sines, cosines, tangents, logarithms,
square roots, etc. These subroutines are part of the software
supplied with the computer.
CALL is the mnemonic for call the subroutine. Every
CALL instruction must include the starting address of the
desired subroutine. For instance, if a square-root subroutine
starts at address 5000H and a logarithm subroutine at
6000H, the execution of
CALL 5000H
will jump to the square-root subroutine. On the other hand,
a
CALL 6000H
produces a jump to the logarithm subroutine.
RET stands for return. It is used at the end of every
subroutine to tell the computer to go back to the original
program. A RET instruction is to a subroutine as a HLT is
to a program. Both tell the computer that something is
finished. If you forget to use a RET at the end of a
subroutine, the computer cannot get back to the original
program and you will get computer trash.
When a CALL is executed in the SAP-2 computer, the
contents of the program counter are automatically saved in
memory locations FFFEH and FFFFH (the last two memory
locations). The CALL address is then loaded into the
program counter, so that execution begins with the first
instruction in the subroutine. After the subroutine is finished,
the RET instruction causes the address in memory locations
FFFEH and FFFFH to be loaded back into the program
counter. This returns control to the original program.
Figure 11-4 shows the program flow during a subroutine.
The CALL 5000H sends the computer to the subroutine
located at 5000H. After this subroutine has been completed,
the RET sends the computer back to the instruction following
the CALL.
CALL is unconditional, like JMP. Once a CALL has
been fetched into the instruction register, the computer will
jump to the starting address of the subroutine.
More on Flags
The sign or zero flag may be set or reset during certain
instructions. Table 11-2 lists the SAP-2 instructions that
can affect the flags. All these instructions use the accu¬
mulator during the execution cycle. If the accumulator goes
negative or zero while one of these instructions is being
executed, the sign or zero flag will be set.
For instance, suppose the instruction is ADD C. The
contents of the C register are added to the accumulator
contents. If the accumulator contents become negative or
zero in the process, the sign or zero flag will be set.
A word about the INR and DCR instructions. Since these
instructions use the accumulator to add or subtract 1 from
the designated register, they also affect the flags. For
instance, to execute a DCR C, the contents of the C register
are decremented by sending these contents to the accumu¬
lator, subtracting 1, and sending the result back to the C
register. If the accumulator goes negative while the DCR
C is executed, the sign flag is set; if the accumulator goes
to zero, the zero flag is set.
TABLE 11-2. INSTRUCTIONS
AFFECTING FLAGS
CALL 5000H -1
5000H
RET - 1
Fig. 11-4 CALL instruction.
Instruction Flags Affected
ADD
S, Z
SUB
S, Z
INR
s, z
DCR
s, z
ANA
s, z
ORA
s, z
XRA
s, z
ANI
s, z
ORI
s, z
XRI
s, z
X 80 Digital Computer Electronics
EXAMPLE 11-5
Hand-assemble the following program starting at address
2000H:
MVI C,03H
DCRC
JZ 0009H
JMP 0002H
HLT
SOLUTION
Address
Contents
Symbolic
2000H
OEH
MVI C,03H
2001H
03 H
2002H
0DH
DCR C
2003H
CAH
JZ 2009H
2004H
09H
2005H
20H
2006H
C3H
JMP 2002H
2007H
02H
2008H
20H
2009H
76H
HLT
EXAMPLE 11-6
In the foregoing program, how many times is the DCR
instruction executed?
2000H: MVI C, 03H
2002H: DCR C -
Three
passes
through
loop v
2003H: JZ 2009H -
2006H: JMP 2002H -
2009H: HLT -
Fig. 11-5 Looping.
the computer will loop 7 times. Similarly, if we wanted to
pass through the loop 200 times (equivalent to C8H), the
first instruction would be
MVI C,C8H
The C register acts like a presettable down counter. This
is why it is sometimes referred to as a counter .
The point to remember is this. We can set up a loop by
using an MVI, DCR, JZ, and JMP in a program. The
number loaded into the designated register (the counter)
determines the number of passes through the loop. If we
put new instructions inside the loop, these added instructions
will be executed X times, the number preset into the counter.
SOLUTION
EXAMPLE 11-7
Figure 11-5 illustrates the program flow. Here is what
happens. The MVI C,03H instruction loads the C register
with 03H. DCR C reduces the contents to 02H. The contents
are greater than zero; therefore, the zero flag is reset, and
the JZ 2009H is ignored. The JMP 2002H returns the
computer to the DCR C instruction.
The second time the DCR C is executed, the contents
drop to 01H; the zero flag is still reset. JZ 2009H is again
ignored, and the JMP 2002H returns the computer to DCR
C.
The third DCR C reduces the contents to zero. This time
the zero flag is set, and the JZ 2009H jumps the program
to HLT instruction.
A loop is part of a program that is repeated. In this
example, we have passed through the loop (DCR C and JZ
2009H) 3 times, as shown in Fig. 11-5. Note that the
number of passes through the loop equals the number
initially loaded into the C register. If we change the first
instruction to
MVI C,07H
When you buy a microcomputer, you often purchase
software to do different jobs. One of the programs you can
buy is an assembler. The assembler allows you to write
programs in mnemonic form. Then the assembler converts
these mnemonics into machine language. In other words,
if you have an assembler, you no longer have to hand-
assemble your programs; the computer does the work for
you.
Show the assembly-language version of the program in
Example 11-5. Include labels and comments.
SOLUTION
Label Instruction
MVI C,03H
REPEAT: DCRC
JZ END
JMP REPEAT
END: HLT
Comment
;Load counter with decimal.3
;Decrement counter
;Test for zero
;Do it again
Chapter 11 SAP-2 181
When you write a program, it helps to include your own
comments about what the instruction is supposed to do.
These comments jog your memory if you have to read the
program months later. The first comment reminds us that
we are presetting the down counter with decimal 3, the
second comment reminds us that we are decrementing the
counter, the third comment tells us that we are testing for
zero before jumping, and the fourth comment tells us that
the program will loop back.
When the assembler converts your source program into
an object program, it ignores everything after the semicolon.
Why? Because that’s the way the assembler program is
written. The semicolon is a coded way to tell the computer
that your personal comments follow. (Remember the ASCII
code. 3BH is the ASCII for a semicolon. When the assembler
encounters 3BH in your source programs, it knows com¬
ments follow.)
Labels are another programming aid used with jumps
and calls. When we write an assembly-language program,
we often have no idea what address to use in a jump or
call instruction. By using a label instead of a numerical
address we can write programs that make sense to us. The
assembler will keep track of our labels and automatically
assign the correct addresses to them. This is a great
laborsaving feature of an assembler.
For instance, when the assembler converts the foregoing
program to machine language, it will replace JZ by CA (op
code of Table 11-1) and END by the address of the HLT
instruction. Likewise, it will replace JMP by C3 (op code)
and REPEAT by the address of the DCR C instruction.
The assembler determines the addresses of the HLT and
JMP by counting the number of bytes needed by all
instructions and figuring out where the HLT and DCR C
instructions will be in the final assembled program.
All you have to remember is that you can make up any
label you want for jump and call instructions. The same
label followed by a colon is placed in front of the instruction
you are trying to jump to. When the assembler converts
your program into machine language, the colon tells it a
label is involved.
One more point about labels. With SAP-2, the labels can
be from one to six characters, the first of which must be a
letter. Labels are usually words or abbreviations, but
numbers can be included. The following are examples of
acceptable labels:
REPEAT
DELAY
RDKBD
A34
B12C3
The first two are words; the third is an abbreviation for
read the keyboard. The last two are labels that include
numbers. The restrictions on length (no more than six
characters) and starting character (must be letter) are typical
of commercially available assemblers.
EXAMPLE 11-8
Show a program that multiplies decimal 12 and 8.
SOLUTION
The hexadecimal equivalents of 12 and 8 are OCH and
08H. Let us set up a loop that adds 12 to the accumulator
during each pass. If the computer loops 8 times, the
accumulator contents will equal 96 (decimal) at the end of
the looping.
Here’s one assembly-language program that will do the
job:
Label
Mnemonic
Comment
MVI A,00H
; Cl ear accumulator
MVI B,0CH
;Load decimal 12 into I
MVI C,08H
;Preset counter with 8
REPEAT:
ADD B
;Add decimal 12
DCR C
;Decrement the counter
JZ DONE
;Test for zero
JMP REPEAT
;Do it again
DONE:
HLT
;Stop it
The comments tell most of the story. First, we clear the
accumulator. Next, we load decimal 12 into the B register.
Then the counter is preset to decimal 8. These first three
instructions are part of the initialization before entering a
loop.
The ADD B begins the loop by adding decimal 12 to
accumulator. The DCR C reduces the count to 7. Since the
zero flag is clear, JZ DONE is ignored the first time through
and the program flow returns to the ADD B instruction.
You should be able to see what will happen. ADD B is
inside the loop and will be executed 8 times. After eight
passes through the loop, the zero flag is set; then the JZ
DONE Will take the program out of the loop to the HLT
instruction.
Since 12 is added 8 times,
12 + 12 + 12 + 12 + 12 + 12 + 12 + 12 = 96
(Because decimal 96 is equivalent to hexadecimal 60, the
accumulator contains 0110 0000.) Repeated addition like
this is equivalent to multiplication. In other words, adding
12 eight times is identical to 12 x 8. Most microprocessors
do not have multiplication hardware; they only have an
adder-subtracter like the SAP computer. Therefore, with
the typical microprocessor, you have to use some form of
programmed multiplication such as repeated addition.
182 Digital Computer Electronics
EXAMPLE 11-9
Modify the foregoing multiply program by using a JNZ
instead of a JZ.
SOLUTION
Look at this:
Label Mnemonic
MVI A,00H
MVI B,0CH
MVI C,08H
REPEAT: ADD B
DCR C
JNZ REPEAT
HLT
Comment
;Clear accumulator
;Load decimal 12 into B
;Preset counter with 8
;Add decimal 12
;Decrement the counter
;Test for zero
;Stop it
This is simpler. It eliminates one JMP instruction and one
label. As long as the counter is greater than zero, the JNZ
will force the computer to loop back to REPEAT. When
the counter drops to zero, the program will fall through the
JNZ to the HLT.
EXAMPLE 11-10
Hand-assemble the foregoing program starting at address
2000H.
SOLUTION
Address
Contents
Symbolic
2000H
3EH
MVI A,00H
2001H
00H
2002H
06H
MVI B,0CH
2003H
0CH
2004H
OEH
MVI, C,08H
2005H
08H
2006H
80H
ADD B
2007H
0DH
DCR C
2008H
C2H
JNZ 2006H
2009H
06H
200AH
20H
200BH
76H
HLT
The first three instructions initialize the registers before the
multiplication begins. If we change the initial values, we
can multiply other numbers.
EXAMPLE 11-11
Change the multiplication part of the foregoing program
into a subroutine located at starting address F006H.
SOLUTION
Address
Contents
Symbolic
F006H
80H
ADD B
F007H
0DH
DCR C
F008H
C2H
JNZ F006H
F009H
06H
F00AH
F0H
F00BH
C9H
RET
Here’s what happened. The initializing instructions depend
on the numbers we are multiplying, so they don’t belong
in the subroutine. The subroutine should contain only the
multiplication part of the program.
In relocating the program we mapped (converted) ad¬
dresses 2006H-200BH to F006H-F00BH. Also, the HLT
was changed to a RET to get us back to the original
program.
EXAMPLE 11-12
The multiply subroutine of the preceding example is used
in the following program. What does the program do?
MVI A,00H
MVI B,10H
MVI C,0EH
CALL F006H
HLT
SOLUTION
Hexadecimal 10H is equivalent to decimal 16, and hexa¬
decimal OEH is equivalent to decimal 14. The first three
instructions clear the accumulator, load the B register with
decimal 16, and preset the counter to decimal 14. The
CALL sends the computer to the multiply subroutine of the
preceding example. When the RET is executed, the accu¬
mulator contents are EOH, which is equivalent to 224.
Incidentally, a parameter is a piece of data that the
subroutine needs to work properly. The multiply subroutine
located at F006H needs three parameters to work properly
{A, B y and C). We pass these parameters to the multiply
subroutine by clearing the accumulator, loading the B
register with the multiplicand, and presetting the C register
with the multiplier. In other words, we set A = 00H,
B = 10H, and C = OEH. Passing data to a subroutine in
this way is called register parameter passing.
Chapter 11 SAP-2 183
11-6 LOGIC INSTRUCTIONS
A microprocessor can do logic as well as arithmetic. What
follows are the SAP-2 logic instructions. Again, they are a
subset of the 8080/8085 instructions.
|xxxx]
xxxx I
1111
lilt
MM
1II1
MM
1 II 1
1 XXXX
XXXX I
Fig. 11-6 Logic instructions are bitwise.
CMA
CMA stands for “complement the accumulator.” The
execution of a CMA inverts each bit in the accumulator,
producing the l’s complement.
ANA
ANA means to and the accumulator contents with the
designated register. The result is stored in the accumulator.
For instance,
ANA B
means to and the contents of the accumulator with the
contents of the B register. The ANDing is done on a bit-by-
bit basis. For example, suppose the two registers contain
A = 1100 1100 (11-1)
and
XRA C. If the accumulator and B contents are given by
Eqs. 11-1 and 11-2, the execution of XRA B produces
SAP-2 also has immediate logic instructions. ANI means
and immediate . It tells the computer to and the accumulator
contents with the byte that immediately follows the op code.
For instance, if
A = 0101 1110
the execution of ANI C7H will and
01011110 with 1100 0111
to produce new accumulator contents of
A = 0100 0110
B = 1111 0001 (11-2) ORI
The execution of an ANA B results in
A = 1100 0000
Notice that the ANDing is bitwise, as illustrated in Fig.
11-6. The ANDing is done on pairs of bits; A 7 is ANDed
with B 7 , A 6 with B 6 , A 5 with B 5 , and so on, with the result
stored in the accumulator.
Two ANA instructions are available in SAP-2: ANA B
and ANA C. Table 11-1 shows the op codes.
ORI is the mnemonic for or immediate. The accumulator
contents are ORed with the byte that follows the op code.
If
A = 0011 1000
the execution of ORI 5AH will or
0011 1000 with 0101 1010
to produce new accumulator contents of
ORA
0111 1010
ORA is the mnemonic for or the accumulator with the
designated register. The two ORA instructions in SAP-2
are ORA B and ORA C. As an example, if the accumulator
and B register contents are given by Eqs. 11-1 and 11-2,
then executing ORA B gives
XRI
XRI means XOR immediate. If
A = 0001 1100
A = 1111 1101
the execution of XRI D4H will xor
0001 1100 with 11010100
XRA
to produce
XRA means xor the accumulator with the designated
register. The SAP-2 instruction set contains XRA B and A= 1100 1000
184 Digital Computer Electronics
11-7 OTHER INSTRUCTIONS
This section looks at the last of the SAP-2 instructions.
Since these instructions don’t fit any particular category,
they are being collected here in a miscellaneous group.
NOP
NOP stands for no operation. During the execution of a
NOP, all T states are do nothings. Therefore, no register
changes occur during a NOP.
The NOP instruction is used to waste time. It takes four
T states to fetch and execute the NOP instruction. By
repeating a NOP a number of times, we can delay the data
processing, which is useful in timing operations. For
instance, if we put a NOP inside a loop and execute it 100
times, we create a time delay of 400 T states.
HLT
We have already used this. HLT stands for halt. It ends
the data processing.
IN
IN is the mnemonic for input. It tells the computer to
transfer data from the designated port to the accumulator.
Since there are two input ports, you have to designate which
one is being used. The format for an input operation is
IN byte
For instance,
IN 02H
means to transfer the data in port 2 to the accumulator.
OUT
OUT stands for output. When this instruction is executed,
the accumulator word is loaded into the designated output
port. The format for this instruction is
OUT byte
Since the output ports are numbered 3 and 4 (Fig. 11-2),
you have to specify which port is to be used. For instance,
OUT 03H
will transfer the contents of the accumulator to port 3.
RAL
RAL is the mnemonic for rotate the accumulator left. This
instruction will shift all bits to the left and move the MSB
< a > tbt
Fig. 11-7 Rotate instructions: (a) RAL; ( b ) RAR.
into the LSB position, as illustrated in Fig. ll-7a. As an
example, suppose the contents of the accumulator are
A = 1011 0100
Executing the RAL will produce
A = 0110 1001
As you see, all bits moved left, and the MSB went to the
LSB position.
RAR
RAR stands for rotate the accumulator right. This time,
the bits shift to the right, the LSB going to the MSB
position, as shown in Fig. 11-76. If
A = 1011 0100
the execution of a RAR will result in
A = 0101 1010
EXAMPLE 11-13
The bits in a byte are numbered 7 to 0 (MSB to LSB).
Show a program that can input a byte from port 2 and
determine if bit 0 is a 1 or a 0. If the bit is a 1, the program
is to load the accumulator with an ASCII Y (yes). If the
bit is a 0, the program should load the accumulator with
an ASCII N (no). The yes or no answer is to be sent to
output port 3.
SOLUTION
Label
Mnemonic
Comment
IN 02H
;Get byte from port 2
ANI 01H
;Isolate bit 0
JNZ YES
;Jump if bit 0 is a 1
MVI A,4EH
;Load N into accumulator
JMP DONE
;Skip next instruction
YES:
MVI A,59H
;Load Y into accumulator
DONE:
OUT 03H
HLT
;Send answer to port 3
Chapter 11 SAP-2 185
The IN 02H transfers the contents of input port 2 to the
accumulator to get
A = A7A6A5A4A3A2A] Aq
The immediate byte in ANI 01H is
0000 0001
This byte is called a mask because its 0s will mask or blank
out the corresponding high bits in the accumulator. In other
words, after the execution of ANI 01H the accumulator
contents are
A = 0000 000A 0
If A 0 is 1, the JNZ YES will produce a jump to the MVI
A,59H; this loads a 59H (the ASCII for Y) into the
accumulator. If A 0 is 0, the program falls through to the
MVI A,4EH. This loads the accumulator with the ASCII
for N.
The OUT 03H loads the answer, either ASCII Y or N,
into port 3. The hexadecimal display therefore shows either
59H or 4EH.
EXAMPLE 11-14
Instead of a parallel output at port 3, we want a serial
output at port 4. Modify the foregoing program so that it
converts the answer (59H or 4EH) into a serial output at
bit 0, port 4.
SOLUTION
Label
Mnemonic
IN 02H
ANI 01H
JNZ YES
MVI A,4EH
JMP DONE
Comment
YES:
MVI A,59H
DONE:
MVI C,08H
;Load counter with 8
AGAIN:
OUT 04H
;Send LSB to port 4
RAR
;Position next bit
DCR C
; Decrement count
JNZ AGAIN
HLT
;Test count
In converting from parallel to serial data, the A 0 bit is sent
first, then the bit, then the A 2 bit, and so on.
EXAMPLE 11-15
Handshaking is an interaction between a CPU and a
peripheral device that takes place during an I/O data transfer.
In SAP-2 the handshaking takes place as follows. After
you enter two digits (1 byte) into the hexadecimal encoder
of Fig. 11-2, the data is loaded into port 1; at the same
time, a high READY bit is sent to port 2.
Before accepting input data, the CPU checks the READY
bit in port 2. If the READY bit is low, the CPU waits. If
the READY bit is high, the CPU loads the data in port 1.
After the data transfer is finished, the CPU sends a high
ACKNOWLEDGE signal to the hexadecimal keyboard en¬
coder; this resets the READY bit to 0. The ACKNOWLEDGE
bit then is reset to low.
After you key in a new byte, the cycle starts over with
new data going to the port 1 and a high READY bit to port
2 .
The sequence of SAP-2 handshaking is
1. READY bit (bit 0, port 2) goes high.
2. Input the data in port 1 to the CPU.
3. ACKNOWLEDGE bit (bit 7, port 4) goes high to reset
READY bit.
4 . Reset the ACKNOWLEDGE bit.
Write a program that inputs a byte of data from port 1
using handshaking. Store the byte in the B register.
SOLUTION
Label Mnemonic
Comment
STATUS: IN 02H
;Input byte from port 2
ANI 01H
;Isolate READY bit
JZ STATUS
;Jump back if not ready
IN 01H
;Transfer data in port 1
MOV B,A
;Transfer from A to B
MVI A,80H
;Set ACKNOWLEDGE bit
OUT 04H
;Output high ACKNOWLEDGE
MVI A,00H
;Reset ACKNOWLEDGE bit
OUT 04H
;Output low ACKNOWLEDGE
HLT
If the READY bit is low, the ANI 01H will force the
accumulator contents to go to zero. The JZ STATUS
therefore will loop back to IN 02H. This looping will
continue until the READY bit is high, indicating valid data
in port 1.
When the READY bit is high, the program falls through
the JZ STATUS to the IN 01H. This transfers a byte from
port 1 to the accumulator. The MOV sends the byte to the
B register.The MVI A,80H sets the ACKNOWLEDGE bit
186 Digital Computer Electronics
(bit 7). The OUT 04H sends this high ACKNOWLEDGE
to the hexadecimal encoder where the internal hardware
resets the READY bit. Then the ACKNOWLEDGE bit is
reset in preparation for the next input cycle.
11-8 SAP-2 SUMMARY
This section summarizes the SAP-2 T states, flags, and
addressing modes.
T States
The SAP-2 controller-sequencer is microprogrammed with
a variable machine cycle. This means that some instructions
take longer than others to execute. As you recall, the idea
behind microprogramming is to store the control routines
in a ROM and access them as needed.
Table 11-3 shows each instruction and the number of T
states needed to execute it. For instance, it takes four T
states to execute the ADD B instruction, seven to execute
the ANI byte, eighteen to execute the CALL, and so on.
Knowing the number of T states is important in timing
applications.
Notice that the JM instruction has T states of 10/7. This
means it takes 10 T states when a jump occurs but only 7
without the jump. The same idea applies to the other
conditional jumps; 10 T states for a jump, 7 with no jump.
Flags
As you know, the accumulator goes negative or zero during
the execution of some instructions. This affects the sign
and zero flags. Figure 11-8 shows the circuits used in
SAP-2 to set the flags.
When the accumulator contents are negative, the leading
bit A 7 is a 1. This sign bit drives the lower and gate. When
the accumulator contents are zero, all bits are zero and the
output of the nor gate is a 1. This nor output drives the
upper and gate. If gating signal L F is high, the flags will
be updated to reflect the sign and zero condition of the
accumulator. This means the Z FlAC will be high when the
accumulator contents are zero; the S FLAG will be high when
the accumulator contents are negative.
Not all instructions affect the flags. As shown in Table
11-3, the instructions that update the flags are ADD, ANA,
ANI, DCR, INR, ORA, ORI, SUB, XRA, and XRI. Why
only these instructions? Because the L F signal of Fig. 11-8
is high only when these instructions are executed. This is
accomplished by microprogramming an L F bit for each
instruction. In other words, in the control ROM we store a
high L f bit for the foregoing instructions, and a low L, bit
for all others.
Fig. 11-8 Setting the flags.
Conditional Jumps
As mentioned earlier, the conditional jumps take ten T
states when the jump occurs but only seven T states when
no jump take place. Briefly, this is accomplished as follows.
During the execution cycle the address ROM sends the
computer to the starting address of a conditional-jump
microroutine. The initial microinstruction looks at the flags
and judges whether or not to jump. If a jump is indicated,
the microroutine continues; otherwise, it is aborted and the
computer begins a new fetch cycle.
Addressing Modes
The SAP-2 instructions access data in different ways. It is
the operand that tells us how the data is to be accessed.
For instance, the first instructions discussed were
LDA address
STA address
These are examples of direct addressing because we specify
the address where the data is to be found.
Immediate addressing is different. Instead of giving an
address for the data, we give the data itself. For instance,
MVI A,byte
accesses the data to be loaded into the accumulator by using
the byte in memory that immediately follows the op code.
Table 11-3 shows the other immediate instructions.
An instruction like
MOV A,B
Chapter 11 SAP-2 187
TABLE 11-3. SAP-2 INSTRUCTION SET
Instruction OpCode T States Flags Addressing Bytes
ADD B
ADD C
ANA B
ANA C
ANI byte
CALL address
CMA
DCR A
DCR B
DCR C
HLT
IN byte
INR A
INR B
INR C
80
81
AO
A1
E6
CD
2F
3D
05
0D
76
DB
3C
04
0C
4
4
4
4
7
18
4
4
4
4
5
10
4
4
4
S, Z
s, z
s, z
s, z
s, z
None
None
s, z
s, z
s, z
None
None
S, Z
s, z
s, z
Register
Register
Register
Register
Immediate
Immediate
Implied
Register
Register
Register
Direct
Register
Register
Register
1
1
1
1
2
3
1
1
1
1
1
2
1
1
1
JM address
FA
10/7
None
Immediate
3
JMP address
C3
10
None
Immediate
3
JNZ address
C2
10/7
None
Immediate
3
JZ address
CA
10/7
None
Immediate
3
LDA address
3A
13
None
Direct
3
MOV A,B
78
4
None
Register
1
MOV A,C
79
4
None
Register
1
MOV B,A
47
4
None
Register
1
MOV B,C
41
4
None
Register
1
MOV C,A
4F
4
None
Register
1
MOV C,B
48
4
None
Register
i
MVI A,byte
3E
7
None
Immediate
2
MVI B,byte
06
7
None
Immediate
2
MVI C.byte
0E
7
None
Immediate
2
NOP
00
4
None
—
1
ORA B
B0
4
S, Z
Register
1
ORA C
B1
4
s, z
Register
1
ORI byte
F6
7
s, z
Immediate
2
OUT byte
D3
10
None
Direct
2
RAL
17
4
None
Implied
1
RAR
IF
4
None
Implied
1
RET
C9
10
None
Implied
1
ST A address
32
13
None
Direct
3
SUB B
90
4
S, Z
Register
1
SUB C
91
4
s, z
Register
1
XRA B
A8
4
s, z
Register
1
XRA C
A9
4
s, z
Register
1
XRI byte
EE
7
s, z
Immediate
2
is an example of register addressing. The data to be loaded
is stored in a CPU register rather than in the memory.
Register addressing has the advantage of speed because
fewer T states are needed for this type of instruction.
Implied addressing means that the location of the data
contained within the op code itself. For instance,
RAL
188 Digital Computer Electronics
tells us to rotate the accumulator bits left. The data is in
the accumulator; this is why no operand is needed with
implied addressing.
Bytes
Each instruction occupies a number of bytes in the memory.
SAP-2 instructions are either 1, 2, or 3 bytes long. Table
11-3 shows the length of each instruction. As you see,
ADD instructions are 1-byte instructions, ANI instructions
are 2-byte instructions, CALLs are 3-byte instructions, and
so forth.
EXAMPLE 11-16
SAP-2 has a clock frequency of 1 MHz. This means that
each T state has a duration of 1 jjls. How long does it take
to execute the following SAP-2 subroutine?
Label
Mnemonic
Comment
MVI C,46H
;Preset count to decimal 70
AGAIN:
DCR C
;Count down
JNZ AGAIN
;Test count
NOP
RET
;Delay
SOLUTION
The total byte length of the subroutine is 8. As part of the
SAP-2 software, the foregoing subroutine can be assembled
and relocated at addresses F010H to F017H. Hereafter, the
execution of a CALL F010H will produce a time delay of
1 ms.
EXAMPLE 11-17
How much time delay does this SAP-2 subroutine produce?
Label
Mnemonic
Comment
MVI B,0AH
;Preset B counter with
decimal 10
LOOP1:
MVI C,47H
;Preset C counter with
decimal 71
LOOP2:
DCR C
;Count down on C
JNZ LOOP2
;Test for C count of zero
DCR B
;Count down on B
JNZ LOOP1
RET
;Test for B count of zero
SOLUTION
This subroutine has two loops, one inside the other. The
inner loop consists of DCR C and JNZ LOOP2. This inner
loop produces a time delay of
The MVI is executed once to initialize the count. The DCR
is executed 70 times. The JNZ jumps back 69 times and
falls through once. With the number of 7 states given in
Table 11-3, we can calculate the total execution time of
the subroutine as follows:
MVI:
1 x 7
X
1
(JLS =
7 |JLS
DCR:
70 x 4
X
1
(JLS =
280
JNZ:
69 x 10
X
1
JJLS =
690
JNZ:
1 x 7
X
I
(JLS =
7
NOP:
1 x 4
X
1
fJLS =
4
RET:
1 x 10
X
1
(JLS =
10
(jump)
(no jump)
998 ns « 1 ms
As you see, the total time needed to execute the subroutine
is approximately 1 ms.
A subroutine like this can produce a time delay of 1 ms
whenever it is called. There are many applications where
you need a delay.
According to Table 11-3, the instructions in the foregoing
subroutine have the following byte lengths:
Instruction
MVI
DCR
JNZ
NOP
RET
Bytes
2
1
3
1
1
DCR C: 71 X 4 X 1 p.s = 284 pis
JNZ LOOP2: 70 X 10 X 1 p,s = 700 (jump)
JNZ LOOP2: 1 x 7 x 1 pis =_ 1_ (no jump)
991 pis
When the C count drops to zero, the program falls through
the JNZ LOOP2. The B counter is decremented, and the
JNZ LOOP1 sends the program back to the MVI C,47H.
Then we enter LOOP2 for a second time. Because LOOP2
is inside LOOP1, LOOP2 will be executed 10 times and
the overall time delay will be approximately 10 ms.
Here are the calculations for the overall subroutine:
MVI B,0AH:
MVI C,47H:
LOOP2:
DCR B:
JNZ LOOP1:
JNZ LOOP1:
RET:
1 X 7 X 1 jjls =
7 JJLS
10 X 7 X 1 (jls =
70
10 X 991 |uls =
9,910
10 x 4 X 1 (is =
40
9 X 10 X 1 |uls =
90
(jump)
1 x 7 x 1 (jls =
7
(no jump)
1 x 10 X 1 JJLS =
10
10,134 p,s ~ 10 ms
This SAP-2 subroutine has a byte length of
2 + 2+1+3+1+3+1 = 13
Chapter 11 SAP-2 189
It can be assembled and located at addresses F020H to
F02CH. From now on, a CALL F020H will produce a time
delay of approximately 10 ms.
By changing the first instruction to
MVI B,64H
the B counter is preset with decimal 100. In this case, the
inner loop is executed 100 times and the overall time delay
is approximately 100 ms. This 100-ms subroutine can be
located at addresses F030H to F03CH.
EXAMPLE 11-18
Here is a subroutine with three loops nested one inside the
other. How much time delay does it produce?
Label
Mnemonic
Comment
MVI A,0AH
;Preset A counter with
decimal 10
LOOP 1:
MVI B,64H
;Preset B counter with
decimal 100
LOOP2:
MVI C,47H
;Preset C counter with
decimal 71
LOOP3:
DCR C
;Count down C
JNZ LOOP3
;Test C for zero
DCR B
;Count down B
JNZ LOOP2
;Test B for zero
DCR A
;Count down A
JNZ LOOP1
RET
;Test A for zero
SOLUTION
LOOP3 still takes approximately 1 ms to get through.
LOOP2 makes 100 passes through LOOP3, so it takes about
100 ms to complete LOOP2. LOOP1 makes 10 passes
through LOOP2; therefore, it takes around 1 s to complete
the overall subroutine.
What do we have? A 1-s subroutine. It will be located
in F040H to F052H. To produce a 1-s time delay, we
would use a CALL F040H.
By changing the initial instruction to
MVI A,64H
LOOP1 will make 100 passes through LOOP2, which
makes 100 passes through LOOP3. The resulting subroutine
can be located at F060H to F072H and will produce a time
delay of 10 s.
Table 11-4 summarizes the SAP-2 time delays. With
these subroutines, we can produce delays from 1 ms to
10 s.
TABLE 11-4. SAP-2 SUBROUTINES
Label Starting Address Delay Registers Used
DIMS F010H
D10MS F020H
D100MS F030H
DISEC F040H
D10SEC F060H
EXAMPLE 11-19
The traffic lights on a main road show green for 50 s,
yellow for 6 s, and red for 30 s. Bits 1, 2, and 3 of
port 4 are the control inputs to peripheral equipment that
runs these traffic lights. Write a program that produces time
delays of 50, 6, and 30 s for the traffic lights.
SOLUTION
Label
Mnemonic
Comment
AGAIN:
MVI A,32H
;Preset counter with
decimal 50
STA SAVE
;Save accumulator
contents
MVI A,02H
;Set bit 1
OUT 04H
;Tum on green light
LOOPGR:
CALL DISEC
;Call 1-s subroutine
LDA SAVE
;Load current A count
DCR A
;Decrement A count
STA SAVE
;Save reduced A count
JNZ LOOPGR
;Test for zero
MVI A,06H
STA SAVE
;Preset counter with
decimal 6
MVI A,04H
;Set bit 2
OUT 04H
;Tum on yellow light
LOOPYE:
CALL DISEC
LDA SAVE
DCR A
STA SAVE
JNZ LOOPYE
MVI A,1EH
STA SAVE
;Preset counter with
decimal 30
MVI A,08H
;Set bit 3
OUT 04H
;Tum on red light
LOOPRE:
CALL DISEC
LDA SAVE
DCR A
STA SAVE
JNZ LOOPRE
JMP AGAIN
SAVE:
Data
1 ms C
10 ms B, C
100 ms B, C
Is A, B, C
10 s A, B, C
190 Digital Computer Electronics
Let’s go through the green part of the program; the yellow
and red are similar. The green starts with MVI A,32H,
which loads decimal 50 into the accumulator. The STA
SAVE will store this initial value in a memory location
called SAVE. The MVI A,02H sets bit 1 in the accumulator;
then the OUT 04H transfers this high bit to port 4. Since
this port controls the traffic lights, the green light comes
on.
The CALL DISEC produces a time delay of 1 s. The
LDA SAVE loads the accumulator with decimal 50. The
DCR A decrements the count to decimal 49. The STA
SAVE stores this decimal 49. Then the JNZ LOOPGR
takes the program back to the CALL DISEC for another
1-s delay.
The CALL DISEC is executed 50 times; therefore, the
green light is on for 50 s. Then the program falls through
the JNZ LOOPGR to the MVI A,06H. The yellow part of
the program then begins and results in the yellow light
being on for 6 s. Finally, the red part of the program is
executed and the red light is on for 30 s. The JMP AGAIN
repeats the whole process. In this way, the program is
controlling the timing of the green, yellow, and red lights.
EXAMPLE 11-20
Middle C on a piano has a frequency of 261.63 Hz. Bit 5
of port 4 is connected to an amplifier which drives a
loudspeaker. Write a program that sends middle C to the
loudspeaker.
SOLUTION
n
~L
IT
— 3822 jus
1911 ns
Fig. 11-9 Generating middle C note.
The OUT 04H sends a bit (either low or high) to the
loudspeaker. The MVI presets the counter to decimal 134.
Then comes LOOP2, the DCR and JNZ, which produces
a time delay of 1,866 |xs. The program then falls through
to the CM A, which complements all bits in the accumulator.
The two NOPs add a time delay of 8 p.s. The JMP LOOP1
then takes the program back. When the OUT 04H is
executed, bit 5 (complemented) goes to the loudspeaker.
In this way the loudspeaker is driven into the opposite state.
The execution time for both half cycles is 3,824 p,s, close
enough to middle C.
Here are the calculations for the time delay:
OUT 04H:
MVI C,86H:
DCR C:
JNZ LOOP2:
JNZ LOOP2:
CMA:
2 NOPs:
JMP LOOP1:
1 x 10 X 1 |xs = 10 p,s
lx7xl(j,s= 7
134 x 4 X 1 (xs = 536
133 x 10 x 1 |xs = 1,330
1 x 7 x 1 |xs = 7
1 X 4 X 1 (is = 4
2 x 4 x 1 |xs = 8
1 X 10 X 1 (ULS = _10
1,912 |xs
To begin with, the period of middle C is
This is the half-cycle time. The period is 3,824 |xs.
T
1
/
1
261.63 Hz
3,822 p,s
What we are going to do is send to port 4 a signal like Fig.
11-9. This square wave is high for 1,911 |xs and low for
1,911 (xs. The overall period is 3,822 |xs, and the frequency
is 261.63 Hz. Because the signal is square rather than
sinusoidal, it will sound distorted but it will be recognizable
as middle C.
Here is a program that sends middle C to the loudspeaker.
Label
Mnemonic
Comment
LOOP1:
OUT 04H
;Send bit to speaker
MVI C,86H
;Preset counter with decimal
134
LOOP2:
DCR C
;Count down
JNZ LOOP2
;Test count
CMA
;Reset bit 5
NOP
;Fine tuning
NOP
;Fine tuning
JMP LOOP1
;Go back for next half cycle
EXAMPLE 11-21
Serial data is sometimes called a serial data stream because
bits flow one after another. In Fig. 11-10 a serial data
stream drives bit 7 of port 2 at a rate of approximately 600
bits per second. Write a program that inputs an 8-bit
character in a serial data stream and stores it in memory
location 2100H.
SOLUTION
Since approximately 600 bits are received each second, the
period of each bit is
1
600 Hz
1,667 |xs
The idea will be to input a bit from port 2, rotate the
accumulator right, wait approximately 1,600 |xs, then input
another bit, rotate the accumulator right, and so on, until
all bits have been received.
Chapter 11 SAP-2 191
W bus
Fig. 11-10
Here is
Label
BIT:
DELAY:
ACKNOWLEDGE
READY
SERIAL IN
CON
a program that will work:
Mnemonic
Comment
MVI B,00H
;Load zero into B register
MVI C,07H
;Preset counter with decimal 7
IN 02H
;Input data
ANI 80H
;Isolate bit 7
ORA B
;Update character
RAR
;Move bits right
MOV B,A
;Save bits in B
MVI A,73H
;Begin a delay of 1 ,600 |jls
DCR A
;Count down A
JNZ DELAY
;Test A count for zero
DCR C
;Count down C
JNZ BIT
;Test C count for zero
IN 02H
;Input last bit
ANI 80H
;Isolate bit 7
ORA B
STA 2100H
;Save character
The first instruction clears the B register. The second
instruction loads decimal 7 into the C counter. The IN 02H
brings in the data from port 2. The ANI mask isolates bit
7 because this is the SERIAL IN bit from port 2. The ORA
B does nothing the first time through because B is full of
Os. The RAR moves the accumulator bits to the right. The
MOV B,A stores the accumulator contents in the B register.
MVI A,73H presets the accumulator with decimal 115.
Then comes a delay loop, DCR A and JNZ DELAY, that
takes approximately 1,600 jxs to complete.
The DCR C reduces the C count by 1, and the JNZ BIT
tests the C count for zero. The program jumps back to the
IN 02H to get the next bit from the serial data stream. The
ANI mask isolates bit 7, which is then ORed with the
contents of the B register; this combines the previous bit
with the newly received bit. After another RAR, the two
received bits are stored in the B register. Then comes
another delay of approximately 1,600 jjls.
The program continues to loop and each time a new bit
is input from the serial data stream. After 7 bits have been
192 Digital Computer Electronics
received, the program will fall through the JNZ BIT
instruction.
The last four instructions do the following. The IN 02H
brings in the eighth bit. The ANI isolates bit 7. The ORA
B combines this new bit with the other seven bits in the B
register. At this point, all received bits are in the accu¬
mulator. The STA 2100H then stores the byte in the
accumulator at 2100H.
A concrete example will help. Suppose the 8 bits being
received are 57H, the ASCII code for W. The LSB is
received first, the MSB last. Here is how the contents of
the B register appear after the execution of the ORA B:
A = 1000 0000
A = 1100 0000
A = 1110 0000
A = 01110000
A = 1011 1000
A = 0101 1100
A = 1010 1110
A = 01010111
(First pass through loop)
(Second pass)
(Third pass)
(Fourth pass)
(Fifth pass)
(Sixth pass)
(Seventh pass)
(Final contents)
Incidentally, the ASCII code only requires 7 bits; for this
reason, the eighth bit (A-j) may be set to zero or used as a
parity bit.
GLOSSARY
assembler A program that converts a source program into
a machine-language program.
comment Personal notes in an assembly-language program
that are not assembled. They refresh the programmer’s
memory at a later date.
conditional jump A jump that occurs only if certain
conditions are satisfied.
direct addressing Addressing in which the instruction
contains the address of the data to be operated on.
flag A flip-flop that keeps track of a changing condition
during a computer run.
hand assembling Translating a source program into a
machine-language program by hand rather than computer.
handshaking Interaction between a CPU and a peripheral
device that takes place during an I/O operation. In SAP-2
it involves READY and ACKNOWLEDGE signals.
immediate addressing Addressing in which the data to be
operated on is the byte immediately following the op code
of the instruction.
implied addressing Addressing in which the location of
the data is contained within the mnemonic.
label A name given to an instruction in an assembly-
language program. To jump to this instruction, you can use
the label rather than the address. The assembler will work
out the correct address of the label and will use this address
in the machine-language program.
mask A byte used with an ANI instruction to blank out
certain bits.
register addressing Addressing in which the data is stored
in a CPU register.
relocate To move a program or subroutine to another part
of the memory. In doing this, the addresses of jump
instructions must be converted to new addresses.
subroutine A program stored in higher memory that can
be used repeatedly as part of a main program.
SELF-TESTING REVIEW
Read each of the following and provide the missing words.
Answers appear at the beginning of the next question.
1. The controller-sequencer produces_
words or microinstructions.
2. {control) A flag is a_that keeps track of
a changing condition during a computer run. The
sign flag is set when the accumulator contents go
negative. The-flag is set when the accu¬
mulator contents go to zero.
3. (flip-flop, zero) In coding the LDA address and
STA address instructions, the_byte of
the address is stored in lower memory, the_
byte in upper memory.
4. {lower, upper) The JMP instruction changes the
program sequence by jumping to another part of the
program. With the JM instruction, the jump is exe¬
cuted only if the sign flag is_With the
JNZ instruction, the jump is executed only if the
zero flag is_
5. {set, clear) Every subroutine must terminate with a
-instruction. This returns the program to
the instruction following the CALL. The CALL
instruction is unconditional; it sends the computer to
the starting address of a_
6. {RET, subroutine) An assembler allows you to write
programs in mnemonic form. Then the assembler
Chapter 11 SAP-2 193
7.
8 .
9.
converts these mnemonics into-lan¬
guage. The assembler ignores the-fol¬
lowing a semicolon and assigns addresses to the
labels. Labels can be up to six characters, the first
of which must be a-
(machine, comments, letter ) Repeated addition is
one way to do_Programmed multiplica¬
tion is used in most microprocessors because their
ALUs can only add and subtract.
(multiplication) A parameter is a piece of data
passed to a_* WTien you call a subrou¬
tine, you often need to pass-for the
subroutine to work properly.
(subroutine, parameters) A-
. is used to
isolate a bit; it does this because the ANI sets all
other bits to zero.
10. (mask) Handshaking is an interaction between a
__ and a peripheral device. In SAP-2 the
_bit tells the CPU whether the input data
is valid or not. After the data has been transferred
into the computer, the CPU sends an-
bit to the peripheral device.
11. (CPU, READY, ACKNOWLEDGE) The SAP-2
computer is microprogrammed with a-
machine cycle. This means that some instructions
take longer than others to execute.
12. (variable) The types of addressing covered up to
now are direct, immediate, register, and implied.
PROBLEMS
11-1. Write a source program that loads the accumula¬
tor with decimal 100, the B register with deci¬
mal 150, and the C register with decimal 200.
11-2. Hand-assemble the source program of the pre¬
ceding problem starting at address 2000H.
11-3. Write a source program that stores decimal 50 at
memory location 4000H, decimal 51 at 4001H,
and decimal 52 at 4002H.
11-4. Hand-assemble the source program in the pre¬
ceding problem starting at address 2000H.
11-5. Write a source program that adds decimal 68 and
34, with the answer stored at memory location
5000H.
11-6. Hand-assemble the preceding program starting at
address 2000H.
11-7. Here is a program:
Label Mnemonic
LOOP: MVI C,78H
DCR C
JNZ LOOP
HLT
a. How many times (decimal) is the DCR C
executed?
b. How many times does the program jump to
LOOP?
c. How can you change the program to loop 210
times?
11-8. Which of the following are valid labels?
a. G100
b. UPDATE
c. 5TIMES
d. 678RED
e. T
f. REPEAT
11-9. Write a program that multiplies decimal 25 and
7 and stores the answer at 2000H. (Use the
multiply subroutine located at F006H.)
11-10. Write a program that inputs a byte from port 1
and determines if the decimal equivalent is even
or odd. If the byte is even, the program is to
send an ASCII E to port 3; if odd, an ASCII O.
11-11. Modify the foregoing program so that it sends
the answer in serial form to bit 0 of port 4.
11-12. Write a program that inputs a byte from port 1
using handshaking. Store the byte at address
4000H.
11-13. Hand assemble the foregoing program starting at
address 2000H.
11-14. Write a subroutine that produces a time delay of
approximately 500 |xs.
11-15. Hand-assemble the preceding program starting at
address 2000H.
11-16. Write a subroutine that produces a time delay of
approximately 35 ms using a SAP-2 subroutine.
Hand-assemble this subroutine and locate it at
starting address E000H.
11-17. Write a subroutine that produces a time delay of
50 ms. (Use a SAP-2 subroutine.) Hand-assem¬
ble the program at starting address E100H.
11-18. Write a subroutine that produces a delay of 1
min. (Use CALL F060H.)
11-19. Hand-assemble the preceding subroutine at start¬
ing addresses F080H.
11-20. The C note one octave above middle C has a
frequency of 523.25 Hz. Write a program that
sends this note to bit 4 of port 4.
11-21. Hand-assemble the foregoing program starting at
address 2000H.
1 94 Digital Computer Electronics
SAP-3
The SAP-3 computer is an 8-bit microcomputer that is
upward-compatible with the 8085 microprocessor. In this
chapter, the emphasis is on the SAP-3 instruction set. This
instruction set includes all the SAP-2 instructions of the
preceding chapter plus new instructions to be discussed.
Appendix 6 shows the op codes, T states, flags, and so
forth, for the SAP-3 instructions. In the remainder of this
chapter, refer to Appendix 6 as needed.
12-1 PROGRAMMING MODEL
All you need to know about SAP-3 hardware is the
programming model of Fig. 12-1. This is a diagram showing
the CPU registers needed by a programmer.
Some of the CPU registers are familiar from SAP-2. For
instance, the program counter (PC) is a 16-bit register that
can count from 0000H to FFFFH or decimal 0 to 65,535.
As you know, the program counter sends out the address
of the next instruction to be fetched. This address is latched
into the MAR.
CPU registers A, B, and C are the same as in SAP-2.
These 8-bit registers are used in arithmetic and logic
operations. Since the accumulator is only 8 bits wide, the
range of unsigned numbers is 0 to 255; the range of signed
2’s-complement numbers is - 128 to +127.
SAP-3 has additional CPU registers (D, E, H, and L)
for more efficient data processing. These 8-bit registers can
be loaded with MOV and MVI instructions, the same as
the A, B, and C registers. Also notice the F register, which
stores flag bits S, Z, and others.
Finally, there is the stack pointer (SP), a 16-bit register.
This new register controls a portion of memory known as
the stack . The stack and the stack pointer are discussed
later in this chapter.
Figure 12-1 shows all the CPU registers needed to
understand the SAP-3 instruction set. With this program¬
ming model we can discuss the SAP-3 instruction set,
which is upward-compatible with the 8080 and 8085. At
the end of this chapter, you will know almost all of the
8080/8085 instruction set.
12-2 MOV AND MVI
The MOV and MVI instructions work the same as in SAP-
2. The only difference is more registers to choose from.
The format of any move instruction is
MOV regl, reg2
where regl = A, B, C, D, E, H, orL
reg2 = A, B, C, D, E, H, or L
PC
SP
Fig. 12-1 SAP-3 programming model.
The MOV instructions send the data in reg2 to regl.
Symbolically,
regl ^reg2
where the arrow indicates that the data in register 2 is
copied nondestructive^ into register 1. At the end of the
execution
regl = reg2
For instance,
MOV L,A
copies A into L, so that
L = A
Similarly,
MOV E,H
gives
E = H
The immediate moves have the format of
MVI reg,byte
12-3 ARITHMETIC INSTRUCTIONS
Since the accumulator is only 8 bits wide, its contents can
represent unsigned numbers from 0 to 255 or signed 2’s
complement numbers from — 128 to +127. Whether signed
or unsigned binary numbers are used, the programmer needs
to detect overflows , sums or differences that lie outside the
normal range of the accumulator. This is where the carry
flag comes in.
Carry Flag
As shown in Fig. 6-7, a 4-bit adder-subtracter produces a
sum S 3 S 2 S 1 S 0 and a carry. In SAP-1, two 74LS83s (equiv¬
alent to eight full adders) produce an 8-bit sum and a carry.
In this simple computer, the carry is disregarded. SAP-3,
however, takes the carry into account.
Figure 12-2a shows the logic circuit used for the SAP-3
adder-subtracter. When SUB is low, the circuit adds the A
and B inputs. If a final carry is generated, CARRY will be
high and CY will be high. If there is no final carry, CY is
low.
On the other hand, when SUB is high, the circuit forms
the 2’s complement of B, which is then added to A, Because
of the final xor gate, a high CARRY out of the last full-
adder produces a low CY. If no carry occurs, CY is high.
In summary,
CY
CARRY
CARRY
for ADD instructions
for SUB instructions
where reg = A, B, C, D, E, H, or L. Therefore, the
execution of
MVI D,0EH
will result in
D = OEH
During an add operation, CY is called a carry. During a
subtract operation, CY is referred to as a borrow.
The 8-bit sum S 7 S 6 S 5 S 4 S 3 S 2 S l So is stored in the accu¬
mulator of Fig. 12-2 b. The carry (or borrow) is stored in a
special flip-flop called the carry flag , designated CY in Fig.
12-2 b. This flag acts like the next higher bit of the
accumulator. That is,
Likewise,
CY =A 8
MVI L,FFH
produces
L = FFH
Carry-Flag Instructions
There are two instructions we can use to control the carry
flag. The STC instruction will set the CY flag if it is not
already set. (STC stands for set carry.) So, if
What is the advantage of more CPU registers? As you
may recall, MOV and MVI instructions use fewer T states
than memory-reference instructions (MRIs). The extra CPU
registers mean that we can use more MOV and MVI
instructions and fewer MRIs. Because of this, SAP-3
programs can run faster than SAP-2 programs; furthermore,
having more CPU registers for temporary storage simplifies
program writing.
CY = 0
the execution of a STC instruction produces
CY = 1
The other carry-flag instruction is the CMC, which stands
for complement the carry. When executed, a CMC corn-
196 Digital Computer Electronics
SUB
CARRY
CY
(a)
(b)
Fig. 12-2 (a) SAP-3 adder-subtractor ( b ) carry flag and accumu¬
lator.
plements the value of CY. If CY = I, CMC produces a CY
of 0. On the other hand, if CY = 0, CMC results in a CY
of 1.
If you want to reset the carry flag and its current status
is unknown, you have to set it, then complement it. That
is, execution of
STC
CMC
guarantees that the final value of CY will be 0 if the initial
value of CY is unknown.
ADD Instructions
The format of the ADD instruction is
ADD reg
where reg = A, B, C, D, E, H, or L. This instruction
adds the contents of the specified register to the accumulator
contents. The sum is stored in the accumulator and the
carry flag is set or reset, depending on whether there is a
final carry or not.
For instance, suppose
A = 1111 0001 and E = 0000 1000
The instruction
ADD E
produces the binary addition
1111 0001
± 0000 1000
ini iooi
There is no final carry; therefore, at the end of the instruction
cycle,
CY = 0 and A = 1111 1001
As another example, suppose
A = 1111 1111 and L = 0000 0001
Then executing an ADD L produces
1111 1111
+ 0000 0001
1 0000 0000
At the end of the instruction cycle
CY - 1 and A = 0000 0000
ADC Instructions
The ADC instruction (add with carry) is formatted like this:
ADC reg
Chapter 12 SAP-3 1 97
where reg = A, B, C, D, E, H, or L. This instruction
adds the contents of the specified register plus the carry
flag to the contents of the accumulator. Because it includes
the CY flag, the ADC instruction allows us to add numbers
outside the unsigned 0 to 255 range or the signed - 128 to
4-127 range.
As an example, suppose
A = 1000 0011
E = 0001 0010
and CY = 1
The execution of
ADC E
produces the following addition:
1000 0011
00010010
+_ 1
10010110
Therefore, the new accumulator and carry flag contents are
CY = 0 A = 1001 0110
SUB Instructions
The SUB instruction is formatted as
SUB reg
where reg = A, B, C, D, E, H, or L. This instruction will
subtract the contents of the specified register from the
accumulator contents; the result is stored in the accumulator.
If a final borrow occurs, the CY flag is set. If there is no
borrow, the CY flag is reset. In other words, during
subtraction the CY flag functions as a borrow flag.
For example, if
A = 0000 1111 and C = 0000 0001
then
SUB C
results in
Notice that there is no final borrow. In terms of 2’s-
complement addition, the foregoing subtraction appears like
this:
0000 1111
+ ini mi
10000 1110
The final CARRY is 1, but this is complemented during
subtraction to get a CY of 0 (Fig. 12-2 a). This is why the
execution of SUB C produces
CY = 0 A = 0000 1110
Here is another example. If
A = 0000 1100 and C = 0001 0010
then a SUB C produces
0000 1100
- 0001 0010
i mi ioio
Notice the final borrow. This borrow occurs because the
contents of the C register (decimal 18) are greater than the
contents of the accumulator (decimal 12). In terms of 2’s-
complement arithmetic, the foregoing looks like
0000 1100
+ 11101110
01111 1010
In this case, CARRY is 0 and CY is 1. The final register
and flag contents are
CY = 1 and A = 1111 1010
SBB Instructions
SBB stands for subtract with borrow. This instruction goes
one step further than the SUB. It subtracts the contents of
a specified register and the CY flag from the accumulator
contents. If
A = 1111 1111
E = 0000 0010
and CY = 1
the instruction SBB E starts by combining E and CY to get
0000 0011 and then subtracts this from the accumulator as
follows:
0000 1111
- 0000 0001
nil nil
- oooooon
0000 1110
mi noo
198 Digital Computer Electronics
The final contents are
CY = 0 and A = 1111 1100
EXAMPLE 12-1
In unsigned binary, 8 bits can represent 0 to 255, whereas
16 bits can represent 0 to 65,535. Show a SAP-3 program
that adds 700 and 900, with the final answer stored in the
H and L registers.
SOLUTION
Double bytes can represent decimal 700 and 900 as follows:
700 10 = 02BCH = 0000 0010 1011 1100 2
900,o = 0384H = 0000 0011 1000 0100,
Here is how to add 700 and 900:
Label Instruction Comment
MVI A,00H ;Clear the accumulator
MVI B,02H ;Store upper byte (UB) of
700
MVI C,BCH ;Store lower byte (LB) of
700
MVI D,03H ;Store UB of 900
MVI E,84H ;Store LB of 900
ADD C ;Add LB of 700
ADD E ;Add LB of 900
MOV L,A ;Store partial sum
MVI A,00H ;Clear the accumulator
ADC B ;Add UB of 700 with carry
ADD D ;Add UB of 900
MOV H,A ;Store partial sum
HLT ;Stop
The first five instructions initialize registers A through E.
The ADD C and ADD E add the lower bytes BCH and
84H; this addition sets the carry flag because
BCH = 10111100,
+ 84H = 1000 0100,
1 40H = 1 0100 0000,
The sum is stored in the L register and the final carry in
the CY flag.
Next, the accumulator is cleared. The ADC B adds the
upper byte plus the carry flag to get
OOH = 0000 0000 2
+ 02H = 0000 0010 2
+ 1H = _ U
03 H = 0000 0011 2
Then the ADD D produces
03H = 0000 0011 2
+ 03H = 0000 0011 2
06H = 0000 0110,
The MOV H,A stores this upper sum in the H register.
So the program ends with the answer stored in the H and
L registers as follows:
H = 06H = 0000 0110,
and L = 40H = 0100 0000 2
The complete answer is 0640H, which is equivalent to
decimal 1,600.
12-4 INCREMENTS, DECREMENTS,
AND ROTATES
This section is about increment, decrement, and rotate
instructions. The increment and decrement are similar to
those of SAP-2, but the rotates are different because of the
carry flag.
Increment
The increment instruction appears as
INR reg
where reg = A, B, C, D, E, H, or L. It works as previously
described. Therefore, given
L = 0000 1111
the execution of INR L produces
L = 0001 0000
The INR instruction has no effect on the carry flag, but,
as before, it does affect the sign and zero flags. For instance,
if
B = 1111 1111
and the initial flags are
5=1 Z = 0 CY = 0
then INR B produces
B = 0000 0000
5 = 0 Z = 1 CY = 0
Chapter 12 SAP-3 I 99
As you see, the carry flag is unaffected even though the B
register overflowed. At the same time, the zero flag has
been set and the sign flag reset.
Decrement
The decrement is similar. It looks like
DCR reg
where reg = A, B, C, D, E, H, or L. If
E = 01110110
then a DCR E produces
E = 01110101
The DCR affects the sign and zero flags but not the carry
flag. This is why the initial values may be
E = 0000 0000
S = 0 Z = 1 CY = 0
Executing a DCR E results in
E = 11111111
S = 1 Z - 0 CY = 0
(b)
Fig. 12-3 (a) RAL; (b) RAR.
Rotate All Left
Figure 12-3 a illustrates the RAL instruction used in
SAP-3. The CY flag is included in the rotation of bits.
RAL stands for rotate all left, which is a reminder that all
bits including the CY flag are rotated to the left.
If the initial values are
CY = 1 A = 0111 0100
As you see, the original CY goes to the LSB position, and
the original MSB goes to the CY flag.
Rotate All Right
The rotate-all-right instruction (RAR) rotates all bits in¬
cluding the CY flag to the right, as shown in Fig. 12-3 b.
If
CY = 1 A = 01110100
an RAR will result in
CY — 0 A = 1011 1010
This time, the original CY goes to the MSB position, and
the original LSB goes into the CY flag.
(b)
Fig. 12-4 (a) RLC; (b) RRC.
Rotate Left with Carry
Sometimes you don’t want to treat the CY flag as an
extension of the accumulator. In other words, you may not
want to rotate all bits. Figure 12-4a illustrates the RLC
instruction. The accumulator bits are rotated left, and the
MSB is saved in the CY flag. For instance, given
CY = 1 A = 0111 0100
executing an RLC produces
CF = 0 A =1110 1000
Rotate Right with Carry
Figure 12-4 b shows how the RRC instruction rotates the
bits. In this case, the accumulator bits are rotated right and
the LSB is saved in the CY flag. So, given
CY = 1 A = 0111 0100
then executing a RAL instruction produces an RRC will result in
cy = o a =11101001 cy = o a = 00111010
200 Digital Computer Electronics
Multiply and Divide by 2
Example 11-14 showed a program where the RAR instruc¬
tion was used in converting from parallel to serial data.
Parallel-to-serial conversion, and vice versa, is one of the
main uses of rotate instructions.
There is another use for rotate instructions. Rotating has
the effect of multiplying or dividing the accumulator contents
by a factor of 2. Specifically, with the carry flag reset, an
RAL has the effect of multiplying by 2, while the RAR
divides by 2. This can be proved algebraically, but it’s
much easier to examine a few specific examples to see how
it works.
Suppose
CY = 0 A = 0000 0111
Then an RAL produces
CY = 0 A = 0000 1110
The accumulator contents have changed from decimal 7 to
decimal 14. The RAL has multiplied by 2.
Likewise, if
cy = o A = 0010 0001
then an RAL results in
cy = o A = 0100 0010
In this case, A has changed from decimal 33 to 66.
RAR instructions have the opposite effect; they divide
by 2. If
CV = 0 A = 0001 1000
an RAR gives
cy = 0 A = 0000 1100
The decimal contents of the accumulator have changed from
decimal 24 to 12.
Remember the basic idea. RAL instructions have the
effect of multiplying by 2; RAR instructions divide by 2.
12-5 LOGIC INSTRUCTIONS
The SAP-3 logic instructions are almost the same as in
SAP-2. For instance, three of the logic instructions are
ANA reg
ORA reg
XRA reg
where reg = A, B, C, D, E, H, or L. These instructions
will and, or, or xor the contents of the specified register
with the contents of the accumulator on a bit-by-bit basis.
The only new logic instruction is the CMP, formatted as
CMP reg
where reg = A, B, C, D, E, H, or L. CMP compares the
contents of the specified register with the contents of the
accumulator. The zero flag indicates the outcome of this
comparison as follows:
7 = [ 1 if A = reg
[0 if A ^ reg
SAP-3 carries out a CMP as follows. The contents of
the accumulator are copied in a temporary register. Then
the contents of the specified register are subtracted from
the contents of the temporary register. Since the ALU does
the subtraction, the zero flag is affected. If the 2 bytes
being compared are equal, the zero flag is set. If the bytes
are unequal, the zero flag is reset. Because the temporary
register is used, the accumulator contents are not changed
by a CMP instruction.
For example, if
A = F8H
D = F8H
and Z = 0
executing a CMP D results in
A = F8H
D = F8H
and Z = 1
CMP has no effect on A and D; only the flag changes to
indicate that A and D are equal. (If they were not equal, Z
would be 0.)
CMP is a powerful instruction because it allows us to
compare the accumulator contents with the data in a specified
register. By following a CMP with a conditional zero jump,
we can control loops in a new way. Later programs will
show how this is done.
12*6 ARITHMETIC AND LOGIC
IMMEDIATES
So far, we have introduced these arithmetic and logic
instructions: ADD, ADC, SUB, SBB, ANA, ORA, XRA,
and CMP. Each of these has the accumulator as an implied
register; the data comes from a specified register (A, B, C,
D, E, H, or L).
Chapter 12 SAP-3 201
The immediate instructions from SAP-2 that carry over
to SAP-3 are ANI, ORI, and XRI. As you know, each of
these has the format of
ANI byte
ORI byte
XRI byte
where the immediate byte is ANDed, ORed, or xoRed with
the accumulator byte.
Besides the foregoing, SAP-3 has these immediate in¬
structions:
ADI byte
ACI byte
SUI byte
SBI byte
CPI byte
The ADI adds the immediate byte to the accumulator byte.
The ACI adds the immediate byte plus the CY flag to the
accumulator byte. The SUI subtracts the immediate byte
from the accumulator byte. The SBI subtracts immediate
byte and the CY flag from the accumulator byte. The CPI
compares the immediate byte with the accumulator byte; if
the bytes are equal, the zero flag is set; if not, it is reset.
At this point,
CY — 1 A = C8H
The high CY flag indicates a borrow.
After saving C8H in the L register, the program loads
the upper byte of 900 into the accumulator. The SBI is
used instead of a SUI because of the borrow that occurred
when subtracting the bytes. The execution of the SBI gives
0000 0011
- 0000 0010
-_ 1
0000 0000
This part of the answer is stored in the H register, so that
the final contents are
H = 00H = 0000 0000 2
L = C8H = 1100 1000 2
12-7 JUMP INSTRUCTIONS
EXAMPLE 12-2
Show a program that subtracts 700 from 900 and stores the
answer in the H and L registers.
SOLUTION
Here are the SAP-2 jump instructions that become part of
the SAP-3 instruction set:
JMP address
JM address
JZ address
JNZ address
(Unconditional jump)
(Jump if minus)
(Jump if zero)
(Jump if not zero)
We need double bytes to represent 900 and 700 as follows: TT „ . ^ „ .
Here are some more SAP-3 jump instructions.
900 10 = 0384H = 0000 0011 1000 0100 2
700 10 = 02BCH = 0000 0010 1011 1100 2 JP
Here’s the program for subtracting 700 from 900:
Label Instruction Comment
MVI A, 84H
SUI BCH
MOV L,A
MVI A, 03H
SBI 02H
MOV H,A
;Load LB of 900
;Subtract LB of 700
;Save lower half answer
;Load UB of 900
;Subtract UB of 700 with borrow
;Save upper half answer
JM stands for jump if minus. When the program encounters
a JM address, it will jump to the specified address if the
sign flag is set.
The JP instruction has the opposite effect. JP stands for
jump if positive (including zero). This means that
JP address
produces a jump to the specified address if the sign flag is
reset.
The first two instructions subtract the lower bytes as follows:
JC and JNC
1000 0100
- 1011 1100
1 1100 1000
The instruction
JC address
202 Digital Computer Electronics
means to jump to the specified address if the carry flag is
set. In short, JC stands for jump if carry. Similarly,
JNC address
means to jump to the specified address if the carry flag is
not set. That is, jump if no carry.
Here is a program segment to illustrate JC and JNC:
Label Instruction Comment
MVI A,FEH
REPEAT: ADI 01H
JNC REPEAT
MVI A,C4H
JC ESCAPE
ESCAPE: MOV L,A
The MVI loads the accumulator with FEH. The ADI adds
1 to get FFH. Since no carry takes place, the JNC takes
the program back to the REPEAT point, where a second
ADI is executed. This time the accumulator overflows to
get contents of 00H with a carry. Since the CY flag is set,
the program falls through the JNC. The accumulator is
loaded with C4H. Then the JC produces a jump to the
ESCAPE point, where the C4H is loaded into the L register.
JPE and JPO
Besides the sign, zero, and carry flag, SAP-3 has a parity
flag designated P. During the execution of certain instruc¬
tions (like ADD, INR, etc.), the ALU result is checked for
parity. If the result has an even number of Is, the parity
flag is set; if an odd number of Is, the flag is reset.
The instruction
JPE address
produces a jump to the specified address when the parity
flag is set (even parity). On the other hand,
JPO address
results in a jump when the parity flag is reset (odd parity).
For instance, given these flags,
S = 1 Z = 0 CY = 0 P = 1
the program would jump if it encountered a JPE instruction;
but it would fall through a JPO instruction.
Incidentally, we now have discussed all the flags in the
SAP-3 computer. For upward compatibility with the 8085
Fig. 12-5 F register stores flags.
microprocessor, these flags are stored in the F register, as
shown in Fig. 12-5. For instance, if the contents of the F
register are
F = 0100 0101
then we know that the flags are
S = 0 Z = 1 P = 1 CY = 1
EXAMPLE 12-3
What does the following program segment do?
SOLUTION
Label Instruction Comment
MVI E,00H ;Initialize counter
LOOP: INR E increment counter
MOV A,E ;Load A with E
CPI FFH ;Compare to 255
JNZ LOOP ;Go back if not 255
The E register is being used as a counter. It starts at 0. The
first time the INR and MOV are executed
A = 01H
After executing the CPI, the zero flag is 0 because 01H
and FFH are unequal. The JNZ then forces the program to
return to the LOOP point.
The looping will continue until the INR and MOV have
been executed 255 times to get
A = FFH
On this pass through the loop, the CPI sets the zero flag
because the accumulator byte and the immediate byte are
equal. With the zero flag set for the first time, the program
falls through the JNZ instruction.
Do you see the point? The computer will loop 255 times
before it falls through the JNZ. One use of this program
segment is to set up a time delay. Another use is to insert
additional instructions inside the loop as follows:
Chapter 12 SAP-3 203
Label Instruction Comment
MVI E,00H
LOOP:
INR E
MOV A,E
CPI FFH
JNZ LOOP
The instructions at the beginning of the loop (symbolized
by dots) will be executed 255 times. If you want to change
the number of passes through the loop, modify the CPI
instruction as required.
12-8 EXTENDED-REGISTER
INSTRUCTIONS
Some SAP-3 instructions use pairs of CPU registers to
process 16-bit data. In other words, during the execution
of certain instructions, the CPU registers are cascaded, as
shown in Fig. 12-6. The pairing is always as shown: B
with C, D with E, and H with L. What follows are the
SAP-3 instructions that use register pairs . Throughout these
instructions, you will notice the letter X, which stands for
extended register, a reminder that register pairs are involved.
B
C
D
E
H
L
Fig. 12-6 Register pairs.
Load Extended Immediate
Since there are three register pairs (BC, DE, and HL), the
LXI instruction can appear in any of these forms:
LXI B,dble
LXI D,dble
LXI H,dble
where B stands for BC
D stands for DE
H stands for HL
dble stands for double byte
The LXI instruction says to load the specified register pair
with the double byte. For instance, if we execute
LXI B,90FFH
the B and C registers are loaded with the upper and lower
bytes to get
B - 90H
C - FFH
Visualizing B and C paired off as shown in Fig. 12-6, we
can write
BC = 90FFH
DAD Instructions
DAD stands for double-add. This instruction has three
forms:
DAD B
DADD
DADH
where B stands for BC
D stands for DE
H stands for HL
The DAD instruction adds the contents of the specified
register pair to the contents of the HL register pair; the
result is then stored in the HL register pair. For instance,
given
BC = F521H
HL - 0003H
the execution of a DAD B produces
HL = F524H
As you see, F521H and 0003H are added to get F524H.
The result is stored in the HL register pair.
The DAD instruction affects the CY flag. If there is a
carry out of the HL register pair, the CY flag is set;
otherwise it is reset. As an example, if
DE = 0001H
HL = FFFFH
a DAD D will result in
HL = 0000H
CY = 1
Incidentally, a DAD H has the effect of adding the data
in the HL register pair to itself. In other words, a DAD H
doubles the value of HL. If
HL = 1234H
204 Digital Computer Electronics
a DAD H results in
HL = 2468H
INX and DCX
INX stands for increment the extended register , and DCX
means decrement the extended register . The extended
increment instructions are
INX B
INX D
INX H
where B stands for BC
D stands for DE
H stands for HL
The DCX instructions have a similar format: DCX B, DCX
D, and DCX H.
The INX and DCX instructions have no effect on the
flags. For instance, if
BC = FFFFH
5 = 1
Z = 0
P = 1
CY = 0
executing an INX B results in
BC = 0000H
S = 1
Z = 0
P = 1
CY = 0
Notice that all flags are unaffected.
In summary, the extended register instructions are LXI,
DAD, INX, and DCX. Of the three register pairs, the HL
combination is special. The next section tells you why.
2050H
(a) (b)
Fig. 12-7 (a) HL pointer; (b) pointing to 2050H.
first memory location is Mqoooh, the next is Mqooih* and so
on. The memory location with address HL is M HL .
With some SAP-3 instructions, the contents of the HL
register pair are used as the address for data in memory.
That is, the contents of the HL register pair are sent to the
MAR, and then a memory read or write is performed. It’s
as though the HL register pair were pointing to the desired
memory location, as shown in Fig. 12-7*2.
For instance, suppose
HL = 2050H
If HL is acting as a pointer, its contents (2050H) are sent
to the MAR during one T state. During the next T state,
the memory location whose address is 2050H undergoes a
read or write operation. As shown in Fig. 12-76 the HL
register pair points to the desired memory location.
12-9 INDIRECT INSTRUCTIONS
As discussed in Chap. 10, the program counter is an
instruction pointer; it points to the memory location where
the next instruction is stored.
The HL register pair is different; it points to memory
locations where data is stored. In other words, SAP-3 has
several instructions where the HL register pair acts like a
data pointer. The following discussion clarifies the idea.
Indirect Addressing
With direct addressing like LDA 5000H and STA 6000H,
the programmer knows the address of the memory location
because the instruction itself directly gives the address.
With instructions that use the HL pointer, however, pro¬
grammers do not know the address; all they know is that
the address is stored in the HL register pair. Whenever an
instruction uses the HL pointer, the addressing is called
indirect addressing.
Visualizing the HL Pointer
Figure 12-7a shows a 64K memory; it has 65,636 memory
registers or memory locations where data is stored. The
Indirect Read
One of the indirect instructions is
MOV reg,M
Chapter 12 SAP-3 205
As another example, if
where reg = A, B, C, D, E, H, or L
M = M hl
This instruction says to load the specified register with the
data addressed by HL. After execution of this instruction,
the designated register contains M HL .
For instance, if
HL = 3000H and M 300 oh = 87H
executing a
MOV C,M
produces
C - 87H
HL = 9850H and M 9850H = CEH
a MOV A,M results in
A = CEH
Figure 12-8 b illustrates the MOV A,M. The HL pointer
points to CEH, which is the data to be loaded into the A
register.
Indirect Write
Here is another indirect MOV instruction:
MOV M,reg
HL
HL
3000H
87H
9850H
CEH
(a) (b)
HL
E300H
F2H
(c)
Fig. 12-8 Examples of indirect addressing.
where M = Mhl
reg = A, B, C, D, E, H, orL
This says to load the memory location addressed by HL
with the contents of the specified register. After execution
of this instruction,
M hl = reg
As an example, if
HL = E300H
B = F2H
the execution of a MOV M,B produces
M E3 ooh = F2H
Figure 12-8c illustrates the idea.
Indirect-Immediate Instructions
Sometimes we want to write immediate data into the memory
location addressed by the HL pointer. The instruction to
use in this case is
MVI M,byte
Here is an example. If HL = 3000H, executing a
MVI M,87H
Figure 12-8 a shows how to visualize the MOV C,M. The produces
HL pointer points to 87H, which is the data to be read into
register C. M 3000H = 87H
206 Digital Computer Electronics
Other Pointer Instructions
Here are more instructions using the HL pointer:
ADD M
ADC M
SUB M
SBBM
INRM
DCRM
ANAM
ORAM
XRAM
CMPM
In each of these, M is the memory location addressed by
HL. Think of M as another register where data is stored.
Each of the foregoing instructions operates on this data as
previously described.
EXAMPLE 12-4
Suppose 256 bytes of data are stored in memory between
addresses 2000H and 20FFH. Show a program that will
copy these 256 bytes at addresses 3000H to 30FFH.
SOLUTION
Label
Instruction
Comment
LXI H,1FFFH
initialize pointer
LOOP:
INX H
;Advance pointer
MOV B,M
;Read byte
MOV A,H
;Load 20H into accumulator
ADI 10H
;Add offset to get 30H
MOV H,A
;Offset pointer
MOV M,B
; Write byte in new location
SUI 10H
; Subtract offset
MOV H,A
; Restore H for next read
MOV A,L
;Prepare for compare
CPI FFH
;Check for 255
JNZ LOOP
;If not done, get next byte
HLT
;Stop
This looping program transfers each successive byte in the
2000H-20FFH area of memory into the 3000H-30FFH area
of memory. Here are the details.
The LXI initializes the pointer with address 1FFFH. The
first time into the loop, the INX will advance the HL pointer
to 2000H. The MOV B,M then reads the first byte into the
B register. The next three instructions
MOV A,H
ADI 10H
MOV H,A
offset the HL pointer to 3000H. Then the MOV M,B writes
the first byte into location 3000H. The next two instructions,
SUI and MOV, restore the HL pointer to 2000H. The MOV
A,L puts 00H into the accumulator. Because the CPI FFH
resets the zero flag, the JNZ forces the program to return
to the LOOP entry point.
On the second pass through the loop, the computer will
read the byte at 2001H and it will store this byte at 3001H.
The looping will continue with successive bytes being
moved from the 2000H-20FFH section of memory to the
3000H-30FFH area. Since the first byte is read from 2000H,
the 256th byte is read from 20FFH. After this byte is stored
at 30FFH, the pointer is restored to 20FFH. The MOV A,L
then loads the accumulator to get
A = FFH
This time, the CPI FFH will set the zero flag. Therefore,
the program will fall through the JNZ to the HLT.
12-10 STACK INSTRUCTIONS
SAP-2 has a CALL instruction that sends the program to a
subroutine. As you recall, before the jump takes place, the
program counter is incremented and the address is saved at
addresses FFFEH and FFFFH. The addresses FFFEH and
FFFFH are set aside for the purpose of saving the return
address. At the completion of a subroutine, the RET
instruction loads the program counter with the return
address, which allows the computer to get back to the main
program.
The Stack
A stack is a portion of memory set aside primarily for
saving return addresses. SAP-2 has a stack because addresses
FFFEH and FFFFH are used exclusively for saving the
return address of a subroutine call. Figure 12-9 a shows
how to visualize the SAP-2 stack.
SAP-3 is different. To begin with, the programmer
decides where to locate the stack and how large to make
it. As an example, Fig. 12-9 b shows a stack between
addresses 20E0H and 20FFH. This stack contains 32
memory locations for saving return addresses. Programmers
can locate the stack anywhere they want in memory, but
once they have set up the stack, they no longer use that
portion of memory for program and data. Instead, the stack
becomes a special space in memory, used for storing the
return addresses of subroutine calls.
Stack Pointer
The instructions that read and write into the stack are called
stack instructions; these include PUSH, POP, CALL, and
Chapter 12 SAP-3 207
(a) (b)
Fig. 12-9 (a) SAP-2 stack; ( b ) example of a stack; (c) stack
pointer addresses the stack; (d) SP points to 20FFH.
others to be discussed. Stack instructions use indirect
addressing because a 16-bit register called the stack pointer
(SP) holds the address of the desired memory location. As
shown in Fig. 12-9c, the stack pointer is similar to the HL
pointer because the contents of the stack pointer indicate
which memory location is to be accessed. For instance, if
SP = 20FFH
the stack pointer points to memory location M 20 ffh ( see
Fig. 12-9 d). Depending on the stack instruction, a byte is
then read from, or written into, this memory location.
To initialize the stack pointer, we can use the immediate
load instruction
LXI SP,dble
For instance, if we execute
LXI SP,20FFH
the stack pointer is loaded with 20FFH.
PUSH Instructions
The contents of the accumulator and the flag register are
known as the program status word (PSW). The format for
this word is
PSW = AF
where A = contents of accumulator
F = contents of flag register
The accumulator contents are the high byte, and the flag
contents the low byte. When calling subroutines, we usually
have to save the program status word, so that the main
208 Digital Computer Electronics
fc) id)
program can resume after the subroutine is executed. We
may also have to save the contents of the other registers.
PUSH instructions allow us to save data in a stack. Here
are the four PUSH instructions:
PUSH B
PUSH D
PUSH H
PUSH PSW
where B stands for BC
D stands for DE
H stands for HL
PSW stands for program status word
When a PUSH instruction is executed, the following things
happen:
1. The stack pointer is decremented to get a new value
of SP - 1.
2. The high byte in the specified register pair is stored in
Msp- l*
3. The stack pointer is decremented again to get SP —
2 .
4. The low byte in the specified register pair is stored in
Msp - 2*
Here is an example. Suppose
BC = 5612H
SP = 2100H
When a PUSH B is executed,
1. The stack pointer is decremented to get 20FFH.
2. The high byte 56H is stored at 20FFH (Fig. 12-10 g).
3. The stack pointer is again decremented to get 20FEH.
4. The low byte 12H is stored at 20FEH (Fig. 12-10 b).
20FAH
20FBH
20FCH
20FDH
20FEH
20FFH
20FAH
20FBH
20FCH
20FDH
20FEH
20FFH
(c) (d)
Fig. 12-10 Push operations: (a) high byte first; (b) low byte
second; (c) 6 bytes pushed on stack; (d) popping a byte off the
stack; ( e ) incrementing stack pointer.
20FAH
20FBH
20FCH
20FDH
20FEH
20FFH
( e. I
Here’s another example. Suppose
SP = 2100H
AF = 1234H
DE = 5678H
HL = 9A25H
then executing
PUSH PSW
PUSH D
PUSH H
loads the stack as shown in Fig. 12-10c. The first PUSH
stores 12H at 20FFH and 34H at 20FEH. The next PUSH
stores 56H at 20FDH and 78H at 20FCH. The last PUSH
stores 9AH at 20FBH and 25H at 20FAH. Notice how the
stack builds. Each new PUSH shoves data onto the stack.
POP Instructions
Here are four POP instructions:
POP B
POP D
POPH
POP PSW
where B stands for BC
D stands for DE
H stands for HL
PSW stands for program status word
Chapter 12 SAP-3 209
When a POP is executed, the following happens:
1. The low byte is read from the memory location
addressed by the stack pointer. This byte is stored in
the lower half of the specified register pair.
2. The stack pointer is incremented.
3. The high byte is read and stored in the upper half of
the specified register pair.
4. The stack pointer is incremented.
Here’s an example. Suppose the stack is loaded as shown
in Fig. 12-10c with the stack pointer at 20FAH. Then
execution of POP B does the following:
1. Byte 25H is read from 20FAH (Fig. 12-10c) and stored
in the C register.
2. The stack pointer is incremented to get 20FBH. Byte
9AH is read from 20FBH (Fig. 12-10 d) and stored in
the B register. The BC register pair now contains
BC = 9A25H
3. The stack pointer is incremented to get 20FCH (Fig.
12-10c).
Each time we execute a POP, 2 bytes come off the stack.
If we were to execute a POP PSW and a POP H in Fig.
12-10c, the final register contents would be
AF = 5678H
HL - 1234H
and the stack pointer would contain
SP = 2100H
CALL and RET
The main purpose of the SAP-3 stack is to save return
addresses automatically when using CALLs. When a
CALL address
is executed, the contents of the program counter are pushed
onto the stack. Then the starting address of the subroutine
is loaded into the program counter. In this way, the next
instruction fetched is the first instruction of the subroutine.
On completion of the subroutine, a RET instruction pops
the return address off the stack into the program counter.
Here is an example:
Address Instruction
2000H LXI SP,2100H
2001H
2002H
Address
Instruction
2003H
CALL 8050H
2004H
2005H
2006H
MVI A,0EH
20FFH
HLT
8050H
8059H
RET
To begin with, LXI and CALL instructions take 3 bytes
each when assembled: 1 byte for the op code and 2 for the
data. This is why the LXI instruction occupies 2000H to
2002H and the CALL occupies 2003H to 2005H.
The LXI loads the stack pointer with 2100H. During the
execution of CALL 8050H, the address of the next instruc¬
tion is saved in the stack. This address (2006H) is pushed
onto the stack in the usual way; the stack pointer is
decremented and the high byte 20H is stored; the stack
pointer is decremented again, and the low byte 06H is
stored (see Fig. 12-1 la). The program counter is then
loaded with 8050H, the starting address of the subroutine.
When the subroutine is completed, the RET instruction
takes the computer back to the main program as follows.
First, the low byte is popped from the stack into the lower
half of the program counter; then the high byte is popped
from the stack into the upper half of the program counter.
(a) (b)
Fig. 12-11 (a) Saving a return address during a subroutine call;
(b) popping the return address during a RET.
210 Digital Computer Electronics
After the second increment, the stack pointer is back at
2100H, as shown in Fig. 12-11 b.
The stack operation is automatic during CALL and RET
instructions. All we have to do is initialize the setting of
the stack pointer; this is purpose of the LXI SP,dble
instruction. It sets the upper boundary of the stack. Then a
CALL automatically pushes the return address onto the
stack, and a RET automatically pops this return address off
the stack.
Conditional Calls and Returns
Here is a list of the SAP-3 conditional calls:
CNZ address
CZ address
CNC address f
CC address
CPO address
CPE address " 4
CP address ^ r
CM address
They are similar to the conditional jumps discussed earlier.
The CNZ branches to a subroutine only if the zero flag is
reset, the CZ branches only if the zero flag is set, the CNC
branches only if the carry flag is reset, and so forth.
The return from a subroutine may also be conditional.
Here is a list of the conditional returns:
RNZ
RZ
RNC
RC
RPO
RPE
RP
RM
The RNZ will return only if the zero flag is reset, the RZ
returns only when the zero flag is set, the RNC returns
only if the carry flag is reset, and so on.
EXAMPLE 12 5
SAP-3 has a clock frequency of 1 MHz, the same as SAP-
2. Write a program that provides a time delay of approxi¬
mately 80 ms.
SOLUTION
Label
Mnemonic
Comment
LXI SP,E000H
initialize stack pointer
MVI E,08H
initialize counter
LOOP:
CALL F020H
;Delay for 10 ms
DCR E
;Count down
JNZ LOOP
HLT
;Test for 8 passes
You almost always use subroutines in complicated programs;
this means that the stack will be used to save return
addresses. For this reason, one of the first instructions in
any program should be a LXI SP to initialize the stack
pointer.
The 80-ms time delay program shown here starts with a
LXI SP,E000H. This implies that the stack grows from
address DFFFH toward lower memory. In other words, the
stack pointer is decremented before the first push operation;
this means that the stack begins at DFFFH.
The remainder of the program is straightforward. The E
register is used as a counter. The program calls the 10-ms
time delay 8 times. Therefore, the overall time delay is
approximately 80 ms.
GLOSSARY
data pointer Another name for the HL register pair because
some instructions use its contents to address the memory.
extended register A pair of CPU registers that act like a
16-bit register with certain instructions.
indirect addressing Addressing in which the address of
data is contained in the HL register pair.
overflow A sum or difference that lies outside the normal
range of the accumulator.
pop To read data from the stack.
push To save data in the stack.
stack A portion of memory reserved for return addresses
and data.
stack pointer A 16-bit register that addresses the stack.
The stack pointer must be initialized by an LXI instruction
before calling subroutines.
Chapter 12 SAP-3 211
SELF-TESTING REVIEW
Read each of the following and provide the missing words.
Answers appear at the beginning of the next question.
1. An_is a sum or difference that lies out¬
side the normal range of the accumulator. One way
to detect an overflow is with the-flag.
2. ( overflow , carry ) To reset the carry flag, you may
use an_followed by a CMC. STC stands
for_the carry flag.
3. (STC, set) The ADC instruction adds the-
flag and the contents of the specified register to the
contents of the_SBB stands for subtract
with-
4. (carry, accumulator, borrow) The RAL rotates all
bits to the_with CY going to the LSB.
RRC rotates the accumulator bits to the right with the
LSB going to the carry flag.
5. (left) The CMP instruction compares the contents of
the designated register with the contents of the accu¬
mulator. If the two are equal, the zero flag is
_The CPI compares an immediate byte to
the contents of the-
6. (set, accumulator) JM stands for jump if-
. The program will branch to a new address if the
_flag is set. JNZ means jump if not zero.
With this instruction, the program branches only if
the_flag is reset.
7. (minus, sign, zero) The LXI instruction is used to
load register pairs. B is paired off with C, D with E,
and H with_The HL register pair acts
like a_pointer with some instructions.
This type of addressing is called-
8. (L, data, indirect) The stack is a portion of memory
reserved primarily for return addresses. The stack
pointer is a 16-bit register that addresses the stack. It
is necessary to initialize the stack pointer before
calling any subroutines.
PROBLEMS
12-1. Write a program that adds decimal 345 and 753.
(Use immediate bytes for the data.)
12-2. Write a program that subtracts decimal 456 from
983. (Use immediate data.)
12-3. Suppose that 1,024 bytes of data are stored be¬
tween addresses 5000H and 53FFH. Write a pro¬
gram that copies these bytes at addresses 9000H
to 93FFH.
12-4. Show a program that provides a delay of approxi¬
mately 35 ms. If you use the SAP subroutines of
Chap. 11, start your program with LXI SP,E000H
12-5. Write a program that sends 1, 2, 3, ... , 255 to
port 22 with a time delay of 1 ms between OUT
22 instructions. (Use a LXI SP,E000H and a
CALL F010H.)
12-6. Bytes arrive a port 21H at a rate of approximately
1 per millisecond. Write a program that inputs
256 bytes and stores them at addresses 8000H to
80FFH. (Use CALL F010H.)
12-7. Suppose that 512 bytes of data are stored at ad¬
dresses 6000H to 61FFH and write a program that
outputs these bytes to port 22H at a rate of ap¬
proximately 100 bytes per second. (Use CALL
F020H.)
12-8. A peripheral device is sending serial data to bit 7
of port 21H at a rate of 1,000 bits per second.
Write a program that converts any 8 bits in the
serial data stream to an 8-bit parallel word, which
is then sent to port 22H. (Use CALL F010H.)
12-9. Suppose that 256 bytes are stored at addresses
5000H to 50FFH and write a program that con¬
verts each of these bytes into a serial data stream
at bit 0 of port 22H. Output the data at a rate of
approximately 1,000 bits per second. (Use CALL
F010H.)
212
Digital Computer Electronics
PART 3
PROGRAMMING POPULAR
MICROPROCESSORS
Introduction to Microprocessors
This part of the text is designed to introduce you to some
of the more popular microprocessors. The design and
operation of a microprocessor are based on the digital
circuits which you studied in Part 1.
You will learn the basic principles of microprocessors
and how to write simple assembly language programs. In
the study of computers, programming, and microprocessors,
one fundamental idea emerges:
If you do correctly a great number of
very simple tasks, you will have done
something complicated.
If you understand the basic principles and simple programs
presented here, you will be on your way to understanding
more complicated ideas.
Since the microprocessor is a “computer on a chip,” it
may help to take a quick look at computers before stalling
to study microprocessors.
13-1 COMPUTER HARDWARE
The digital circuits you studied in the first part of this text
are the building blocks of a computer. In the early days of
computers, digital circuits were made by using vacuum
tubes and later were built with transistors. Circuits were
designed which would act as the “brain” of a computer.
These circuits were called the central processing unit (CPU).
The CPU could perform basic arithmetic operations such
as addition and subtraction, logic operations such as ANDing
and ORing, and control operations. Thus it could process
data.
A CPU cannot be used alone. There are other components
which are needed to make a computer. For example, we
said that a CPU can process data. Where is this data? We
need memory—a place where data can be stored until the
CPU needs it. And what if the CPU does a calculation and
comes up with an answer? How would we know what the
Fig. 13-1 A simplified overview of a microprocessor
system.
answer is? We need a way for the CPU to communicate
with us. We need an output device. Figure 13-1 illustrates
what a simple system looks like.
13-2 DEFINITION OF A
MICROPROCESSOR
What exactly is a microprocessor? As the name implies, it
must be small (micro-) and it must be able to process data
(-processor). A microprocessor is a CPU which is con¬
structed on a single silicon chip. What, then, is a CPU? A
CPU is an electronic circuit which can interpret and execute
instructions and control input and output.
In this text, when reference is made to a microprocessor,
only the microprocessor is being referred to. However, if
reference is made to a computer, then we are talking about
a device which contains a microprocessor and several
subsystems. Figure 13-2 serves to illustrate this.
13-3 SOME COMMON USES FOR
MICROPROCESSORS
Microprocessors can be found in a variety of products.
Some well-known examples are computers and industrial
controls. Some not-so-obvious products that use micropro-
213
Fig. 13-2 Block diagram of a complete computer and
peripherals.
cessors include answering machines, compact disk players,
and automobiles.
The microprocessor supplies electronic products with a
new dimension. In the past, electronic products have been
able to make simple decisions because of certain kinds of
circuitry and/or sensors. The microprocessor, however, has
multiplied this trait many times: Some devices, most notably
computers, now almost appear to think.
13-4 MICROPROCESSORS
FEATURED IN THIS TEXT
It is the purpose of this book to examine the most popular
8-bit microprocessor families in addition to the 16-bit Intel
8086-8088 family.
6502 Family
The 6502 family is supported by this text. The 65C02, an
advanced version of the 6502 which is used in the Apple
lie, has some additional instructions and enhanced features
which can be found in the manufacturer’s programming
manuals.
6800 Family
The 6800/6808 is supported by this text. The 6809 is an
enhanced version of the 6800. It understands all the
instructions of the 6800 and includes some other advanced
features.
8080/8085/Z80 Family
The 8080, 8085, and Z80 are also supported in this text.
The 8080 and 8085 have exactly the same instruction set
except for two additional instructions included in the 8085.
The Z80 understands all the 8080/8085 instructions and has
many other additional instructions.
Only those instructions common to all three micropro¬
cessors are discussed in this text. (The extended Z80
instructions are not used in the text.) This has the advantage
of making it possible for students to use a mixture of 8085
and Z80 microprocessor trainers in the same class at the
same time with all students on equal footing and with a
minimum of confusion. Either Z80 or 8085 mnemonics can
be used interchangeably for the homework problems and
the object code will be the same.
8086/8088 Family
The Intel 8086/8088 is the only 16-bit microprocessor
discussed in this text. This microprocessor (in addition to
the 80286, 80386, and 80486) is used in the popular IBM
PCs, IBM compatibles, and clones. The DOS DEBUG
utility is used throughout the text. Assemblers are introduced
in later chapters.
13-5 ACCESS TO
MICROPROCESSORS
Developing skill in programming and interfacing micropro¬
cessors requires access to a microprocessor. Here are some
ways to gain access to a microprocessor supported by this
text.
Computers
The 6502 or one of its derivatives can be found in the entire
line of Commodore computers including the PET, Vic-20,
C-64, C-16, Plus-4, and C-128. They can also be found in
the Apple II line of computers including the Apple II, II + ,
lie, lie, and lie + . They are also included in that portion of
the Laser line of computers that are Apple-compatible, in¬
cluding the Laser 128, Laser 128 EX, and Laser 128 EX/2.
And last of all, some of the older Atari home computers
contain this type of microprocessor.
The 8085 and Z80 can be found in some of the older
CP/M machines. (CP/M stands for control program for
microprocessors.) The Z80 was used in Radio Shack’s
TRS-80 line of computers and is also found in the Com¬
modore 128 (the Commodore 128 contains two micropro¬
cessors). The Commodore 128 will also run CP/M software
if that is desired.
The 8086/8088 are found in all of the IBM PCs and XTs,
IBM compatibles, and clones. The 80286 is used in AT-
class machines, and of course the 80386 is used in the
newer 386s. These microprocessors use a superset of the
8086/8088 instructions set and can therefore also be used
with this text.
214 Digital Computer Electronics
Some IBM compatibles use the NEC-V20 or one of the
other NEC microprocessors. These are compatible with the
Intel series of microprocessors and will work equally well.
Microprocessor Trainers
Another way to gain access to a microprocessor supported
by this text is through the use of a microprocessor trainer.
Heathkit’s ET-3400-A trainer contains a 6808 chip. E&L
Instruments has the “FOX” (MT-80Z) with a Z80 micro¬
processor. Intel makes the SDK-85, which features the
8085 chip, and the SDK-86, which uses the 8086. Motorola
makes the MEK6800D with a 6800 chip.
Software Emulation Programs
Finally, there are software emulation programs that will
make a computer act as though it is using another micro¬
processor.
Chapter 13 Introduction to Microprocessors 215
Programming and Languages
What is a program and why do we need one? What do we
mean by program design? What is a programming lan¬
guage? Why do we need a language? What is a flowchart?
How does all of this relate to electronics and digital circuits?
These are some of the questions we will try to answer in
this chapter.
14-1 RELATIONSHIP BETWEEN
ELECTRONICS AND PROGRAMMING
A question sometimes raised by electronics students is,
“Why are we learning about programming microproces¬
sors?”
Programming is a topic which is closely related to
electronics. Mathematics and physics are topics which
support or undergird the subject of electronics. They form
a foundation. Programming is not so much a support subject
as it is a related subject. Let’s take a closer look at this.
Digital Electronics and Microprocessors
What prompted the creation of digital electronics? It was
the desire to make a machine without moving parts which
could perform mathematical calculations. Such a machine
would be much faster than any mechanical calculator.
Correctly connecting enough digital logic circuits together
created such a machine.
Once the calculating machine had been built, there had
to be a way to tell this machine to add, or subtract, or
perform some logical operation. Thus programming was
born. We simply needed a way to tell the machine what to
do. In the beginning, programming was done by connecting
wires or patch cords. This was very slow compared to what
we do today.
Over the years digital circuits became more complex,
the calculating machine grew into far more than just a big
calculator, and the need for ways to communicate with the
machine grew. Finally, it became possible to put the entire
computer “brain” on a single chip.
Until this point an electronics technician might never
work on or even see a computer. However, when the
“brain” could be put on a chip, and the cost was measured
in dollars rather than thousands of dollars, its possibilities
became endless.
Designers and engineers realized that these “brains,” or
microprocessors, could improve the performance of many
common electronic products and could make new products
economically possible. With microprocessors everywhere,
the electronics technician can no longer be unaware of their
operation.
The Electronic Technician and Programming
So why should a technician learn about programming?
Because the technician will probably eventually work on
products with microprocessors, and the microprocessor
cannot be separated from its program. A microprocessor
without a program would be like a resistor with no resistance
or a wire with no conductivity. Without the program, a
microprocessor does nothing.
Programming is now part of the overall picture that
electronics is concerned with—like mathematics and phys¬
ics. Some technicians will not need as much knowledge
about programming as others: It depends on what your
career field is. But everyone should at least be aware of
the basics.
The goal of this book is to provide the digital understand¬
ing and programming experience which would be appro¬
priate for the “typical” electronics student.
14-2 PROGRAMMING
In everyday language:
A program is a very detailed list of steps which
must be followed to accomplish a certain task.
216
A Familiar Example
We have all used this concept of programming—of follow¬
ing specific steps to accomplish a certain task—but have
probably not thought of it in these terms. Let’s look at
something like taking a city bus downtown. You would be
likely to
1. Wear clothes appropriate for the weather that particular
day.
2. Take some money or tickets.
3. Go to a nearby bus stop.
4. Wait for the correct bus.
5. Get on.
6. Pay the driver.
7. Sit down if there were empty seats available.
8. Wait until the bus arrived in the area you wished to
go to.
9. Alert the driver you wished to get off.
10. Wait for the bus to stop.
11. And finally get off.
Figure 14-1 is a flowchart (we’ll talk about flowcharts in
just a minute) of this process.
Unless this was your first time riding a bus, you wouldn’t
think about every detail because much of it is understood
and is a natural part of your life. You usually dress for the
weather when you go outside, and you usually take money
when you go places. With a computer, though, things are
different.
Very little is “natural” for a computer. The micropro¬
cessor has several temporary storage places where numbers
can be kept (called registers). The machine can add and
subtract, it can and and or, it can move numbers from one
register to another, and it can do other simple things, but
everything must be specified! One of the things that often
surprises people learning to program microprocessors is the
amount of detail which is necessary when writing a program.
Fig. 14-1 Flowchart of a bus ride.
Chapter 14 Programming and Languages 217
14-3 FUNDAMENTAL PREMISE
Before we look further at the subject of programming and
flowcharts, we need to discuss a fundamental concept of
programming. The concept is this:
You cannot program the computer to do
something you don’t know how to do.
If you use computers only with application software (spread¬
sheets, word processors, and so on), this may not always
be true, but if you want to program microprocessors, it is.
Before you begin to think about how you will program a
computer to do something, think about how you would do
it yourself without a computer. After you know how you
would do it, you can begin to tell the computer how it
should do it.
14-4 FLOWCHARTS
When you are writing a program, it helps to have an
organized way to write or express the flow of the program’s
logic. A flowchart is one way to do this.
Fig. 14-3 Straight-line program to calculate sales tax and
display total cost for one item.
Flowchart symbols
Figure 14-2 shows some common flowchart symbols. There
are others, but we’ll need only a few for most of the
programs we’ll be writing.
Straight-Line Programs
The simplest type of program is the straight-line program .
In this type of program the steps involved follow each
other, one after another, without any alternate routes or
paths. Figure 14-3 is an example of a straight-line program.
This program is similar to one that might be used at the
cash register of a store. It allows you to enter the price and
product code of one item. The program then calculates a 5
percent sales tax, adds the tax to the original price to arrive
at a total, and finally displays the total cost. The program
will accept only one item, which means that it would have
to be “run” again to find the total cost of a second item.
Since we often buy more than one item at a time, let’s look
at another flowchart.
Looping
A loop is a section of a program which will repeat over
and over again. We can make the loop repeat indefinitely,
or make it stop after a certain number of repetitions, or
make it stop when some condition is met. Look at Fig.
14-4 and compare it to Fig. 14-3.
Fig. 14-4 Sales-tax program with loop.
2 18 Digital Computer Electronics
These are almost identical, aren’t they? What do you
think this program will do that the one in Fig. 14-3 didn’t?
The answer, of course, is that this program is ready to
accept a new number immediately after displaying the
previous total. After you enter an item’s price, the total
cost is shown on the screen and the program then waits for
you to enter the price of the next item.
Loops make it easier for programs to perform repetitive
tasks. The program that uses loops can do the same
calculations or functions over and over again.
Branching
Sometimes we want the computer program to do different
things based on the situation at the time or based on the
results of certain operations. We need a way to branch off
from the main program flow. Branching allows us to write
one program that can do different things at different times.
Let’s look at the sales-tax situation again. Study Fig. 14-5
at this time. This new version of the sales-tax program has
a branch and a decision symbol.
Let s look at the decision symbol (diamond). If the
program is to be able to take an alternate path when certain
conditions exist, we must give it a chance to check for
those conditions. The decision diamond represents that
time. If the item is a nonfood item, it will be taxed as
usual, and the program flow continues downward. If it is
Fig. 14-5 Sales-tax program with loop and branch for non-
taxable food items.
a food item which is not to be taxed, then we take the
branch. The branch doesn’t actually say not to tax the food
item. But by making the total cost equal to the original
price and bypassing the tax calculation section, we have
effectively done the same thing. The total that appears will
be the same as the original price, and the program will then
loop back to the beginning to wait for the next item.
Subroutines
Sometimes we need to have the computer program take
care of some intermediate task before it can continue with
the main job at hand. We don’t want it to branch and then
end up somewhere else after the branch is finished. Rather,
we want it to go to an intermediate task and then come
right back to where it was before it left. This is called a
subroutine . Looking at a subroutine will help clarify this
new concept. Figure 14-6 shows our new program.
Everything is the same as in the last (Fig. 14-5) program
except that we have added a subroutine which handles
inventory. This subroutine is really just another small
program that works along with the main one. It reduces the
inventory total for this particular item by 1. If this total is
less than 10, then it’s time to order more. Either way, the
subroutine prints a line on a printer in the administrative
office with the product code and name of the product. We
then return ’ from the subroutine to the main program and
continue where we left off.
Calling Subroutines
The act of going to a subroutine is often referred to as
calling a subroutine, at the end of which we return to the
main program.
The greatest advantage in having subroutines is not in
calling or using them once but in using them several times
in a program. You write that part of the program only once,
but you can use it many times. Figure 14-7 illustrates this.
In Fig. 14-7 the boxes are not process boxes but rather
representations of certain parts or modules of the whole
computer program.
In this hypothetical situation there may be times when
merchandise needs to be ordered other than w'hen inventory
drops below 10. For example, if a clerk finds a piece of
merchandise damaged too badly to sell at a reduced price,
it may simply be disposed of; however, it must be replaced
to keep inventory up. The “damaged merchandise” part of
the program can then call the “inventory-ordering subrou¬
tine” at some point.
Likewise, the store might sometimes give food or clothing
to charity. This part of the program might also call the
inventory-ordering subroutine to replace that merchandise.
This store’s computer program uses the same subroutine
in three different situations, but the programmer had to
write the subroutine only once.
Chapter 14 Programming and Languages 219
Fig. 14-6 Sales-tax program with inventory control
reordering subroutine.
14-5 PROGRAMMING LANGUAGES
Price entry
part of
program
Damaged-
merchandise
reporting
part of program
Charities
bookkeeping
part of
program
Inventory¬
reordering
subroutine
Fig. 14-7 Repetitive calling of inventory-reordering
subroutine.
Now that we can define and flowchart the desired process,
we need to be able to communicate this process to the
computer. We need a language which the computer under¬
stands. Many languages have been developed for use with
computers.
Machine Language
There is only one language the computer actually under¬
stands, and that is machine language, which consists of Is
and Os. This binary language is fine for the computer but
not for people. To have to communicate with the computer
in binary, you would place in its memory a series of
numbers that might look like this:
10010100
01001010
11101110
00101001
It would be nearly impossible to remember what the many
different patterns of Is and 0s meant, and the probability
of making a mistake would be very high. Something better
is needed.
220 Digital Computer Electronics
Assembly Language
The first step toward a language that is easier for people to
work with uses abbreviations to stand for different opera¬
tions. For example, the instruction which tells a 6800
microprocessor to add numbers is the ADDA instruction,
which stands for ADD accumulator A to a memory location.
This “language” of abbreviations is called assembly
language. The “abbreviations” are called mnemonics. A
mnemonic (pronounced ne-'man-ik) is something that aids
the memory. Mnemonics are designed to be easy to re¬
member and are a significant improvement over binary
digits.
Machine language and assembly language are the subjects
of this book. We refer to them as low-level languages
because only very simple instructions exist.
High-level languages
In-between languages
Low-level languages
Fig. 14-8 Some examples of high-level, low-level, and in-
between languages.
High-Level Languages
Over the course of time, people working with computers
felt it would be helpful to create languages that were more
like English, so that it would not be so difficult to
communicate with the computer and so that more advanced
commands could be created. We call these high-level
languages .
For example, many microprocessors do not have the
ability to multiply or divide. It is obvious, however, that
these are common mathematical functions that must be
available to a computer programmer. In machine or assembly
language one can use repeated additions to multiply or
repeated subtractions to divide. This is not necessarily the
best way to multiply or divide, but it is one way. In a high-
level language there are “multiply” and “divide” com¬
mands. The language knows how to create the multiply and
divide functions even though the microprocessor does not
have these functions built in. In fact, these languages can
understand English commands like print , run, do, next ,
and end. The microprocessor does not understand these
English words, but the language changes (interprets or
compiles) them into machine language before sending them
to the microprocessor.
Many high-level languages have been created over the
years. FORTRAN (formula tran slation) is a language that
handles high-level mathematics very well and is designed
for scientists and engineers. COBOL, which stands for
common business-oriented language, is tailored to the needs
of business. BASIC, which stands for beginner’s all-purpose
symbolic instruction code, was designed to be easy for
nonprofessional programmers to learn and use. Pascal,
named for the French mathematician Blaise Pascal, is
designed to encourage the programmer to adhere to what
are considered “correct” programming practices.
There are some languages that are somewhat “in be¬
tween’ ’ the high-level and low-level languages, most notably
C and FORTH. Figure 14-8 illustrates this.
14-6 ASSEMBLY LANGUAGE
Let’s look at the subject of assembly-language programming
in a little more detail.
Machine language is the language the computer under¬
stands, but it is difficult for people to work with. Assembly
language gives us the advantages of machine language
without the disadvantage of doing something that seems so
unnatural.
When we write in assembly language, we use abbrevi¬
ations called mnemonics for certain operations or functions.
The assembly language is called source code. It is more
like English than machine language. The microprocessor,
however, cannot act upon or execute mnemonics. It doesn’t
understand mnemonics. We need to convert the assembly
language or source code into machine language or object
code. There are a couple of ways to do this.
Manual Assembly
Let’s look at manual assembly first. When using this
technique, you write your program on paper using mne¬
monics. Then you look up each mnemonic on a chart. On
the chart there will be a number which is the machine-
language code for the assembly-language mnemonic. You
then write down this object code so that you can later key
it into the microprocessor trainer or computer. This is called
manual assembly because you must look up the codes
yourself.
Assembly with an Assembler or Monitor
The other way to create machine-language object code from
assembly-language source code is through the use of a
monitor or assembler. Since manual assembly involves
simply looking up mnemonics on a chart, it seems reasonable
that the chart could be stored in a computer and the computer
Chapter 14 Programming and Languages 222
could look up the mnemonics and find their corresponding
object code. Though there is much more to a fairly
sophisticated assembler or monitor, this is the basic idea.
A monitor is a program that is normally stored in ROM
and gives you access to the microprocessor’s various
registers. It sometimes has in it a simple assembler to
change mnemonics into machine code and a disassembler
to change machine code back into mnemonics.
An assembler program is usually more sophisticated than
a monitor and has features that are difficult to explain at
this point, but suffice it to say they are for more serious
programming than the monitor. A longer period of time is
required to become skilled in the use of an assembler, but
it is a more powerful tool.
14-7 WORKSHEETS
During the remainder of this book you will be writing
assembly-language programs. In addition to the flowchart,
the worksheet is a tool which helps you stay organized as
you write programs. The worksheet is simply a form on
which you can write your program. It is laid out in such a
way that it’s a little easier to stay neat. Figure 14-9 is a
portion of such a worksheet.
Name_
Program name.
Date_
Sheet _ of
Address
Obj code
Labe!
Mnemonic
Operand/Addr
Comment
Fig. 14-9 Example of a portion of a worksheet.
GLOSSARY
assembler A program which translates assembly language
mnemonics into binary patterns (machine language).
assembly language A low-level language which uses
mnemonics in place of binary patterns (machine language).
branch A section of a program which causes different
actions to be taken based on conditions.
disassembler A program which translates binary patterns
(machine language) into assembly language mnemonics.
loop A section of a program which will repeat over and
over again.
mnemonic Something that aids the memory. Assembly
language uses mnemonics, which are abbreviations for
machine-language instructions.
monitor A program (usually stored in ROM) which gives
the programmer access to the microprocessor’s stack,
accumulator, registers, and so forth. It sometimes contains
a simple assembler.
straight-line program A program in which each step is
followed by the next without any alternate routes or paths.
subroutine A portion of the program which is called upon
to perform a specific task. When the task is finished, the
main part of the program is returned to.
SELF-TESTING REVIEW
Read each of the following and provide the missing words.
Answers appear at the beginning of the next question.
1. Without a_, a microprocessor does noth¬
ing.
2. ( program ) A_is a very detailed list of
steps which must be followed to accomplish a certain
task.
3. ( program ) What is the shape of the decision symbol?
222 Digital Computer Electronics
4. (Diamond) -make programs more practi¬
cal for doing repetitive tasks.
5. (Loops) The only language a computer actually un¬
derstands is__ language.
6. (machine) What does COBOL stand for?
7* (Common business-oriented language) A program in
which the steps involved occur one after the other
without any alternate paths is called a_
program.
8. (straight-line) A section of a program which repeats
indefinitely, a certain number of times, or while or
until a certain condition exists is called a_
(loop)
PROBLEMS
14-1. If you want to write a program to do something,
what should you think about before you try to
figure out what computer instructions to use?
14-2. What is the shape of the process symbol?
14.3. What provides an alternate path for program
flow based on certain conditions?
14-4. What allows program execution to go to an in¬
termediate task and then return to the place
where it was before it started the intermediate
task?
14-5. What is one of the advantages of using subrou¬
tines?
14-6. What is assembly language?
14-7. What does FORTRAN stand for?
14-8. What does BASIC stand for?
14-9. What was one of the goals of the creator of the
Pascal language?
14-10. What does an assembler translate source code
(mnemonics) into?
Chapter 14 Programming and Languages 223
System Overview
New Concepts _
We’ll begin this chapter by reviewing computer architecture.
Then we’ll spend the greater part of the chapter looking at
microprocessor architecture in general and at the architecture
of the microprocessor families supported by this text in
particular.
15-1 COMPUTER ARCHITECTURE
Let’s review computer architecture a little. Refer to Fig.
15-1.
Memory
We said that memory was needed so that there would be a
place for data and instructions to be stored. Data and
instructions which can be lost after power is removed are
stored in RAM (random-access memory). Data and instruc¬
tions which must never be lost, even after the power is
turned off, are stored in ROM (read-only memory). Re¬
member that ROM is a type of memory which cannot have
its contents changed once the ROM chip is manufactured.
PROM and EPROM are used in much the same way as
ROM but can be programmed after being manufactured
(PROM) or even programmed more than once (EPROM).
PROM and EPROM differ from RAM in that they require
special equipment to program them.
When we refer to memory in this text, we will usually
be referring to RAM.
Addressing
Since there are many memory locations, it is necessary to
have a means of referring to specific locations. This is done
through addressing. Typically, memory locations are num¬
bered from 0000 (in hexadecimal numbering) to the highest
location used by that particular trainer or computer. This
sequential number which is assigned to each location is its
address. See Fig. 15-2.
A memory address is similar to the address of your home.
Your house has a number or address assigned to it, and no
other house on your street can have the same address. Inside
your house are its contents; chairs, beds, and so on. Notice
Fig. 15-1 Block diagram of a complete computer with
peripheral devices. (Arrows indicate data flow.)
Addresses
Memory
0000
Contents
0001
Contents
0002
Contents
0003
Contents
0004
Contents
0005
Contents
0006
Contents
0007
Contents
Fig. 15-2 Memory addressing.
that your home’s address and your home’s contents are not
the same.
Each memory location has an address and contents. The
address is necessary to specify which memory location to
read information from or write information into. The
contents is the information itself.
Address Bus
Most microprocessors can store information and instructions
in a wide range of memory locations. Usually the memory
locations are in a memory chip rather than in the micro¬
processor. The microprocessor needs a way to tell the
memory chip which memory location it wants to put data
into or take data from. It does this through the address bus.
See Fig. 15-3.
The address bus is a communications link between the
microprocessor and the memory chips. Physically, it is
simply a group of electrical paths which are connected to
RAM, ROM, and the I/O chips. Through this bus the
microprocessor can specify the address of any memory
location in any chip or device. Notice in Fig. 15-3 that
information travels on the address bus in only one direction,
from the microprocessor to memory and I/O. There are
more details involved, but this is the basic idea.
Data Bus
Once the microprocessor has specified which memory-
location or device it wants to put data into or take data
from, it then needs a set of electrical paths for this
information to travel on. This set of paths is called the data
bus .
It is this set of electrical paths that allows data to flow
from one chip to the next. Notice in Fig. 15-3 that
information on the data bus travels both to and from the
microprocessor, memory, and I/O devices. Eight-bit mi¬
croprocessors have a data bus that is 8 bits wide; 16-bit
microprocessors have a data bus that is 16 bits wide. That
is, the bus consists of 8 or 16 parallel connecting paths.
Addressing Range
Let’s look at the normal range of addresses possible with
8-bit computers at this time.
In earlier chapters you studied the binary number system
and learned that each position represents a certain power
of 2. This is similar to the way each position in our decimal
number system represents a certain power of 10. This is
illustrated below.
Decimal 10 3
10 2
10 1
10°
1,000’s
100’s
10s
Is
Binary 2 3
2 2
2 1
2°
8s
4s
2s
Is
If we look at a decimal number like 9,999j 0 (the subscript
10 means that we are using a number in base 10), it not
only tells us about a quantity of items, such as apples, but
also tells us about possible combinations.
The number 9,999 is a four -digit number. Using the 10
different decimal digits from 0 through 9, and using no
more than four digits at a time, there would be 9,999 +
1, or 10,000, possible numbers you could create. (You add
the 1 because the number 0000 or simply 0 must also be
included.) This can also be calculated as 10 4 = 10,000.
If you were interested in giving unique addresses to
10,000 homes on the same street (quite a long street), it
would be possible to do so by using only four digits. The
first house would have the address 0, and then you would
just continue numbering up to 9,999.
EXAMPLE 15-1
Using only three digits, how many unique addresses could
you give to homes on a single street (a decimal number)?
SOLUTION
Since 10 3 — 1,000, this is the number of unique addresses
that are possible.
Data bus = bidirectional (two way)
Fig. 15-3 Data bus and address bus.
Chapter 15 System Overview
225
Now, let’s try the same problem in binary: 1111 2 is a
binary number. (The subscript 2 tells us we are using base
2 or binary numbers.) The size of this number is shown
below.
Binary 2 3 2 2 2 1 2°
8s 4s 2s Is
1 111
We have one 8. We have one 4. We have one 2. And we
have one 1. That is, we have an 8, a 4, a 2, and a 1. If
we add this up, we get
8 + 4 + 2 + 1 = 15
The number 111 1 2 is the same as 15 10 (decimal 15). This
means that using only 4 binary digits or bits, there are a
total of 15 + 1, or 16 unique numbers possible. This can
be calculated by using 2 4 - 16.
If you wanted to give unique binary addresses to 16
houses on the same street (not such a long street), it would
be possible to do so with only 4 bits. The first house would
be 0000 or simply 0, the next would be 0001, the next
0010, and so on up to 1111.
EXAMPLE 15 2
Using 12 binary digits, how many unique house addresses
would be possible?
SOLUTION
2 V ~ = 4,096 unique addresses
This is essentially what is necessary in the matter of
addressing memory locations. The highest number that
exists in binary using only 4 bits is 1111 2 (15 10 ). That
means that if we had only four address lines—that is, an
address bus with only four lines—we would be able to
have only a maximum of 16 10 different addresses. (0000
counts as one address.) Obviously, this is not enough. Look
at Fig. 15-4. This illustrates the number of unique addresses
possible with different numbers of address lines.
As can be seen in Fig. 15-4, if we decide to use only
eight address lines, since we are studying 8-bit chips, we
then limit ourselves to 256 memory locations. (Add the
values of the first eight positions starting from the far right
216 2 15 2 14 2 13 2 12 2 11 2 10 2 9
32,768 8,192 2,048 512
65,536 16,384 4,096 1,024
Fig. 15-4 Powers of 2. Also the number of memory
addresses available with varying numbers of address lines.
+ 1.) This is not nearly enough. Most 8-bit chips use 2
bytes for addressing purposes, which then allows 65,536
different memory locations. (One byte is 8 bits; 2 bytes is
16 bits, which then allows 2 16 combinations.) This is often
adequate. If not, there are ways to increase this number by
using a method known as bank switching.
EXAMPLE 15 3
How many memory locations could be addressed by a 10-
line address bus?
SOLUTION
2 10 = 1,024 memory locations can be addressed.
15-2 MICROPROCESSOR
ARCHITECTURE
We now need to look more closely at the actual micropro¬
cessor, which is the “brain” of our computer. First, we
will study those features which most microprocessors have
in common. Then we will look at each of the microprocessor
families and study their specific features.
Accumulator
One of the most often used parts of a microprocessor is the
accumulator. The accumulator is a storage place or register
which often has its contents altered in some way. For
example, we can add the contents of the accumulator to
the contents of a memory location. Usually the result of an
operation is also placed in the accumulator. This action is
illustrated in Fig. 15-5.
The microprocessor can take the contents of the accu¬
mulator and the data coming in, perform some operation
on the two, and place the result back in the accumulator.
There are times when no data is coming in but some
operation is being performed on the contents of the accu¬
mulator only. For example, the microprocessor might find
the l’s complement of the contents of the accumulator and
place the result in the accumulator in place of the original
number.
Some microprocessors have only one accumulator; others
have more than one.
2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 °
256 128 64 32 16 8 4 2 1
226 Digital Computer Electronics
Accumulator
Memory
Data in
In contents Out —.
Fig. 15-5 Accumulator operation.
Result
General-Purpose Registers
General-purpose registers are similar to the accumulator.
In fact, the accumulator is a special type of register.
General-purpose registers are temporary storage locations.
They differ from the accumulator in that operations involving
two pieces of data are usually not performed in them with
the result going back into the register itself, as in the case
of the accumulator. The microprocessor will often alter the
contents of a register, however. Figure 15-6 shows the
operation of a general-purpose register.
One might wonder why a microprocessor needs general-
purpose registers when it has RAM to temporarily store
information. The answer is speed. Data in registers can be
accessed and moved much more quickly than data in RAM.
Program Counter/Instruction Pointer
We mentioned earlier that instructions are stored in memory.
Considering the fact that there can be tens of thousands,
hundreds of thousands, or even millions of memory loca¬
tions, it’s obvious that the microprocessor must keep track
of the location from which it will be getting its next
instruction. This is the job of the program counter.
The program counter is a very special register whose
only job is to keep track of the location of the next
instruction which the microprocessor will use. Figure 15-7
illustrates its operation.
The program counter “points” to the address of the next
instruction to be retrieved and used by the microprocessor.
The act of “getting” an instruction is usually referred to
as fetching the instruction. The period of time needed for
this is often called th t fetch cycle.
Index Registers
Another type of register is the index register. In the same
way that the index of a book helps a person locate
information, the index register can be used to help locate
data. The index register is normally used as an aid in
|-Register- 1
Data in-In contents Out-Data out
Fig. 15-6 General-purpose register operation.
I— Program counter —j
Address of next
instruction
0002
0000
Contents
0001
Contents
0002
Instruction
0003
Contents
0004
Contents
0005
Contents
0006
Contents
0007
Contents
Fig. 15-7 Program counter operation.
accessing data in tables stored in memory. The index
register(s) can be incremented (increased by 1) or decre¬
mented (decreased by 1) but normally does not have other
arithmetic or logical capabilities.
We will look at the index register(s) more completely in
later chapters.
Status Register
The status register , sometimes called the condition code
register , or flag register , is a special register which keeps
track of certain facts about the outcome of arithmetic,
logical, and other operations. This register makes it possible
for the microprocessor to be able to test for certain conditions
and then to perform alternate functions based on those
conditions. This is done through the use of flags.
We will now take an overall look at flags. Don’t be
concerned if these next few paragraphs are not completely
clear at this point. They can serve as a refresher for those
who may have had some experience with microprocessors
in the past. And for those who are new to this subject,
reading about them now will at least give you some idea
of what flags are and how they are used. These concepts
will be covered again in greater detail as they arise in later
chapters.
The status register is divided into individual bits which
have their own unique functions. Each bit is called a flag.
Each flag keeps track of, or “flags,” us concerning certain
conditions. Not every operation or instruction affects every
flag. Some instructions affect many flags, and some don’t
affect any at all. Figure 15-8 shows a model of a typical
status register.
When referring to flags, the following logic is used. If
some condition has come to be, or is true, the flag uses a
1 to say, kk Yes, this is true or has happened.” If that
condition has not occurred, the flag uses a 0 to say, “No,
this is not true or has not happened.” Causing a flag to
become 1 is called setting a flag. Causing a flag to become
0 is called clearing a flag.
Chapter 15 System Overview 227
Memory
Status register
Flags
1
Z
N
C
H
V
b
b
b
b
b
b
1 - Overflow flag
- Half-carry flag
- Carry flag
--— Negative flag
—-- Zero flag
-- Interrupt flag
Fig. 15-8 Model of a typical status register, (b’s represent
bits.)
The zero flag keeps track of whether the last operation
which affects this flag produced an answer of zero. This
flag is set or 1 if a zero result has been produced and is
cleared or 0 if a nonzero result has been produced.
The negative flag tells us if the last operation which
affects this flag produced a negative number. When 8-bit
signed binary numbers are used, if bit 7 (the eighth bit) of
the number is 1, then the number is negative and the N
flag will be set; if bit 7 of the number is 0, then the number
is positive and the N flag will be cleared or 0. (This negative
flag is sometimes called a sign flag and is indicated with
an “S.”)
The carry flag tells us if the last operation which affects
this flag produced a carry from bit 7 (in 8-bit systems) of
the accumulator (bit 7 is the left-most or most significant
bit) into the carry bit. The carry flag also tells us if, during
subtraction, a borrow into bit 7 was needed. How a borrow
is indicated depends on which microprocessor is being
used. See Fig. 15-9.
The half-carry flag tells us if the last operation which
affects this flag was an arithmetic operation which produced
a carry from bit 3 to bit 4. This feature is primarily used
with BCD (binary-coded-demical) numbers.
The overflow flag tells us if the last operation which
affects this flag caused a result that is outside the range of
signed binary numbers for the word size being used at the
time. In the case of 8-bit microprocessors, this is +127 or
— 128. If this range is exceeded, the overflow flag is set
(1) to warn the programmer.
L
—
m
□
0
□
0
0
0
0
0
Carry
7
6
5
4
3
2
1
0
' ag Accumulator
Fig. 15-9 A “ carry” from bit 7 into the carry flag.
0000
A
0001
0002
Top-of-stack
d
d
r
0003
Data item #6
1
— Stack pointer —
0004
Data item #5
_
0002
e
g
s
0005
Data item #4
e
0006
Data item #3
s
0007
Data item #2
0008
Data item #1
Fig. 15-10 Typical stack and stack pointer.
The interrupt (interrupt mask, interrupt flag, interrupt
enable bit) prevents maskable interrupts from occurring
when it is set and allows them when cleared.
Stack and Stack Pointer
The stack is a special place in memory. The stack is most
often used to store certain critical pieces of data during
subroutines and interrupts. You’ll learn more about these
later, but let’s look at the structure of a stack at this time.
Refer to Fig. 15-10.
The structure of the stack is a first-in-last-out (FILO)
type of structure. Unlike main memory, where you can
access any data item in any order, the stack is designed so
that you can access only the top of the stack. If you want
to place data in the stack, it must go on top; if you wish
to remove data from the stack, it must be on top before it
can be removed.
Let’s see how the situation in Fig. 15-10 has come to
be. To do that, refer to Fig. 15-11. Data item #1 is the
first item we wish to place on the stack.
Memory
0000
A
0001
d
0002
d
r
0003
— Stack pointer —
0004
0008
e
c
a
s
0005
e
0006
s
0007
0008
Top-of-stack
1
Fig. 15-11 Typical stack and stack pointer.
228 Digital Computer Electronics
Memory
0000
A
0001
d
0002
d
r
0003
— Stack pointer-
0004
0007
e
s
0005
s
e
0006
s
0007
Top-of-stack
0008
Data item #1
Fig. 15-12 Typical stack and stack pointer.
At this time the stack pointer is “pointing” to memory
location 0008; therefore data item #1 will be placed in the
stack at that memory location. The act of putting a piece
of data in the stack is called pushing data onto the stack.
It is as though the data is being pushed in from the top.
Now look at Fig. 15-12.
We have pushed data item #1 onto the stack and the
stack pointer has been decremented or decreased by one,
which means that it is now pointing to memory location
0007. Location 0007 is the top-of-the-stack now. Now let's
push data item #2 onto the stack. The stack will appear as
it does in Fig. 15-13.
When data item #2 was pushed onto the stack, it went
into the location the stack pointer was pointing to—which
was 0007. The stack pointer was then decremented to 0006.
This process will be repeated until it appears as it did in
Fig. 15-10.
At some point we will need this data in the stack, so we
will remove it from the top-of-the-stack. This is called
popping or pulling the data from the stack. We simply
Memory
0000
A
0001
d
0002
d
r
0003
— Stack pointer —
0004
0006
e
s
0005
s
0006
Top-of-stack
e
s
0007
Data item #2
0008
Data item #1
Fig. 15-13 Typical stack and stack pointer.
reverse the whole process. As each data item is removed,
the stack pointer will drop, which in this case means that
it will point to the next-greater memory address.
EXAMPLE 15-4
Refer to Fig. 15-13. If we pull data item #2 from the stack,
will the stack pointer increment or decrement? What hex¬
adecimal value will appear in the stack pointer?
SOLUTION
The stack pointer will be incremented as data item #2 is
pulled from the stack. The hexadecimal value 0007 will
appear in the stack pointer. In fact, the stack will appear
as it did in Fig. 15-12.
Width of Registers
All registers have a maximum capacity. That is, they will
only hold a certain number of bits. The width is generally
8, 16, or 32 bits.
8-Bit Registers
An 8-bit register is one that is 8 bits wide. This means it
can hold 1 byte as shown in Fig. 15-14. Most computers
and trainers you will be using will not display an 8-bit
register in binary. Instead, they will have a hexademical
display. If you have forgotten how to convert binary to
hexadecimal and hexadecimal to binary, review that section
in Chap. 1.
|-Register- 1
Data in-In 0100 0011 Out-► Data out
Fig. 15-14 Eight-bit register model.
It is often useful to separate the 8 bits into two groups
of 4. The left group of 4 is called the upper nibble, and
the right group of 4 is called the lower nibble. This is
illustrated in Fig. 15-15.
0101 0011
Upper nibble Lower nibble
Fig. 15-15 Upper- and lower-nibble positions.
Chapter 15 System Overview 229
EXAMPLE 15-5
If a register contained the binary number shown in Fig. 15-
lb, what would appear in the hexadecimal display for that
register?
be represented by 1100 in binary. Putting the four nibbles
together produces 1011 1111 0011 1100, which constitutes
the binary contents of this register.
Specific Microprocessor
Families ___
The rest of this chapter is divided into sections, each of
which is devoted to one particular microprocessor family.
Go to the section which discusses the microprocessor family
you are using.
SOLUTION
The upper nibble, 1100, is the same as the hexadecimal
digit C. The lower nibble, 1011, is the same as the
hexadecimal digit B. Therefore, the hexadecimal display
will show CB.
16-Bit Registers
A 16-bit register of course is 16 bits wide. This is illustrated
in Fig. 15-17. As you can see, the 16 bits are again separated
into groups of 4. Each nibble, or group of 4, will be
represented in the display as 1 hexadecimal digit.
Fig. 15-17 Sixteen-bit register model.
EXAMPLE 15-6
In Fig. 15-18, what are the binary contents of the register
when the display is as shown?
Fig. 15-18 Example B.
SOLUTION
The far left digit (also called the most significant digit), the
B, has a binary equivalent of 1011. The F would be 1111.
The 3 would be 0011. And the hexadecimal digit C would
15-3 6502 FAMILY
Let’s look at specific characteristics of the 6502 family of
microprocessors.
Accumulator
The accumulator in the 6502 family of microprocessors is
8 bits wide. The 6502 has only one accumulator* unlike
others which have more than one. Figure 15-19 shows what
it looks like.
General-Purpose Registers
The 6502 has no general-purpose registers. The functions
they perform must be accomplished in the 6502 by using
the accumulator, index registers, and memory.
Fig. 15-19 6502 accumulator model.
Program Counter
The 6502 family program counter, as shown in Fig. 15-20,
is 16 bits wide and is divided into an upper half which we
have labeled PC H (program counter high) and a lower half
which we have labeled PC L (program counter low).
Fig. 15-20 Sixteen-bit 6502 program counter and display.
230 Digital Computer Electronics
Most of the time it operates as one 16-bit counter, but
there are times, particularly when subroutines are involved,
when the division into 2 bytes is necessary. The display
for the program counter will appear as four hexadecimal
digits as shown in the figure.
bit, it will be easier to remember. Please note that other
microprocessors handle this situation with the carry flag
and subtraction in just the opposite manner.
Stack and Stack Pointer
Index Registers
The 6502 has two index registers. They are each 8 bits
wide. One is the X index register, and the other is the Y
index register.
Status Register
The 6502 status register contains 8 bits, but only 7 are
actually used. The layout of this register is shown in Fig.
15-21.
The 6502 has several flags in addition to those mentioned
in the New Concepts section of this chapter.
The break flag keeps track of what are called “software
interrupts.” When the programmer puts a BRK (BReaK)
instruction in the program telling the microprocessor to
stop, the programmer “interrupts” the program in progress.
If this occurs, the break flag is set.
The decimal mode flag, when set, tells the microprocessor
to assume that any numbers which it is instructed to add
or subtract are BCD (binary-coded decimal) numbers instead
of regular binary numbers. This will result in a BCD answer.
During addition the carry flag in the 6502 is used as
described in the New Concepts section of this chapter.
When a carry goes out from bit 7 of the accumulator, it
goes into the carry bit. During subtraction, however, if a
borrow is needed from the carry bit by bit 7, then the carry
flag is cleared (0). If you think of it as though the 1 that
was needed during the borrow actually came from the carry
Carry flag
Zero flag
Interrupt flag
Decimal mode flag
Break flag
Unused
Overflow flag
Negative flag
Fig. 15-21 6502 family status register, (b’s represent bits.)
The 6502 has a stack with a maximum size of 256 bytes
or memory locations. The stack pointer is 8 bits wide with
a 9th bit that is always set. Figure 15-22 shows it in more
detail.
The greatest memory address (lowest position) which can
be designated as the top-of-the-stack is 1 1111 1111 2 , which
is 01FF 16 . Each time another number is pushed onto the
stack, the top-of-the-stack rises, which means that the stack
pointer is decremented by one (since smaller-numbered
memory addresses are toward the top). The smallest address
which can be designated as the top-of-the-stack is 1 0000
0000 2 , which is 0100, 6 . This is not always the top; it is
simply the highest position (smallest memory address) at
which the top can exist.
We will look at the stack and its uses in later chapters.
Complete Model
Let’s look at a complete model of the 6502 family of
microprocessors. Refer to Fig. 15-23.
In our model we do not show the binary numbers that
are actually in each register or location but, rather, the
hexadecimal numbers which appear in the display of
microprocessor trainers. The exception is the status register,
in which both binary and hexadecimal are shown. The small
h’s and b’s represent the data that would be in each register
or memory location. Each “h” stands for one hexadecimal
digit or nibble—which is to say, 4 bits. Each “b” stands
for 1 bit. When we use this model in later chapters, we
will place actual values in place of the h’s and b’s.
A
d
d
r
e
s
s
e
s
00FE
00FF
0100
0101
0102
01FC
01FD
01FE
01FF
Memory
Fig. 15-22 6502 family stack and stack pointer.
Chapter 15 System Overview 23 X
Memory
Accumulator
hh
X register
hh
Y register
hh
1
Stack pointer
hh
PCh—P rograrr
hh
i counter—PC L
hh
Status register
N V —B D 1 ZC
bb — bbbbb
h | h
Fig. 15-23 Complete 6502 programming model.
15*4 6800/6808 FAMILY
This section covers the Motorola 6800 and 6808 micropro¬
cessors. The 6809 is an enhanced version of the 6800/6808,
but most of this section can be applied to the 6809 as well.
The 6809 has all of the features of the 6800 plus additional
ones. The 6800 and 6808 are the primary subjects of this
section, but some differences in the 6809 are mentioned.
Accumulators
The 6800/6808 microprocessors have two 8-bit accumula¬
tors. Each has the same capabilities; that is, neither is a
general-purpose register. Both are true accumulators. (Gen¬
eral-purpose registers do not have all of the features of an
accumulator.) Figure 15-24 illustrates their functions.
The operation of these accumulators is the same as that
described in the New Concepts section of this chapter. One
note of interest concerning the 6809. It has the same 8-bit
accumulators; however, it has the additional ability to treat
Data in
|-Accumulator A- 1
In 8 bits Out - 1
the two as a single 16-bit accumulator known as accumulator
D and has special instructions for such operation.
General-Purpose Registers
The 6800/6808, like the 6502, has no general-purpose
registers. Their functions must be performed by using the
accumulators, index register, and memory.
Program Counter
The 6800, 6808, and 6809 each have 16-bit program
counters. The 6800 family program counter, as shown in
Fig. 15-25, is 16 bits wide but is divided into an upper half
which we have labeled PC H (for program counter high)
and a lower half we have labeled PC L (for program counter
low). Most of the time it operates as one 16-bit counter,
but there are times, particularly when subroutines are
involved, when the division into 2 bytes is necessary. The
display for the program counter will appear as four hex¬
adecimal digits as shown in the figure.
Index Register
The 6800 and 6808 microprocessors each have one 16-bit
index register called the X index register . The 6809 has
two 16-bit registers named the X index register and the Y
index register.
The 6800 family’s index registers operate as described
in the New Concepts section of this chapter and will be
discussed in more detail in later chapters.
Condition Code Register
The 6800/6808 condition code register (called a status
register in other microprocessors), which is shown in Fig.
15-26, is composed of 6 flags or bits in an 8-bit register.
The 2 most significant bits are not used and are always set
( 1 ).
In the 6809 the 2 bits that are unused on the 6800/6808
have functions and are called the E flag and the F flag .
They will not be discussed in this text.
Result
Accumulator B
■ Program counter
1111 0000
— PC H -
0100 0001
— PC L
301
Data in
—► in
8 bits
Out-
r-Display-i
1
1
F°
41
Result
r;., ic tc e; vi a w,
—PC H
r AC AO foi
— PC L —
mill, nran
Fig. 15-24 Models of the 6800/6808 family accumulators.
display.
232 Digital Computer Electronics
Status register
Flags
1
1
H
1
N
Z
V
C
1
1
b
b
b
b
b
b
- Carry flag
- Overflow flag
--- Zero flag
Negative flag
“ -- Interrupt flag
Half-carry flag
Unused
--— Unused
Fig. 15-26 6800/6808 status register, (b’s represent bits.)
The carry flag in the 6800 family is set (1) when either
a carry or borrow from bit 7 occurs. (The 6502 by contrast
sets the flag for a carry but clears it for a borrow.)
All flags used in the 6800/6808 operate as described in
the New Concepts section of this chapter.
Stack and Stack Pointer
The 6800/6808 has a 16-bit stack pointer which uses RAM
for the stack itself. It operates as described in the New
Concepts section of this chapter.
The 6809 has a second stack called the user stack which
operates in a fashion similar to the first stack, which is
called the hardware stack . The user stack is not used for
interrupts and subroutines but is left free for the programmer
to use.
Complete Model
Let s look at a complete model of the 6800 family of
microprocessors. Refer to Fig. 15-27.
In our model we do not show the binary numbers that
are actually in each register or location but, rather, the
hexadecimal numbers which appear in the display of
microprocessor trainers. The exception is the status register
in which both binary and hexadecimal are shown. The small
ITs and b’s represent the data that would be in each register
or memory location. Each “h” stands for one hexadecimal
digit or nibble—which is to say, 4 bits. Each “b” stands
for 1 bit. When we use this model in later chapters, we
will place actual values in place of the ITs and b’s.
15-5 8080/8085/Z80 FAMILY
This section deals with the 8080 and 8085 microprocessors
from Intel and the Z80 microprocessor manufactured by
the Zilog Corp.
The 8080 and 8085 are nearly identical, the 8085 being
a slightly improved version of the 8080. Except for two
instructions, the instruction sets for the two chips are
identical.
The Z80 is a considerably enhanced version of the 8080.
It understands all the instructions of the 8080 and many
more. It has all the registers of the 8080 plus a number of
additional registers. We will cover only those aspects of
the Z80 that are found in the 8080 and 8085 at this time.
Accumulator
The 8080/8085/Z80 chips have one 8-bit accumulator. It
operates as described in the New Concepts section of this
chapter. Its operation is shown in Fig. 15-28. The Z80 also
has a second alternate accumulator.
Accumulator A
hh
Accumulator B
hh
X H —X register—X L
hh | hh
SP H —Stack pointer—SP L
hh | hh
PCh—P rogram
hh
counter—PC L
hh
Status register
1 1 H 1 N Z V C
1 1 b b b b b b
h | h
Fig. 15-27 Complete 6800/6808 programming model.
General-Purpose Registers
The 8080/8085/Z80 chips have an abundance of general-
purpose registers. These registers are arranged in pairs.
Notice the arrangement of one of these pairs in Fig. 15-29.
In this figure, 8 bits of data can go into and out of either
register B or C. Or, 16 bits can go into and out of the pair,
at which point they act as one 16-bit register.
Data in
|-Accumulator
In 8 bits
Out- 1
- •+ -Result
Fig. 15-28 8080/8085/Z80 accumulator model.
Chapter 15 System Overview 233
-Register B-
-Register C- 1
_1 1_1 1_
_
_1 1_1 L_l
16 bits into
BC register
P a ' r 8 bits into
register B
8 bits out of
register B
8 bits out of
register C
8 bits into
register C
16 bits out of
BC register
pair
Fig. 15-29 Model of 8080/8085/Z80 general-purpose
registers.
There are three sets of these general-purpose register
pairs. They are the BC pair, the DE pair, and the HL pair.
The letters B, C, D, and E are assigned to stand for each
register. The letters H and L stand for high and low. The
HL register pair is usually used for a different purpose than
the other two pairs. We will discuss that purpose more in
a later chapter.
Each of these registers has a mate, or “alternate,”
register in the Z80.
Program Counter
The 8080/8085/Z80 chips each have a 16-bit program
counter which operates as described in the New Concepts
section of this chapter. This program counter, as is the case
with the 6502 family and the 6800 family, is divided into
two halves for some operations. The upper byte or 8 bits
are called the PC H (for program counter high), and the
lower byte is called the PC L (for program counter low).
See Fig. 15-30.
Most of the time the program counter operates as one
16-bit counter, but there are times, particularly when
subroutines are involved, when division into 2 bytes is
necessary. The display for the program counter will appear
as four hexadecimal digits as shown in the figure.
Index Register(s)
The 8080 and 8085 have no index registers. The Z80 has
two—an X index register and a Y index register. The index
registers in the Z80 are each 16 bits wide.
Status Register
The status register in the 8080 and 8085 contains five flags
in an 8-bit register. See Fig. 15-31.
The parity flag involves a topic which has not been
discussed yet. Parity refers to the number of Is in a binary
number. Even parity exists when there is an even number
of Is. For example, the binary number 0110 000 has even
parity because it has two Is, and 2 is an even number. Odd
parity exists when there is an odd number of Is. For
example, the binary number 0111 0000 has odd parity
because there are three Is, and 3 is an odd number. It is
sometimes useful to keep track of parity for error-checking
routines and in data communications. If the parity is even,
the parity flag becomes set (1); if parity is odd, it clears
( 0 ).
The Z80 has the same five flags as the 8080 and 8085,
and in the same positions, plus one additional flag. See
Fig. 15-32.
The half-carry flag in the Z80 has exactly the same
function as the auxiliary carry in the 8085/8080.
The parity flag in the Z80 has a dual role—that of parity
checking and that of warning the programmer of 2’s-
complement overflow. Also, the Z80 has a negative or sign
flag (the 8080 and 8085 do not have one) which operates
as described in the New Concepts section of this chapter.
Stack and Stack Pointer
The 8080, 8085, and Z80 each have a stack with a 16-bit
stack pointer which operates as described in the New
Concepts section of this chapter.
Complete Model
Let’s look at a complete model of the 8080/8085/Z80 family
of microprocessors. Refer to Fig. 15-33 at this time.
Status register
Flags
S
Z
—
A
—
P
—
C
b
b
—
b
—
b
—
b
Carry flag (CY)
Unused
-Program counter- 1
1111 0000
0100 0001
-PC H -1
-PC L —1
-Display- 1
F ° I 41
— PC H —^—PC t —I
Fig. 15-30 Sixteen-bit 8080/8085/Z80 program counter and
display.
1 - Parity flag
—--- Unused
- Auxiliary carry (AC)
- Unused
- Zero flag
- Sign flag
Fig. 15-31 8080/8085 status register, (b’s represent bits.)
234 Digital Computer Electronics
Status register
Flags
S
Z
—
H
—
P
N
C
b
b
—
b
—
b
b
b
’- Carry flag (CY)
- Negative flag
- Parity/overflow (PV)
- Unused
- Half-carry flag
- Unused
- Zero flag
- Sign flag
Fig. 15-32 Z80 status register, (b’s represent bits.)
A couple of points concerning differences between the
8080/8085 and the Z80 should be noted. Figure 15-33 is a
model of the 8080/8085. The Z80 has an additional set of
alternate registers and two index registers which are not
shown in the model. The status register in the Z80 has an
additional flag called the negative flag . And the auxiliary
carry flag in the 8080/8085 is usually called the half-carry
flag in the Z80.
In our model we will not show the binary numbers that
are actually in each register or location but rather the
hexadecimal numbers which appear in the display of
microprocessor trainers. The exception is the status register
in which both binary and hexadecimal are shown. The small
Accumulator
hh
Register B
hh
Register C
hh
Register D
hh
Register E
hh
Register H
hh
Register L
hh
SPh—S tack pointer—SPj.
hh | hh
PC H —Progranr
hh
counter—PC|_
hh
Status register
SZ —A —P —C
bb — b — b — b
h | h
Fig. 15-33 Complete 8080/8085 and Z80 (8080 subset)
programming model.
h’s and b’s represent the data that would be in each register
or memory location. Each “h” stands for one hexademical
digit or nibble, which is to say 4 bits. Each “b” stands for
1 bit. When we use this model in later chapters, we will
place actual values in place of the h’s and b’s.
There is one point of significant difference between the
8080/8085/Z80 family and the 6502 or 6800 family. In the
case of the 6502 and 6800 microprocessors, the registers
and accumulators are completely independent of one an¬
other. In the 8080/8085/Z80 family, the six registers, namely
B and C, D and E, and H and L, can operate as six
independent 8-bit registers or as three 16-bit register pairs.
This allows single operations to be performed on 16-bit
data words.
15-6 8086/8088 FAMILY
In this section we will examine the 8086 and 8088 micro¬
processors from Intel. The 8088 is the microprocessor used
in the popular IBM PCs, XTs, and compatibles. The 80286
used in ATs and the 80386 can also be used with this text.
Since the 8086/8088 chips are the successors of the 8085,
they are similar to it but have many additional registers and
capabilities.
Accumulator(s)
The 8086/8088 has an accumulator (shown in Fig. 15-34)
which is 16 bits wide and is called AX. The upper 8 bits
is called AH {accumulator high), and the lower 8 bits is
called AL (accumulator low).
General-Purpose Registers
The 8086/8088 has three 16-bit or six 8-bit general-purpose
registers (besides the accumulator). These are shown in
Fig. 15-34 and are called the BX, CX, and DX registers.
Each can be divided into an upper and lower byte called
BH, BL, CH, CL, DH, and DL, respectively. Also note
in the figure that A stands for accumulator, B for base, C
- Accumulator AX -
AH
hh
BH
hh
CH
hh
DH
hh
-Base BX-
-Count CX-
-Data DX -
AL
hh
BL
hh
CL
hh
DL
hh
Fig. 15-34 8086/8088 accumulator and general-purpose
registers.
Chapter 15 System Overview 235
for count, and D for data. This can help you remember the
main functions of each register.
Instruction Pointer
Instead of a program counter, the 8086/8088 has an
instruction pointer which does what the program counter
does in the 8-bit microprocessors. The instruction pointer
is 16 bits wide.
Index Registers
The 8086/8088 has several index registers and pointers
including the base pointer, source index, and destination
index. All are 16 bits wide. These are not used alone, as
with the 8-bit chips, but are used in combination with
registers called segment registers . Figure 15-35 is a model
of the 8086/8088 pointers and index registers.
Stack and Stack Pointer
The 8086/8088 stack is a standard memory stack (as are
all the 8-bit microprocessors we’ve covered). The 8086/
8088, however, can have a very large stack, up to 64K
(65,536 bytes). The location of the top-of-the-stack is
calculated by using both the stack pointer and the stack
segment.
Status Register
The status register containing the 8086/8088 flags is 16 bits
wide, although not all 16 bits are used. This register, shown
in Fig. 15-36, has a lower byte (8 bits) which is exactly
the same as the 8-bit 8085 microprocessor’s status register.
It has the same flags in the same positions. The upper byte
has four flags which the 8085 does not have.
The first flag is the trap flag, which controls a single-
step mode of operation.
Fig. 15-35 8086/8088 index registers and pointers.
- FIs
New
gs-
8085-like
-O D 1 T
-b b b b
h | h
S Z — A — P — C
b b — b — b — b
h i h
i
Fig. 15-36 8086/8088 flag register, (b’s represent bits; h’s
represent hex digits.)
The interrupt enable flag controls the interrupt request
pin on the microprocessor chip.
The direction flag controls whether the source index and
destination index increment or decrement during string
operations.
Finally, the overflow flag alerts the programmer to the
existence of an arithmetic overflow when set. This is a
condition in which the legal range for signed binary numbers
of a particular word size has been exceeded.
Segment Registers
The 8086/8088 microprocessor has several other registers
which do not exist on the 8-bit chips. These are the segment
registers. We’ll explain very briefly how they are used at
this time.
All the pointers and index registers in the 8086/8088
chips are 16 bits wide; 2 16 is 65,536 (64K) bytes. The
address bus, however, is 20 bits wide. We can have memory
locations extending up to 2 20 or 1,048,576 (1 mega-) bytes.
None of the pointers, including the instruction pointer,
would be able to point to this wide of a range of addresses.
To solve this problem, segment registers are used. Their
contents are combined with the contents of the various
pointers and index registers to form an address which is 20
bits wide. Exactly how this is done will be explained in a
later chapter.
Complete Model
Figure 15-37 is a complete model of the 8086/8088 micro¬
processors.
In the model shown in Fig. 15-37 the placeholders for
each binary digit are not shown. Rather, the hexadecimal
digits that would be seen on a computer or trainer are
indicated. The exception is the status register, in which
both binary and hexadecimal placeholders are shown. The
small h’s and b’s represent the data that would be in each
register or memory location. Each “h” stands for one
hexadecimal digit or nibble, which is 4 bits. Each “b”
stands for 1 bit. When we use this model in later chapters,
we will place actual values in place of the h’s and b’s.
236 Digital Computer Electronics
A
d
d
r
e
s
s
e
s
Memory
0100
hh
0101
hh
0102
hh
0103
hh
0104
hh
0105
hh
0106
hh
0107
hh
0108
hh
0109
hh
010A
hh
010B
hh
010C
hh
010D
hh
010E
hh
010F
hh
0110
hh
0111
hh
0112
hh
0113
hh
0114
hh
0105
hh
0106
hh
0107
hh
■Accumulator AX-
AH ! AL
hh | hh
-Base BX-
BH ! BL
hh | hh
-Count CX-
CH i CL
hh | hh
-Data DX-
DH
hh
DL
hh
Source index
hhhh
Destination index
hhhh
Stack pointer
hhhh
Base pointer
hhhh
Code segment
hhhh
Data segment
hhhh
Extra segment
hhhh
Stack segment
hhhh
Instruction pointer
hhhh
New
Flags -
-0 D I T
-b b b b
8085-like
S Z — A — P — C
b b — b — b — b
Fig. 15-37 Complete 8086/8088 microprocessor programming model.
GLOSSARY
accumulator A register in a microprocessor which can
not only store a byte or word of data but can have its
contents operated on, with the result of that operation going
back into the accumulator, replacing the previous value.
address B inary numbers which are assigned to consecutive
memory locations. Specific memory locations are accessed
through their addresses.
address bus A set of conductors upon which binary
addresses travel to memory chips.
data bus A set of conductors which carry binary data to
and from the microprocessor, memory, and I/O devices.
fetching The act of going to memory to get an instruction
which is to be decoded and executed.
flag One of the bits in the status register. (See status
register.)
general-purpose registers Locations which can store a
byte or word of data similar to RAM but which are inside
the microprocessor itself. Certain operations can usually be
performed on the contents of registers.
index register A register which can be incremented and
decremented and whose primary function is to point to data
(often used in tables).
Chapter 15 System Overview 237
program counter A special-purpose register whose pur¬
pose is to keep track of the next instruction to be fetched
from memory.
RAM An acronym for random-access memory. This type
of memory loses its data when power is removed.
ROM An acronym for read-only memory. This type of
memory does not lose its data when power is removed.
stack An area (usually in RAM) which holds vital infor¬
mation during subroutines and interrupts. It can also be
used by the programmer as a LIFO (last-in-first-out) data
storage area.
status register (condition code register) A special register
whose individual bits show the status of certain conditions
or the results of certain operations.
SELF TESTING REVIEW
Read each of the following and provide the missing words.
Answers appear at the beginning of the next question.
1. _is the type of memory which can have
its contents changed thousands of times per second.
2. {RAM) The_of a memory location
is similar to the address of your home and the
_inside the memory location is similar to
the beds, chairs, dishes, and so on, in your home.
3. ( address , data) The_of a memory loca¬
tion is necessary to specify which of many locations
is to be written to or read from.
4. ( address ) The address bus is usually-
(unidirectional, bidirectional).
5. (unidirectional) The data bus is usually-
6. (bidirectional) Each different bit position in binary
numbers represents a certain power of-
7. (2) Probably the most used register in a micropro¬
cessor is the_
8. (accumulator) A register which helps microproces¬
sors to work with tables of data is the-
9. (index register) When a flag has a-in it,
this indicates that the condition which the flag tests
has not come true.
10. (0) When a flag has a_in it, this indi¬
cates that the condition which the flag tests has
come true. (7)
PROBLEMS
General
15-1. By what means is one memory location differen¬
tiated from another?
15-2. Using decimal numbers, how many combinations
can be represented by using only five digits?
15-3. Using binary numbers, how many combinations
can be represented by using only 20 bits?
15-4. If we had 20,000 lo memory locations, what
would be the least number of address lines
needed to describe each location? (Hint: Change
20,000 to binary or hex and determine the num¬
ber of bits needed.)
15-5. What register can have its contents altered in the
greatest variety of ways and is the real “work¬
horse” in the microprocessor?
15-6. In simplest terms, what are general-purpose reg¬
isters?
15-7. What advantage do registers have over RAM?
15-8. What has the sole purpose of keeping track of
the next instruction to be fetched?
15-9. In what register are the flags located?
15-10. What has happened if the zero flag has a 1 in it?
15-11. Which flag will be set if a carry from bit 7 of
the accumulator is produced during an arithmetic
operation?
15-12. Which flag is primarily used with binary-coded
decimal numbers?
15-13. When normal stack instructions are used, can a
number be pulled from somewhere in the middle
of the stack?
15-14. What is taking a number from the top of the
stack called?
15-15. If an 8-bit register contained the binary number
1101 1110, what hexadecimal number would ap¬
pear as the display or readout for that register?
15-16. What are the binary contents of a register whose
hexadecimal display reads 2A?
15-17. What would the hexadecimal display of a 16-bit
register with 1100 0101 1000 0001 2 as its con¬
tents read?
6502 Family
15-18. How many general-purpose registers does the
6502 have?
15-19. How wide are the index registers in the 6502?
15-20. What flag, when set, tells the 6502 to assume
that binary-coded decimal (BCD) numbers are
being used?
15-21. What is the maximum size of the 6502 stack?
238 Digital Computer Electronics
6800 Family
15 - 22 . How many accumulators does the 6800 have?
15 - 23 . How wide is the 6800 program counter?
15 - 24 . How many memory locations can the 6800 pro¬
gram counter reference or point to?
15 - 25 . What are the 2 most significant bits in the 6800
condition code register used for?
8080/8085/Z80 Family
15 - 26 . How many 8-bit general-purpose registers does
the 8085 have?
15 - 27 . How many index registers does the 8085 have?
15 - 28 . How wide is the 8085 stack pointer?
8086/8088 Family
15 - 29 . Describe how the 8088 accumulator is labeled
and arranged.
15 - 30 . How many 8-bit general-purpose registers does
the 8088 have?
15 - 31 . In the 8088 what has the same function as the
program counter in the 8-bit microprocessors?
15 - 32 . What 8-bit microprocessor is the lower byte of
the 8088 flag register patterned after?
15 - 33 . How large can the 8088 stack be?
Chapter 15 System Overview 239
Data Transfer Instructions
New Concepts _
So far we’ve been able to get an overview of computers,
computer architecture, microprocessor architecture, pro¬
gramming, languages, flowcharting, and hardware. Now
let’s take a closer look at some of these areas.
Instruction Sets
The commands that microprocessors understand are called
instructions , and the complete “vocabulary” of each chip
is called its instruction set .
We will be studying the 6502, 6800/6808, 8080/8085/
Z80, and 8086/8088 microprocessor families and each
family’s instruction set. We will deviate from this plan in
two respects.
Rather than study the entire Z80 instruction set, we will
study only those instructions which are common to the
8080 and 8085. (The Z80 has many instructions which
neither the 8080 nor the 8085 understands. However, the
Z80 understands all the instructions of the other two chips
with only two exceptions.)
Also, we will not study the entire 8086/8088 instruction
set but will omit the loop and string instructions since they
have no counterpart in the 8-bit microprocessors.
Organization of This Text
You may find it helpful to know how this programming
portion of the text was developed.
We are ready to begin learning about microprocessor
instructions. The instructions being discussed in each chap¬
ter, the sequence in which the instructions are being
presented, the sequence of the chapters, and the instruction
categories have all been carefully planned.
As mentioned before, this text centers around the most
popular general-purpose 8-bit microprocessors (the 6502
family, the 6800/6808 family, and the 8080/8085/Z80
family) and the 16-bit 8086/8088 family. During the prep¬
aration of this text, the instruction sets of each of these
microprocessors were carefully analyzed, and it was found
that each chip’s instructions fell into natural groups. After
each instruction was placed into its natural category, it was
possible to identify those categories which were common
to every microprocessor family. Those instructions which
did not fall naturally into one of these common groups were
placed in the group in which they most nearly fit. In short,
a consistent and uniform method of classifying instructions
was applied to each microprocessor family. In the tables
section of this book (Part 4) you will find the complete
instruction set of each chip broken down into these groups
or categories.
Next, the chapters were planned to reflect these same
groups. Thus, rather than trying to make the microprocessors
fit the scheme of this text, the text was designed around
the natural characteristics of the microprocessors. Each
chip’s instruction set has been broken down into the same
categories as the others, and the appendixes and chapters
treat each chip family equally.
Organization within Each Chapter
Most chapters start with a New Concepts section (which is
where we are now). The discussion here is general—that
is, it can be applied equally well to all microprocessor
families and does not focus on any one family. Then, after
this general discussion, the remainder of the chapter is
divided into family-specific sections.
For example, if you are using the 6808 microprocessor,
you would read the New Concepts section and then go
immediately to the 6800/6808 Family section. There, spe¬
cific information will be given to help you apply the
principles discussed in the New Concepts section to the
6800/6808 microprocessors.
Now let’s look at our first instruction category.
240
16-1 CPU CONTROL INSTRUCTIONS
The easiest instruction to learn about is an instruction which
does nothing, and surprisingly, there is such an instruction.
Let’s look at it.
The No Operation Instruction
The no operation instruction does exactly that: It does
nothing. This is a waste of time, and wasting time is what
this instruction does best.
A microprocessor is quite fast, in some situations too
fast. We can give it a certain number of these no operation
instructions to stall it until a certain amount of time passes.
The no operation instruction has another use—that of
filling space in the program. When writing programs, we
must sometimes insert additional instructions into the middle
of a program to alter the way it works or to fix a problem.
If you use one of the simpler monitors (instead of an
assembler, or a monitor with an insert feature), it may not
have a feature which will let you insert instructions into
the middle of a program you have entered. When this
happens, you must rewrite every part of the program
beginning from the point at which the inserted instruction
must be placed, to the end. By adding some no operation
instructions at various locations in the program when you
first write it, some spaces will have been created where
new instructions can go. The new instructions can simply
take the place of the no operation instructions.
The Halt Instruction
Called wait , halt , or break (depending on the microproces¬
sor), this instruction has the obvious purpose of stopping
the microprocessor. There is no go instruction—we’ll see
how that is done shortly—but there must be a way to stop
the program. In some microprocessor families this is not
the only function of this instruction, but this is all we need
to be concerned with at this time.
16-2 DATA TRANSFER
INSTRUCTIONS
This category of instructions has the job of transferring or
moving data from one place to another. Before studying
these instructions, we need to consider a basic concept.
Physical Places
Sometimes people think that when we speak of moving
data from one place to another within a microprocessor,
we are referring only to the “net effect’’ of the transfer,
and that nothing actually moved.
If this were so, the operation of a microprocessor would
resemble what happens when you go to the bank and transfer
money from your savings account into your checking
account. Though the net effect of the transfer is to decrease
the amount of money in the savings account and to increase
the amount in the checking account, you know that no one
in the bank actually picked up the money in the savings
account and placed it in another spot where your checking
account was. It all happened “on paper.’’
This is not the case with microprocessors. The accu¬
mulators, general-purpose registers, program counter, index
registers, and so on, are all real places. While it is true that
tiny numbers don’t move around inside the chip, the voltages
representing these numbers can be made to appear in various
places, so for all practical purposes the numbers themselves
move.
If you experience difficulty visualizing what a program
does, it may help to write down the contents of each register
and/or memory location. Then as each location is changed
by the program, change it on your paper. We will use this
technique in many of the figures.
Where Data Is Transferred
Data is moved between registers or between registers and
memory. The number of possible combinations depends on
the microprocessor and how many registers it has. Figure
16-1 shows some typical possibilities.
How Data Is Transferred
Different microprocessor instruction sets use different terms
to represent the act of transferring data. “Move,” “load,”
“store,’’ and “transfer” are all common terms.
Though we will use the term “moving,” and even though
thinking of it in that way will work as you become proficient,
in the beginning a distinction has to be made. When a
Fig. 16-1 Some of the possible data transfer combinations.
Chapter 16 Data Transfer Instructions 24 1
Fig. 16-2 An example of a transfer instruction.
move , load , transfer , or store instruction is executed , o
duplicate of the data is actually being placed in the target
register or destination .
If you were to move your car from one parking spot to
another in a parking lot, your car would no longer be in its
original place. This is true moving. This is not what happens
in a microprocessor. If, however, you photocopy an im¬
portant document, place the copy in a filing cabinet, and
keep the original, you have not actually moved the document
to the filing cabinet, but rather you have moved a copy of
the document. This is what happens in a microprocessor.
An Example of a Transfer Instruction
Look at Fig. 16-2.
Suppose we wanted to transfer the FF in the accumulator
to the register, which now contains 23. We would write a
program which instructs the microprocessor to transfer the
contents of the accumulator to the register. The result of
this action is shown in Fig. 16-3.
Fig. 16-3 An example of a transfer instruction.
Notice that the original FF in the accumulator is still
there. We simply made a copy of it and placed the copy in
the register. The original contents of the register are lost.
Now go to the section of this chapter which discusses
your particular microprocessor family.
Specific Microprocessor
Families
16-3 6502 FAMILY
Let’s see how the ideas which were introduced in the New
Concepts section apply to the 6502 microprocessor family.
CPU Control Instructions
The 6502 family has a no operation instruction which uses
the mnemonic NOP. Refer to the Expanded Table of 6502
Instructions Listed by Category in Part 4 of this text.
Look at the NOP instruction, which is the very first
instruction in this table. In the third column, the Boolean/
Arithmetic Operation column, we see that this instruction
does “nothing,” just as we said it would. Also notice the
hexadecimal number under the Op (op code) column, in
this case EA. This is the actual hexadecimal code for NOP.
Don’t worry about the rest of the NOP information at this
time.
The 6502 family doesn’t have an actual halt instruction,
but the instruction which serves its purpose is the BReaK
instruction. Refer to the table again. Notice that the BReaK
instruction uses the mnemonic BRK and has an op code of
00 .
Data Transfer Instructions
Look under the BReaK instruction and you will see the
beginning of the Data Transfer Instructions section of the
table. In this section you will see a list of all of the different
types of data transfer instructions available in the 6502
family. (To those with previous microprocessor experience:
You may notice that we have excluded transfer instructions
involving the stack. This is intentional. They have been
included in the Stack Instructions category.)
Direction of Data Transfer
Let’s look at the data transfer instructions more closely.
The first instruction listed is the LoaD Accumulator instruc¬
tion. The boldfaced letters show where the LDA mnemonic
came from. The third column shows the Boolean/Arithmetic
Operation. This is a concise and graphic way to state exactly
what this instruction does. It shows M, which stands for
memory, moving toward A, which stands for the accu-
242 Digital Computer Electronics
mulator. To put it another way, the contents of a certain
memory location are being transferred into the accumulator.
Recall from the New Concepts section that moving or
transferring is actually more like making a copy of what’s
in a particular location and placing the copy in the desti¬
nation.
Referring to the Expanded Table of 6502 Instructions,
notice that the second and third instructions, LDX and
LDY, are similar to the LDA. The difference is that they
copy the contents of a particular memory location and place
it in either the X register or the Y register instead of the
accumulator.
It may help to have a mental picture of our programming
model of the 6502, shown in Fig. 16-4, as we discuss these
instructions.
We have talked about moving or copying the contents
of some particular memory location to the accumulator, the
X register, or the Y register. Now let’s consider doing the
reverse.
Look at the fourth, fifth, and sixth instructions in the
table. They are STA, STX, and STY, that is, Store the
contents of the accumulator in a memory location , store
the contents of the X register in a memory location , and
store the contents of the Y register in a memory location ,
respectively. The store instructions are just the reverse of
the load instructions. (See the Boolean/Arithmetic Operation
column.)
Now, continue referring to both the table and Fig. 16-4.
The next two instructions (TAX and TXA) allow you to
transfer the contents of the accumulator and X register
between each other. The last two instructions (TAY and
TYA) allow you to transfer the contents of the accumulator
and the Y register between each other.
mnemonic LDA? No, but if you are using an assembler,
the assembler translates the mnemonics into binary numbers
which it does understand. (If you use a hexadecimal keypad
or type in hex numbers, you do not have an assembler.)
The point here is that the microprocessor inside your
computer does not understand English words like “load”
or mnemonics like LDA.
If you are using an assembler, the assembler program is
translating the mnemonics, which the microprocessor does
not understand, into something it does understand. What
does the microprocessor understand? Binary numbers. In
our case we will enter them as their equivalent hexadecimal
value and let the monitor or assembler translate that into
binary. For our purposes, at least at this point, well say
that the microprocessor understands hexadecimal. (The
monitor is part of the firmware built into your microprocessor
trainer.)
Refer to the Expanded Table of 6502 Instructions. If we
wanted to tell the microprocessor to load the accumulator
from memory (the first data transfer instruction, LDA) the
microprocessor chip would actually need the hex code in
the seventh column over, the Op code column (Op for
short). We would place the hex number A9, AD, A5, Al,
Bl, B5, BD, or B9, depending on which variation of the
instruction we wanted to use, in the computer’s memory
as the first instruction to execute.
Let’s try another example. What if you wanted to have
the microprocessor store the contents of the Y register in
memory? What would be the hex number the microprocessor
would need to understand what you wanted to do? (You
should have said either 8C or 84 or 94 from the STY
instruction.)
Op Codes
Does your computer or microprocessor trainer understand
the words “load accumulator”? No. Does it understand the
Accumulator
hh
X Register
hh
Y Register
hh
! Stack pointer
! hh
PC H —Program
hh
counter—PC L
hh
Status register
N V —BDIZC
bb—bbbbb
h | h
Fig. 16-4 Complete 6502 programming model.
Sample 6502 Program
Program Objective
Let’s create a program which will
1. Place the number 11 in the accumulator.
2. Stop.
Creating the Program
Refer to the Data Transfer Instructions section of the
Expanded Table. Do you see an instruction which could be
used to place a number in the accumulator? Look in the
Boolean/Arithmetic Operation column. You need an instruc¬
tion which has an arrow pointing to the accumulator. There
are three such instructions—LDA, TXA, and TYA. Since
we don’t want to involve the X register or Y register, LDA
will be our choice.
The next step is to determine which of the LDA instruc¬
tions to use. There are eight. The key to this decision is in
the Address Mode column. The LDA instruction which has
Immediate in the address column is the one we want.
Chapter 16 Data Transfer Instructions 243
Addr
Obj
Assembler
Comment
0000
A9
LDA #$11
Load the accumulator with the number (11)
immediately following the LDA# op code (A9)
0001
11
0002
00
BRK
Halt
Fig. 16-5 Sample program. (Note: The addresses should be
an area where user programs can be placed. If 0000 is not
such a place on your system, then you will need to change
these addresses.)
Immediate addressing tells the microprocessor that the data
it needs will be coming immediately after the op code. We
will learn more about addressing modes in the next chapter.
Finally, you want the program to stop. The instruction
which does this is in the CPU Control Instructions section
of the Expanded Table. The BRK instruction is the obvious
choice.
Entering the Program
The completed program is shown in Fig. 16-5. WeTl see
how to enter it into your microprocessor first by using an
assembler and then without an assembler.
Note that the column labeled Obj contains the actual
6502 op codes while the Assembler column contains the
mnemonic and data in a format similar to that which is
used by an assembler.
Refer to the LDA instruction in the Expanded Table. To
the right of the word Immediate, you see LDA #$dd. This
is in the Assembler Notation column and describes how
many assemblers require that you type this instruction. With
eight different LoaD Accumulator instructions, the assem¬
bler must know which one you want. The format of the
information after the LDA is how the various forms of the
command are differentiated. The # means that the data to
be used is coming immediately after the command itself.
The $ indicates that it is a hexadecimal number. The dd
simply stands for two hexadecimal digits of data. (Each d
stands for one nibble or 4 bits.)
It is important to remember that we are talking about a
typical assembler format; however, there is no absolute
standard that must be followed. Refer to the manual which
came with your assembler, or ask your instructor for
information about your assembler’s format.
We are going to enter this program into memory starting
at location 0000 (hexadecimal). If the trainer you are using
does not allow programs to be placed in these memory
locations, refer to your manual and substitute addresses
which are valid for your trainer or computer for those shown
in Fig. 16-5.
If you are using an assembler, please enter the program
at this time. It will look similar to what is shown in Fig.
16-6.
Address Opcode Data Mnemonic Immediate Hex Data
0002 00 BRK
Fig. 16-6 Disassembly of the sample program. (The
mnemonic and the data to the right of the mnemonic are
all that’s typed in during assembly.)
Now place 0s in the accumulator, the X register, and the
Y register so that you will know what numbers are in each
register before the program is run. Refer to Fig. 16-7 to
see what memory and the registers should look like.
If you are not using an assembler, you must look up the
op codes by hand in the Expanded Table. This is called
hand-assembly. Let’s go through the necessary steps for
hand-assembly.
To the right of the LDA #$dd, in the op code (op for
short) column you will see the hexadecimal number A9.
This is the 6502 op code, which stands for Load the
accumulator with the number immediately following this op
code. Set your trainer so that the memory address at which
the next instruction will be loaded is someplace within the
area allowed for user programs. We chose 0000, but you
Accumulator
00
X Register
00
Y Register
00
1
Stack pointer
hh
PC H —Program
hh
i counter—PC L
hh
Status register
N V— B D 1 Z C
bb — bbbbb
h | h
Fig. 16-7 6502 sample program.
244 Digital Computer Electronics
Memory
0000
A9
0001
11 -
0002
00
0003
hh
0004
hh
0005
hh
0006
hh
0007
hh
0008
hh
0009
hh
New number
- (11) replacing —
old number
(00)
Accumulator
—^ 11 00 —►
X Register
00
Y Register
00
1
_
Stack pointer
hh
PC H —Program
hh
counter—PC(_
hh
Status register
N V —B DIZC
bb — bbbbb
h | h
Fig. 16-8 6502 sample program.
Checking the Results of Program (Analysis)
After running the program, you should have 00 in the X
register, 00 in the Y register, and 11 in the accumulator.
The program does what we designed it to do.
Here’s one for you to try.
EXAMPLE 16-1
Manually place 00s in the accumulator, the X register, and
the Y register. Next, write a program which will
1. Place the hex number EE in the accumulator.
2. Transfer (copy) the contents of the accumulator (A)
into the X register (X).
3. Transfer (copy) the contents of the accumulator (A)
into the Y register (Y).
4. Stop.
may need to use another location. Enter the number A9
into the first available memory location. Since this was a
load accumulator immediate instruction, the microprocessor
will expect the next address, which immediately follows
the op code, to contain the number which is to be placed
in the accumulator. Therefore enter 11 next. In the third
address enter 00, which is the op code for the BRK
instruction.
Enter 0s into the accumulator, X register, and Y register
at this time so that you will know the condition of these
registers before the program is run.
If you check your registers and memory, you should see
what is shown in Fig. 16-7 (although you may have placed
the program at a different memory location). The h’s and
b’s represent hex and binary digits which we are not
concerned with at this time.
Running the Program
Let s use Fig. 16-8 during our analysis of program operation.
The first op code is A9, which means Load the accumulator
with the contents of the next memory location , or more
properly, Place a copy of the contents of the next memory
location in the accumulator . As you see, the number 11 is
replacing 00 in the accumulator. The program then continues
to the next instruction op code, 00, which stands for
BREAK, and stops.
SOLUTION
Figure 16-9 shows the completed program. Figure 16-10
shows memory and the registers and what happens during
program execution.
16-4 6800/6808 FAMILY
Let’s see how the ideas which were introduced in the New
Concepts section apply to the 6800/6808 microprocessor
family.
CPU Control Instructions
The 6800/6808 family has a no operation instruction which
uses the mnemonic NOP. Refer to the Expanded Table of
6800 Instructions Listed by Category in Part 4 of this text.
In the third column, called the Boolean/Arithmetic Op¬
eration column, we see that this instruction does “nothing,”
just as we said it would. Also notice the hexadecimal
number under the op (op code) column, in this case 01.
This is the actual hex code for NOP.
The 6800 family doesn’t have an actual halt instruction,
but the instruction which serves its purpose is the WAIt
for Interrupt instruction. (Bold type and capital letters
Addr
Obj
Assembler
Comment
0000
A9
LDA #$EE
Copy the hex number EE into the
accumulator (A)
0001
EE
0002
AA
TAX
Transfer the contents of A into X
0003
A8
TAY
Transfer the contents of A into Y
0004
00
BRK
Stop
Fig. 16-9 Example 16-1 program listing.
Chapter 16 Data Transfer Instructions 245
Memory
0000
A9 !
0001
EE-
0002
AA
0003
A8
0004
00
0005
hh
0006
hh
0007
hh
0008
hh
0009
hh
1. Transfer "EE" to A
— 2. Transfer A to X -
— 3. Transfer A to V —
Accumulator
EE
X Register
EE
Y Register
EE
Stack pointer
hh
PC H —Program counter—PC L
hh ! hh
Status register
N V—BDIZC
bb — bbbbb
h | h
Fig. 16-10 Example 16-1 program analysis.
identify the mnemonic.) Refer to the Expanded Table of
6800 Instructions. Notice that the wait for interrupt instruc¬
tion uses the mnemonic WAI and has an op code of 3E.
Data Transfer Instructions
Look in the Expanded Table at the next entry underneath
the WAI instruction. This is the first entry in the Data
Transfer Instructions section, which is a list of all of the
different types of data transfer instructions available in the
6800/6808 family. (To those with previous microprocessor
experience: You may notice that we have excluded transfer
instructions involving the stack. This is intentional. They
have been included in the Stack Instructions category.)
Direction of Data Transfer
Let’s look at this Data Transfer section a little more closely.
The first instruction listed is the LoaD Accumulator A
instruction. The boldfaced letters show where the LDAA
mnemonic came from. The third column shows the Boolean/
Arithmetic Operation. This is a concise and graphic way
to state exactly what this instruction does. It shows M,
which stands for memory, moving toward A, which stands
for the accumulator. To put it another way, the contents of
a certain memory location are being transferred into the
accumulator.
Recall from the New Concepts section that moving or
transferring is actually more like making a copy of what’s
in a particular location and placing the copy in the desti¬
nation.
Referring to the table, notice that the second (LoaD
Accumulator B) and seventh (LoaD X register) instructions
are similar to the first (LDAA). The difference is that they
copy the contents of a particular memory location and place
it either in accumulator B or in the X register instead of
accumulator A.
It may help to have a mental picture of our programming
model of the 6800, shown in Fig. 16-11, as we discuss
these instructions.
We have talked about moving or copying the contents
of some particular memory location to accumulator A,
accumulator B, or the X register. Now let’s consider doing
the reverse.
Look at the third, fourth, and eighth instructions in the
Expanded Table. They are STAA, STAB, and STX, which
is to say, store the contents of accumulator A in a memory
location, store the contents of accumulator B in a memory
location , and store the contents of the X register in a
memory location , respectively. The STORE instructions
are just the reverse of the LOAD instructions. (Note the
Boolean/Arithmetic Operation column.)
Accumulator A
hh
Accumulator B
hh
X H —X Register—X L
hh | hh
SP H —Stack pointer—SP L
hh | hh
PC H —Program
hh
counter—PC|_
hh
Status register
1 1 H1NZVC
1 1 b b b b b b
h | h
Fig. 16-11 Complete 6800/6808 programming model.
246 Digital Computer Electronics
Continue referring to both the Expanded Table and Fig.
16-11. Instructions 5 and 6 in the Expanded Table (TAB
and TBA) allow you to transfer the contents of accumulator
A and accumulator B between each other.
The last three instructions (CLR, CLRA, and CLRB)
simply transfer or place the number zero in accumulator A
or B or in a memory location.
Op Codes
Does your computer or microprocessor trainer understand
the words “load accumulator A”? No. Does it understand
the mnemonic LDAA? If you are using an assembler, the
assembler translates the mnemonic into binary numbers,
which it does understand. (If you can type the mnemonic
LDAA into your computer or trainer, you have an assembler.
If instead you must use a hexadecimal keypad or type in
hex numbers, you do not have an assembler.) The point
here is that the microprocessor inside your computer does
not understand English words like “load” or mnemonics
like LDAA.
If you are using an assembler, the assembler program is
translating the mnemonics, which the microprocessor does
not understand, into something it does understand. What
does the microprocessor understand? Binary numbers. In
our case we will enter them as their equivalent hexadecimal
value and let the monitor or assembler translate that into
binary. For our purposes, at least at this point, we’ll say
that the microprocessor understands hexadecimal. (The
monitor is part of the firmware built into your microprocessor
trainer.)
Look again at the Expanded Table. If we wanted to tell
the microprocessor to load the accumulator from memory
(the first data transfer instruction, LDAA), the micropro¬
cessor chip would actually need the hex code in the seventh
column over, the op code column (op for short). We would
place the hex number 86, 96, A6, or B6 (depending on
which variation of the instruction we wanted to use) in the
computer’s memory as the first instruction to execute.
(We’ll talk more about these variations later.)
Let’s look at another example. What if you wanted to
have the microprocessor store the contents of the X register
in memory? What would be the hex number the micropro¬
cessor would need to understand what you wanted to do?
You should have said either DF or EF or FF from the STX
instruction.
Sample 6800/6808 Program
Program Objective
Let’s create a program which will
L Place the number 11 in the accumulator.
2. Stop.
Creating the Program
Refer to the Data Transfer Instructions section of the
Expanded Table. Do you see an instruction which could be
used to place a number in the accumulator? Look in the
Boolean/Arithmetic Operation column. You need an instruc¬
tion which has an arrow pointing to the accumulator. There
are three such instructions—LDAA, TBA, and CLRA.
Since we don’t want to involve accumulator B, and since
we don't want to clear accumulator A, LDAA will be our
choice.
The next step is to determine which LDAA instruction
to use. There are four. The key to this decision is in the
Address Mode column. The LDAA instruction which has
Immediate in the address column is the one we want.
Immediate addressing tells the microprocessor that the data
it needs will be coming immediately after the op code. We
will learn more about addressing modes in the next chapter.
Finally, you want the program to stop. The instruction
which does this is in the CPU Control Instructions section
of the Expanded Table. The WAI instruction is the correct
choice.
Entering the Program
The completed program is shown in Fig. 16-12. We’ll see
how to enter it into your microprocessor first by using an
assembler and then without an assembler.
Note that the column labeled Obj contains the actual
6800 op codes, and the Assembler column contains the
mnemonic and data in a format similar to that used by an
assembler.
Assembler
Comment
0000
LDAA #$11
Load the accumulator with the number (11)
immediately following the LDAA# op code (86)
0001
11
0002
Halt
Fig. 16-12 Sample program. (Note: The addresses should
be an area where user programs can be placed. If 0000 is
not such a place on your system, then you will need to
change these addresses.)
Chapter 16 Data Transfer Instructions 247
Refer to the LDAA instruction in the Expanded Table.
To the right of the word Immediate you see LDAA #$dd.
This is in the Assembler Notation column and describes
how many assemblers require that you type this instruction.
With four different LoaD Accumulator A instructions, the
assembler must know which one you want. The format of
the information after the LDAA is how the different forms
of the command are differentiated. The # means that the
data to be used is coming immediately after the command
itself. The $ indicates that it is a hexadecimal number. The
dd simply stands for two hexadecimal digits of data. (Each
d stands for one nibble or 4 bits.)
It is important to remember that we are talking about a
typical assembler format; however, there is no absolute
standard that must be followed. Refer to the manual which
came with your assembler or ask your instructor for
information about your assembler’s format.
We are going to enter this program into memory starting
at location 0000 (hexadecimal). If the trainer you are using
does not allow programs to be placed in these memory
locations, refer to your manual and substitute valid addresses
in place of those shown in Fig. 16-12.
If you are using an assembler, please enter the program
now. It will look similar to what is shown in Fig. 16-13.
Also place Os in accumulator A, accumulator B, and the
X (index) register so that you will know what numbers are
in each register before you run the program. Refer to Fig.
16-14 to see what the memory and registers should look
like.
If you are not using an assembler, you must look up the
op codes by hand in the Expanded Table. This is called
hand-assembly. Let’s go through the necessary steps for
hand-assembly.
To the right of the LDAA #$dd, in the op code (op for
short) column you will see the hexadecimal number 86.
This is the 6800/6808 op code, which stands for Load
accumulator A with the number immediately following this
op code . Set your trainer so that the memory address where
the next instruction will be loaded is someplace within the
area allowed for user programs. We chose 0000, but you
may need to use another location. Enter the number 86 into
the first available memory location. Since this was a Load
Accumulator A Immediate instruction, the microprocessor
will expect the next address, which immediately follows
the op code, to contain the number which is to be placed
in accumulator A. Therefore enter 11 next. In the third
Address Op code Data Mnemonic Immediate Hex Data
0000 86 11 LDAA#$11
0002 3E WAI
Fig. 16-13 Disassembly of the sample program.
Memory
Fig. 16-14 6800/6808 sample program.
address enter 3E, which is the op code for the WAI
instruction.
Enter 0s into accumulator A, accumulator B, and the X
(index) register now so that you will know the condition
of these registers before the program is run.
If you check your registers and memory, you should see
what is shown in Fig. 16-14 (although you may have placed
the program at a different memory location). The h’s and
b’s represent hex and binary digits which we are not
concerned with now.
Running the Program
Let’s use Fig. 16-15 during our analysis of program
operation.
The first op code is 86, which means, Load accumulator
A with the contents of the next memory location, or more
properly, Place a copy of the contents of the next memory
location in accumulator A. As you see, the number 11 is
A 0002
d
. 0003
Memory
Fig. 16-15 6800/6808 sample program.
248 Digital Computer Electronics
Addr
Obj
Assembler
Comment
0000
86
LDAA #$EE
Load accumulator A with the hex number
immediately following the LDAA# op code (86)
0001
EE
0002
16
TAB
Transfer the contents of A into B
0003
3E
WAI
Stop
Fig. 16-16 Example 16-2 program.
replacing 00 in the accumulator. The program then continues
to the next instruction op code, 3E, which stands for WAI,
and stops.
Checking the Results of Program (Analysis)
After running the program, you should have 00 in accu¬
mulator B and the X (index) register and 11 in accumulator
A. The program docs what we designed it to do.
Here’s one for you to try.
EXAMPLE 16-2
First manually place 00s in accumulator A, accumulator B,
and the X register. Then write a program which will
1. Load accumulator A with the hex number EE.
2. Transfer a copy of the contents of the accumulator A
into accumulator B.
3. Stop.
SOLUTION
Figure 16-16 shows the completed program. Figure 16-17
shows the memory and registers and what happens during
program execution.
16-5 8080/8085/Z80 FAMILY
Let’s see how the ideas which were introduced in the New
Concepts section apply to the 8080/8085/Z80 microproces¬
sor family.
CPU Control Instructions
The 8080/8085/Z80 family has a no operation instruction
which uses the mnemonic NOP. Refer to the Expanded
Table of 8085/8080 and Z80 (8080 Subset) Instructions
Listed by Category in Part 4 of this text.
In the ninth column, called the Boolean/Arithmetic
Operation column, we see that this instruction does “noth¬
ing?” as we said it would. Also notice the hexadecimal
number under the op (op code) column, in this case 00.
This is the actual hex code for NOP.
The 8080/8085/Z80 family has an actual halt instruction.
Refer to the Expanded Table again. Notice that the halt
instruction uses the mnemonic HLT [Z80 = HALT] and
has an op code of 76.
Data Transfer Instructions
Refer to the Expanded Table. Underneath the halt instruction
you will see the MOV A,A [Z80 = LD A,AJ instruction
Memory
0000
86
0001
EE-
0002
16
0003
3E
0004
hh
0005
hh
0006
hh
0007
hh
0008
hh
0009
hh
1. Load EE into
accumulator A **
— 2. Transfer A into B-
Accumulator A
EE
EE
X H —X register—X L
00 | 00
SP H —Stack pointer—SP L
hh | hh
PC H —Program
hh
counter—PC L
hh
Status register
1 1 H1NZVC
1 1 b b b b b b
h | h
Fig. 16-17 Example 16-2 program analysis.
Chapter 16 Data Transfer Instructions 2 49
at the beginning of the Data Transfer Instructions section.
This section is a list of all of the different types of data
transfer instructions available in the 8080/8085/Z80 family.
(To those with previous microprocessor experience: You
may notice that we have excluded transfer instructions
involving the stack. This is intentional. They have been
included in the Stack Instructions category.)
Direction of Data Transfer
Let’s look at the data transfer section a little more closely.
The second instruction listed is the MOVe data to A from
B instruction. The boldfaced letters help show where the
MOV A,B mnemonic came from. (If you are using the Z80
microprocessor, it is the LoaD data into A from B instruc¬
tion. The boldfaced letters show where the LD A,B
mnemonic came from.) The ninth column shows the Boo¬
lean/Arithmetic Operation. This is a concise and graphic
way to state exactly what this instruction does. It shows B,
which stands for register B, moving toward A, which stands
for the accumulator. To put it another way, the contents of
register B are being transferred into the accumulator.
Recall from the New Concepts section that moving or
transferring is actually more like making a copy of what’s
in a particular location and placing the copy in the desti¬
nation.
It may help to have a mental picture of our programming
model of the 8085/8080/Z80, shown in Fig. 16-18, as we
discuss these instructions.
There are many directions in which data could be
transferred with an accumulator, six registers, and memory.
This can be seen in the Expanded Table. The first eight
instructions transfer the contents of a register or memory
location into the accumulator. (This can be seen in the
Operation column and the Boolean/Arithmetic Operation
column.) The second group of eight instructions copy the
contents of the accumulator, one of the registers, or memory
into register B. The third group of eight transfer data into
register C. The fourth group into D. The fifth into E. The
sixth into H. The seventh into L. And the eighth into a
memory location. This makes 8 x 8 or 64 instructions just
to do simple data transfers between registers.
The next group of eight instructions consists of the Move
Immediate instructions. They move a specified number
directly into a register or memory.
We will leave it to you to glance at the rest of the data
transfer instructions in the Expanded Table.
If you have used the 6502 family or 6800/6808 family
chips before (especially the 6502 family) and are now
studying the 8085/Z80 family for the first time, you may
be surprised by the great number of different instructions
this family has. This is offset, however, by the relatively
few addressing modes available and the simplicity this can
offer the programmer. (The 6502 family, by contrast, has
very few different instructions but has a large number of
addressing modes for an 8-bit chip from its era.)
Op Codes
Does your computer or microprocessor trainer understand
the statement “Move data to A from B”? No. Does it
understand the mnemonic MOV A,B? If you are using an
assembler, the assembler translates the mnemonic into
binary numbers, which it does understand. (If you can type
the mnemonic MOV A,B into your computer or trainer,
you have an assembler. If instead you must see a hexade¬
cimal keypad or type in hex numbers, you do not have an
assembler.) The point here is that the microprocessor inside
your computer does not understand English words like
“Move” or mnemonics like MOV A,B.
Memory
0000
hh
0001
hh
0002
hh
0003
hh
0004
hh
0005
hh
0006
hh
0007
hh
0008
hh
0009
hh
000A
hh
Fig. 16-18 Complete 8080/8085 and Z80 (8080 subset)
programming model.
—
Accumulator
hh
Register B
hh
Register C
hh
Register D
hh
Register E
hh
Register H
hh
,_i
Register L
hh
i _
SP H —Stack pointer—SP|_
hh | hh
PCh—P rogram
hh
counter—PC L
hh
Status register
S Z — A — P — C
bb—b —b —b
h | h
250 Digital Computer Electronics
If you are using an assembler, the assembler program is
translating the mnemonics, which the microprocessor does
not understand, into something it does understand. What
does the microprocessor understand? Binary numbers. In
our case we will enter them as their equivalent hexadecimal
value and let the monitor or assembler translate that into
binary. For our purposes, at least at this point, we’ll say
that the microprocessor understands hexadecimal. (The
monitor is part of the firmware built into your microprocessor
trainer.)
Look again at the Data Transfer section of the table. If
we wanted to tell the microprocessor to load the accumulator
from register B (the second data transfer instruction, MOV
A-B [LD A,B], the microprocessor chip would actually
need the hex code in the eighth column over, the op code
column (op for short). We would place the hex number 78
in the computer’s memory as the first instruction to execute.
Let s look at another example. What if you wanted to
have the microprocessor copy the contents of the C register
into the accumulator? What would be the hex number the
microprocessor would need to understand what you wanted
to do? You should have said 79 from the MOV A,C
[LD A,C] instruction.
Sample 8085/Z80 Program
(Note: Since we are simultaneously covering the 8085 and
Z80 microprocessors, we will give the 8085 mnemonic
first, followed by the Z80 mnemonic in italic print and
enclosed by square brackets, for example, MVI A dd ILD
A,ddJ.)
Program Objective
Let’s create a program which will
1. Place the number 11 in the accumulator.
2. Stop.
Creating the Program
Refer to the Data Transfer Instructions section of the
Expanded Table. Do you see an instruction which could be
used to place a number in the accumulator?
[Note: You may want to use the Mini Table of 8085/Z80
(8080 Subset) Instructions listed by Category at this time.
There are so many 8085/Z80 data transfer instructions that
it may prove to be a bit time-consuming to page through
the Expanded Table.]
Look in the Boolean/Arithmetic Operation column (sim¬
ply labeled Operation in the Mini Table). You need an
instruction which has an arrow pointing to the accumulator
(indicated by an A). There are 12 such instructions; using
8085 mnemonics, they are MOV A,A; MOV A,B; MOV
A,C; MOV A,D; MOV A,E: MOV A,H; MOV A,L; MOV
A'M; MVI A,dd; LDAX B; LDAX D; and LDA aaaa.
[Using Z80 mnemonics, they are LD A,A; LD A,B; LD
A,C; LD A,D: LD A,E; LD A,H: LD A,L; LD A, (HL); LD
A,dd; LD A, (BC); LD A, (DE); and LD A, (aaaa)./
The next step is to determine which one of these
instructions to use. The key to this decision can be found
in the Operation or (Boolean/Arithmetic Operation) column.
The data transfer instruction we want is one which will
take a number (which we will place immediately after the
instruction op code) and will transfer it into the accumulator.
The first eight instructions mentioned above take a number
which is already in one of the seven 8085/Z80 registers or
memory and place it in the accumulator. This is not what
we want. The last three instructions take a number or data
byte from a memory location and place it in the accumulator.
This is not what we want either. The MVI A.dd (MoVe
Immediate dd to A) [Z80 = LD A, dd (LoaD dd into A)]
instruction takes the number immediately following the
move instruction and places it in the accumulator. This is
what we want since it allows us to specify the number 11
right after the op code for the move instruction.
Finally, you want the program to stop. The instruction
which does this is in the CPU Control Instructions section.
The halt instruction is the obvious choice.
Entering the Program
The completed program is shown in Fig. 16-19. We’ll see
how to enter it into your microprocessor first using an
assembler and then without an assembler.
Note that the column labeled Obj contains the actual
8085 and Z80 op codes, and the Assembler column contains
the mnemonic and data in a format similar to that used by
an assembler.
Refer to the MVI A,dd [LD A,dd] instruction in the Mini
Table. These mnemonics are used by assemblers, which
means that you must type the instruction using this format.
To the right of the mnemonic, in the Op column, is the op
code for that particular instruction. The 8085 and Z80
microprocessors use the same op codes: Only the mnemonics
are different. The dd simply stands for two hexadecimal
digits of data. (Each d stands for one nibble or 4 bits.)
We are going to enter this program into memory starting
at location 0000 (hexadecimal). If the trainer you are using
does not allow programs to be placed in these memory
locations, refer to your manual to determine where programs
can be placed in memory and substitute those addresses.
If you are using an assembler, please enter the program
now. It will look similar to what is shown in Fig. 16-20.
Also place 0s in the accumulator and all the general-
purpose registers (registers B, C, D, E, H, and L) so that
you will know what numbers are in each register before
you run the program. Refer to Fig. 16-21 to see what the
memory and registers should look like.
If you are not using an assembler, you must look up the
op codes by hand in either the Expanded Table or the Mini
Table. This is called hand assembly . Let’s go through the
necessary steps for hand assembly.
Chapter 16 Data Transfer Instructions 251
8085 rr^nemonics
Addr
Obj
Assembler
Comment
0000
3E
MVI A, 11
Load the accumulator with the number (11)
immediately following the MVI op code (3E)
0001
11
0002
76
HALT
Halt
Z80 mnemonics
Addr
Obj
Assembler
Comment
0000
3E
LD A, 11
Load the accumulator with the number (11)
immediately following the LD A,dd op code (3E)
0001
11
0002
76
HALT
Halt
Fig. 16-19 Sample program. (Note: The addresses should
be an area where user programs can be placed. If 0000 is
not such a place on your system, then you will need to
change these addresses.)
If you look up the MVI A,dd [LD AM] mnemonic in
either the Expanded Table or the Mini Table (for the 8080/
8085/Z80), you will see the hex number 3E in the Op
column. This is the op code which stands for, ”MoVe the
number Immediately following this op code into the Ac¬
cumulator.” [*'.LociD the number following this op code
into the Accumulator . * 9 ] Set your trainer so that the memory
address where the next instruction will be loaded is some¬
place within the area allowed for user programs. We chose
0000, but you may need to use another location. Enter the
hex number 3E into the first available memory location.
Since this was a MoVe Immediate to Accumulator [LoaD
Accumulator] instruction, the microprocessor will expect
the next address, which immediately follows the op code,
to contain the number which is to be placed in the
accumulator. Therefore enter 11 next. In the third address
enter 76, which is the op code for the halt instruction.
8085 mnemonics
Address Opcode Data Mnemonic Source Destination
0000 3E 11 MVI A, 11
0002 76 HALT
Z80 mnemonics
Address Op code Data Mnemonic Source Destination
0000 3E 11 LD A, 11
0002 76 HALT
Fig. 16-20 Disassembly of the sample program.
Enter 0s into the accumulator and all the general-purpose
registers at this time so that you will know the conditions
of these registers before the program is run.
If you check your registers and memory, you should see
what is shown in Fig. 16-21 (although you may have placed
the program at a different memory location). The h's and
b’s represent hex and binary digits which we are not
concerned with at this time.
Running the Program
Let’s use Fig. 16-22 during our analysis of program
operation.
The first op code is 3E, which means, Load the accu¬
mulator with the contents of the next memory location , or
Accumulator
00
Register B
00
Register C
00
Register D
00
:
Register E
00
—
Register H
00
___i
Register L
00
SP H —Stack pointer—SP L
hh | hh
PC H —Program
hh
counter—PC L
hh
Status register
SZ —A —P —C
b b — b — b — b
h | h
Fig. 16-21 8085/Z80 sample program.
252 Digital Computer Electronics
Memory
0000
3E
New number (11)
Accumulator
0001
11
|—replacing old number (00) —
—► 11 00 —►
Register B
00
Register C
00
0002
76
0003
hh
Register D
00
Register E
00
L
UUU4
hh
Register H
00
■ _
Register L
00
i_
0005
hh
0006
hh
SP H —Stack pointer—SP L
hh 1 hh
0007
....
....
hh
PC H —Proaram counter—PC, 1
0008
hh
hh
hh
0009
hh
Status register
SZ —A —P —C
000A
hh
b b — b — b — b
h | h
Fig. 16-22 8085/Z80 sample program.
more properly, Place a copy of the contents of the next
memory location in the accumulator . As you see, the
number 11 is replacing 00 in the accumulator. The program
then continues to the next instruction op code, 76, which
stands for halt, and stops.
Checking the Results of Program (Analysis)
After running the program, you should have 00 in all the
general-purpose registers and 11 in the accumulator. The
program does what we designed it to do.
Here’s one for you to try.
EXAMPLE 16-3
First manually place 00s in the accumulator and all general-
purpose registers. Then write a program which will
1. Place the hex number EE in the accumulator.
2. Move (copy) the contents of the accumulator (A) into
register B.
3. Move (copy) the contents of the accumulator (A) into
register C.
4. Stop.
SOLUTION
Figure 16-23 shows the completed program in both 8085
and Z80 mnemonics. Figure 16-24 shows the memory and
registers and what happens during program execution.
16-6 8086/8088 FAMILY
We will approach the 16-bit 8086/8088 microprocessor a
little differently than we did the 8-bit microprocessors. The
8-bit sections are designed to fit the needs of a person using
op code charts and hand assembly in the earlier chapters
and an assembler in the later chapters.
In the 16-bit section we assume that you are using the
DOS DEBUG utility in the earlier chapters. DEBUG is
readily available to all who use MS-DOS—type machines,
and it is less sophisticated than assemblers, which keeps
you closer to the hardware during the early part of the
learning process.
In later chapters we will use both an assembler and
DEBUG in figures and in answers to chapter questions.
This will allow you to explore the advantages of a full-
featured assembler and to continue to use DEBUG if you
wish.
One final point should be kept in mind. This text is
designed to make the learning process as simple as possible
for the beginner. A 16-bit chip like the 8086/8088 is quite
complex for the beginner. Therefore we do not attempt to
cover every aspect of this chip.
CPU Control Instructions
The 8086/8088 has a no operation (NOP) instruction which
works as described in the New Concepts section of this
chapter. A brief description of the NOP instruction can be
found in the CPU Control Instructions section of the
Expanded Table of 8086/8088 Instruction Listed by Cate¬
gory in Part 4 of this text. The NOP has an op code of 90
and affects no flags.
The 8086/8088 has a halt instruction which functions as
described in the New Concepts section. A description of
this instruction appears in the CPU Control Instructions
section of the 8086/8088 instruction set. Its mnemonic is
HLT, and its op code is F4.
Chapter 16 Data Transfer Instructions 253
8085 mnemonics
IBB
Assembler
Comment
0000
3E
MVI A,EE
Place the hex number EE in the
accumulator (A)
EE
0002
47 '
MOV B,A
Copy into register B the contents of A
0003
4F
MOVC, A 1
Copy into register C the contents of A
0004
76
HALT
Stop
Z80 mnemonics
Addr
Obj
Assembler
Comment
0000
3E
LD A,EE
Place the hex number EE in the
accumulator (A)
0001
EE
0002
47
Copy into register B the contents of A
0003
4F
Copy into register C the contents of A
0004
76
1
Stop
Fig. 16-23 Example 16-3 program.
Data Transfer Instructions
The 8086/8088 has eight instructions which we have placed
in the Data Transfer Instructions section. While the Ex¬
panded Table of 8086/8088 Instructions Listed by Category
lists all eight of these instructions, the most versatile and
by far the most useful for the beginner is the MOVe
instruction.
A copy of our programming model for the 8086/8088
appears in Fig. 16-25.
Direction of Data Transfer
A move can be from (source) a register, memory, or an
immediate number to (destination) a register or memory.
While either the source or the destination can be a memory
location, both cannot be memory locations in the same
instruction. The source and destination must both be either
8 bits wide or 16 bits wide; you can’t mix data widths in
the same instruction. And finally, you can’t move from one
segment register to another.
As you have seen from the programming model, the
8086/8088 has several 8-bit and 16-bit registers. This causes
the number of move combinations between registers alone
to number in the hundreds. A few examples are
MOV
AL.DL
AL <-
-DL
MOV
BH.BL
BH
-BL
MOV
AX.DX
AX DX
MOV
SP.BP
SP <-
BP
MOV
SI.DI
SI <-
DI
MOV
BX.DS
BX
DS
MOV
AL.76
AL
76
A
d
d
r
e
s
s
e
s
Memory
0000
3E
0001
EE-
0002
47
0003
4F
0004
76
0005
hh
0006
hh
0007
hh
0008
hh
0009
hh
000A
hh
-► 1. EE copied into A -
I- EE copied from A
— 2. Into B ■
^— 3. Into C '
Accumulator
-► EE
- -
Register B
EE !
—
Register C
EE
Register D i
00
Register E
00
Register H
oo !
_i
Register L
00
SP H —Stack pointer—SP L
_M
hh |
PC H —Program counter—PC l
hh
hh
Status register
SZ —A —P —C
bb— b — b — b
h I h
Fig. 16-24 Example 16-3 program analysis.
254 Digital Computer Electronics
Memory
0100
hh
0101
hh
0102
hh
0103
hh
0104
hh
0105
hh
0106
hh
0107
hh
0108
hh
A
d
0109
hh
d
010A
hh
r
010B
hh
e
s
010C
hh
s
010D
hh
e
s
010E
hh
010F
hh
0110
hh
0111
hh
0112
hh
0113
hh
0114
hh
0115
hh
0116
hh
.
0117
hh
Fig. 16-25 8080/8086 programming model.
AH
-Accumulator AX-
i
i
AL
hh
i
hh
BH
case da "
i
i
BL
hh
i
i
i i n 1 ^ V __
hh
CH
couni ca
i
CL
hh
i
hh
DH
uaxa ua ■—
i
DL
hh
i
j
hh
Source index
hhhh
Destination index
hhhh
Stack pointer
hhhh
Base pointer
hhhh
Code segment
hhhh
Data segment
hhhh
Extra segment
hhhh
Stack segment
hhhh
New
Instruction pointer
hhhh
■ Flags -
-0
-b
D I T
b b b
8085-like
Z — A — P — C
b — b — b — b
MOV
AX,89E3
AX ^ 89E3
MOV
[1234], AX
memory location
1234 <- AX
MOV
BL,[4456]
BL memory
location 4456
MOV
DX,[BX + DI]
DX memory
location found by
adding the
contents of BX
and DI
MOV
AX,[BX + DI + 0200]
AX <— memory
location pointed to
by the sum of the
contents of BX,
the contents of
Dl, and the hex
number 200, 6
The left column shows the instruction exactly as it appears
when disassembled by DEBUG. The right column indicates
where the data comes from and where it goes.
Sample 8086/8088 Program
Figure 16-26 shows a sequence of commands that will
demonstrate a simple MOVe instruction and give you
practice entering programs into DEBUG.
First, we started DEBUG by typing
C>debug
at the DOS prompt as shown. DEBUG responded with a
which indicates it is waiting for a command.
Chapter 16 Data Transfer Instructions 255
ODEBUG
ftX=0000 BX=0000 CX=0000 DX=0QD0 SP=bD5E BP=0000 SI=QQD0 DI=D000
DS-*H2A ES = c n2A SS-T^A CS-V12A IP=0100 NV UP El PL NZ NA PO NC
n2A:0100 7420 JZ 0122
-a
qR2R:0inD mov al/dl
qqEArDlDE
-u 1UU 101
qqEA:flfiDD MOV AL ,DL
-r
AX=0DDD BX=00nD CX=D0DD DX=0DDD SP=LDBE BP=0Q[]D SI=D00D DI=DDDD
Ds=qqaA ES-qqaA ss=qqaA cs=qqaA ip=oido nv up ei pl nz na po nc
qqpArDicm sado mov al,dl
-rdx
DX □□□□
: DDf3
-r
AX=DDD0 BX=D0D0 CX=DD00 DX=D DF3 SP=LDBE BP=QDDD SI=DDDQ DI=D000
Ds=qqaA ES-qqaA ss=qqaA cs-bbea ip=dido nv up ei pl nz na po nc
qqEA:01DD A ADO MOV AL,DL
-t
AX-D0E3 BX=0DDD CX=DDQD DX=D0F3 SP=LDBE BP=0DD0 SI=0D0D DI=0CIQ0
DS=qq2A Es^qqaA ss=qqEA cs^bbea ip=oioe nv up ei pl nz na po nc
qqa a:dide lb db lb
-q
c>
Fig. 16-26 MOVe instruction (DEBUG screens).
Next we typed an “r,” which stands for register. This
causes DEBUG to display the values of all registers as
shown in Fig. 16-27.
We will now duplicate (several times) that portion of
Fig. 16-26 (in bold type) which shows the values in various
registers. You should compare these sections (as we progress
through each figure) to our 8086/8088 programming model
in Fig. 16-25.
The current values of the general-purpose registers are
shown in bold type in Fig. 16-28.
The values of the stack pointer, base pointer, source
index, and destination index are shown in bold type in Fig.
16-29.
-r
AX=0DDD BX=0000 CX=D0D0 DX=D0D0 SP=LDBE BP=DDDD SI=DDD0 DI=000D
DS=qqaA es^bbea ss=qqaA cs=qqaA ip=oidd nv up ei pl nz na po nc
qqaA:Dicm ?4ED jz oiaa
Fig. 16-27 DEBUG screens (cont.).
-r
AX = D00D BX = D00D CX = DD00 DX = DODD SP=LD5E BP^ODOD SI^OQOD DI=DDDD
DS=qqaA es^bbea ss^bbea cs=qqaA ip=qidd nv up ei pl nz na po nc
qqEA:74 ED JZ D1EE
Fig. 16-28 DEBUG screens (cont.).
-r
AX=0DDQ BX=DDDD CX=DDDD DX=0Q0D SP=bDSE BP=000D SI=0a00 DI=DDDD
ds— qqa a es=bbea ss^bbea cs^bbea ip=didd nv up ei pl nz na po nc
qqEA: U1UU 74ED JZ aiEE
Fig. 16-29 DEBUG screens (cont.).
The values in the segment registers are shown in bold in
Fig. 16-30.
The value of the instruction pointer and the current status
of the flags are shown in bold in Fig. 16-31.
Finally, the address, op code, and assembler notation for
the next instruction which is to be executed are shown in
bold type in Fig. 16-32.
The area shown in bold type in Fig. 16-33 illustrates
how we then typed an "a,” which is the DEBUG assemble
command, at the DEBUG prompt.
-a <ENTER>
256 Digital Computer Electronics
AX=DOOD BX=ODOD
DS=qq2A ES=iq2A
qq5A:DlDD 7A50
Fig. 16-30 DEBUG screens (cont.).
CX-DQDD DX-00D0 SP=tD5E BP=0QQQ SI=00DQ DI=DDDD
ss-qqeA cs=qqsA ip=dioo nv op ei pl nz na po nc
JZ 0155
Fig. 16-31 DEBUG screens (cont.).
-r
AX=DDD0 BX=0000
DS=qq5A Es=qq5A
^EArDlDO 74 50
CX-0000 DX-0000 SP=LDSE BP=0000 SI=D000 DI=0000
SS-TTEA CS=qq 2 A IP=0100 NV UP EI PL NZ NA PO NC
JZ 0152
-r
AX=0000 BX=0000 CX=0DQD DX
DS=q95A ES=qSEA SS=RR5A CS
C HEA :0100 74 E 0 JZ
Fig. 16-32 DEBUG screens (cont.).
ODEBUG
-r
AX=0000 BX=00DD CX=D000 DX
DS=qqEA ES=qq5A SS=qq5A CS:
qq5A:010D 745D JZ
-a
qq2A:01DD mov al,dl
qq5A:010E
-u 1 DD 101
qqpA:D10D flflDO MOV
-r
AX=0000 BX=0000 CX=0000 DX
DS=qq5A Es^qqaA ss=qq2A cs:
qqEA:01DD flflDO MOV
-rdx
DX 0000
: OOf 3
-r
AX=0000 BX=00QQ CX=D000 DX=
DS=qq5A ES=qq5A ss=qq2A cs^
qqEA:01DD flflDO MOV
-t
0000 SP=LD5E BP=0000 SI=0000 DI=DD0D
qq5A IP=0100 NV UP ei pl nz na po nc
01 EE
0000 SP=LD5E BP=000Q SI=0Q00 DI=000D
qqEA IP=0100 NV UP ei pl nz na po nc
01 EE
AL , DL
□000 SP=LD5E BP=0000 Sl=0000 Dl=0000
qS5A IP=010D NV UP El PL NZ NA PO NC
AL, DL
000D SP=LD5E BP=000Q SI=0D00 DI=00D0
qR5A IP=01DD NV UP EI PL NZ NA PO NC
AL, DL
CX-DOOD DX-DDF3 SP=LD5E BP=DDDO SI=000D DI=DDDQ
ss=qqaA cs=qqEA ip=oios nv up ei pl nz na po nc
DB L5
C>
Fig. 16-33 DEBUG screens (cont.).
AX=D0F3 BX=DD00
DS=qq5A ES=qqo a
qqEArDIDE LS
-q
DEBUG then responded with
992A:0100
which is the address at which our program will start. The
992A is the memory segment, and 0100 is the memory
location within that segment. If you try this program on
your computer, your segment will probably not be the same
as ours. This is normal and will not affect the results ot
the program.
We then typed
mov al,dl <ENTER>
and DEBUG responded with
992A:0102
which is the address of the next available memory location.
We then pressed <ENTER> to terminate assembly, and
DEBUG waited for our next command.
Chapter 16 Data Transfer Instructions 257
We told DEBUG to create or assemble the machine code
for the MOV AL,DL instruction. Then we wanted to check
to see that this is what DEBUG did. We wanted to
disassemble the machine code. The DEBUG command for
this is “u,” which stands for unassemble (DEBUG’s name
for disassemble). The next command in our program is
-u 100 101
which tells DEBUG to unassemble memory locations 100 l6 -
101 J<5 within the current code segment. DEBUG responded
with
992A:0100 88D0 MOV AL,DL
992A is the current code segment. 0100 is the memory
location of the first byte of this instruction. 88DO is the
machine code for MOV AL.DL, which was the assembly-
language instruction we typed in.
We typed the register command, and DEBUG again
displayed the current status of all registers. DEBUG’s
response is shown in Fig. 16-34.
When DEBUG displays the registers, it also displays the
instruction which it finds at the memory location pointed
to by the instruction pointer in the current code segment.
These appear in bold type in Fig. 16-34. Our MOV AL,DL
instruction appears in the assembly-language section.
Since our instruction said to move the contents of register
DL to register AL, we needed to place some value in
register DL. Notice that at this point AX, BX, CX, and
DX all contained 0000. Even if the contents of DL were
copied to AL, we wouldn’t see any difference. We needed
to place some value in DL which we could observe.
The area in bold type in Fig. 16-35 shows our next
command
-rdx
which told DEBUG we wanted to change the value in
register DX. DEBUG responded with
DX 0000
which was the current contents of register DX. The cursor
waited after the colon. If we had typed in a value, that
value would have been placed in the DX register. If we
had pressed the <ENTER> key, the value in DX would
not have changed.
-r
AX=0000 BX=0000
DS= C ISBR ES^RRaA
lIBi:0100 flflDO
Fig. 16-34 DEBUG screens (cont.).
ODEBUG
-r
AX=0000 BX=0000
DS=qqaA ES=qqaA
qqaA:0100 7430
-a
qq3A:0100 mov al,
qqaA:oioa
-u 100 101
qqaA:oioo flfiDO
-r
AX=0000 BX=0000
DS=qqaA Es=qqaA
RRBA:0100 flflDO
-rdx
DX 0000
: OOf 3
-r
AX=000D BX=0Q00
DS=RRBA ES=R c iaA
qqaA:oioo aado
-t
AX=00F3 BX=0000
DS=qqeA Es=qqaA
qqaA:oioa ts
-q
CX=0000 DX=0000 SP=LDSE
ss=qqaA cs=naA ip=oioo
BOV AL,DL
CX=0000 DX=0000 SP=LD5E
ss=qqaA cs=qqaA ip=oioo
jz oiaa
dl
MOV AL,DL
CX=0000 DX=0000 SP=fcD5E
ss=qqaA cs=qqaA ip=oioo
MOV AL,DL
CX=0000 DX=00F3 SP=LDSE
ss=qqaA cs=qqaA ip=oioo
MOV AL,DL
CX=0000 DX=00F3 SP=LD5E
ss=qqaA cs=qqaA ip=oioa
DB LS
BP=0000 SI=D000 DI=0000
NV UP El PL NZ NA PO NC
BP=0000 SI=0000 DI=0000
NV UP El PL NZ NA PO NC
BP=0000 SI=0000 DI=0000
NV UP El PL NZ NA PO NC
BP=0000 SI=0000 DI=0000
NV UP El PL NZ NA PO NC
BP=0000 SI=0000 DI=000Q
NV UP El PL NZ NA PO NC
C>
Fig. 16-35 DEBUG screens (cont.).
258 Digital Computer Electronics
We wanted to place a new number in DL. However, we
could not single out the low byte of the DX register, so we
simply placed Os in the high byte and our number in the
low byte. We typed that number (0Gf3) and pressed
<ENTER>.
:00f3 < ENTER >
Figure 16-36 shows how we again used the register
command (“r”).
Notice that the value in register DX has been changed
to the value we typed in.
Running the Program
Next we wanted the computer to execute the MOV AL,DL
instruction. However, we did not want it to continue any
further than that. Even though we had not entered any other
instruction into the computer, there were others. When we
turned the computer on, each unused memory location
contained some number, even if it was 00 16 . Most of these
random numbers were actually the op code for some
instruction. We didn t want these “random” instructions
to execute .
DEBUG has a command called trace which executes the
next instruction (the one displayed at the bottom of the
register display) and then stops and automatically displays
the contents of the registers for viewing. This is what we
did in Fig. 16-37.
Notice that the value in DX has been copied into register
AX. Notice also that the Instruction Pointer has been
incremented to the position ot the next instruction in memory
-r
AX=D0D0 BX=DDDD
RHEArDlDD A ADD
Fig. 16-36 DEBUG screens (cout.L
-t
which is displayed at the bottom of the register display (in
bold type).
Checking the Results
Figure 16-38 shows the operation of the program by using
our programming model to illustrate the movement of F3
from one register to the other.
Our program worked. In the future we will not discuss
each 8086/8088 program in such detail, but we have done
so here to give you an idea of how to monitor the execution
of a program. We have also introduced you to some DEBUG
commands. Remember that the DEBUG commands_ as¬
semble, unassemble , trace , register , and quit —are not
assembly-language instructions but are commands to the
DEBUG utility, which helps you to enter, modify, and
execute assembly-language instructions.
Finally, you may want to exit from the DEBUG program.
That command is simply the quit command, which is
entered with the letter q. You will then be returned to the
DOS prompt.
EXAMPLE 16-4
Place the number FE in register DH. Place the number 12
in DL. Then write a program that will
1. Copy DH to AH.
2. Copy DL to BH.
Use the trace command to execute the program and follow
its operation.
CX=DDDD
ss=qqeA
DX=00F3
CS=qqDA
MOV
SP=bD5E
IP=010D
AL, DL
BP=000D SI=0DD0 DI=0DDQ
NV UP El PL NZ NA P0 NC
AX=00F3 BX=D00D
DS=qq^A Es=qq^A
TT2A: 0102 b5
Fig. 16-37 DEBUG screens (cont.).
CX=0000 DX=00F3 SP=bD5E
ss=qq£A cs=qq^A ip=oio2
DB b5
BP=000D SI=DD0D DI=D000
NV UP El PL NZ NA PO NC
Memory
Accumulator AX
!
0100
88
AH
AL
0101
DO
hh
\
F3
DaSe DA"
0102
hh
BH
hh
!
i
BL
hh
0103
hh
CH
Co u n LCX -
!
CL
0104
hh
hh
1
- n nv
hh
uata ux -
0105
hh
DH
hh
j
DL _
F3
[
Fig. 16-38 MOVe instruction (programming model).
Chapter 16 Data Transfer Instructions 259
ODEBUG
-r
AX=0000 BX=0000
DS= C IBFB E5= C IBFB
3BFB:0100 A3FF72
-rdx
DX □□□□
: felB
-r
AX=0000 BX=Q000
DS =C IBFB ES= C IBFB
3BFB:0100 A3FF72
CX=0000 DX=DQ0Q SP=404E
SS=9BFB CS=3BFB IP=0100
MOV [7 2FF],AX
CX=0000 DX=FE12 SP=404E
SS =C IBFB CS =C IBFB IP=0100
MOV [7 2FF],AX
-a
3BFB:0100 mov ah,Ah
1BFB:Q102 mov bh,dl
IBFB:0104
BP=0000 SI=0000 DI=00D0
NV OP El PL NZ NA P0 NC
DS :72FF=FF1F
BP=0000 SI=0000 DI=0000
NV UP El PL NZ NA PO NC
DS :72FF=FF1F
-r
AX^OOOO BX=0000 CX=0000 DX=FE12 SP=404E
DS =C IBFB ES=RBFB SS =C IBFB CS=9BFB IP=Q100
3BFB:0100 AfiF4 MOV AH,DH
-t
BP=0000 SI=0000 DI=0000
NV OP El PL NZ NA PO NC
AX=FE00
BX=0000
CX=0000
DX=FE1E
DS=9BFB
ES= C IBFB
SS^BFB
CS= c IBFB
3BFB:0102
-t
6QD7
MOV
BH
AX=FE00
BX=1200
CX = 0000
DX^FEIB
DS=9BFB
ES=9BFB
SS =C IBFB
CS=HBFB
SBFB:0104
3C3 A
CMP
1 AL
SP=404E bp=oooo si=oooo di=oddq
IP=D 102 NV OP El PL NZ NA PO NC
DL
SP=404E BP=0000 SI=0000 DI=0000
IP=01Q4 NV OP El PL NZ NA PO NC
3 A
Fig. 16-39 Example 16-4 (DEBUG screens).
SOLUTION
Figure 16-39 shows the process of changing the contents
of the registers, entering the assembly-language instructions,
and tracing program execution. Especially notice the areas
in bold type. (They, of course, will not appear in bold on
your computer screen.)
Figure 16-40 shows the same program, illustrating the
movement of the data with our programming model.
Memory
0100
88
0101
F4
0102
88
0103
D7
0104
hh
0105
hh
Fig. 16-40 Example 16-4 (programming model).
-Accumulator AX -
AH
FE
BH
12
CH
hh
DH
FE
-Base BX-
-Count CX-
-Data DX-
AL
hh
BL
hh
CL
hh
DL —,
12
260 Digital Computer Electronics
SELF-TESTING REVIEW
Read each of the following and provide the missing words.
Answers appear at the beginning of the next question.
1* The various instructions which form the instruction
set of most microprocessors fall into natural
-or groups.
2. ( categories) The_and_are the
microprocessor chips found in IBM PC compatibles.
3. (8086, 8088) A technique which is sometimes help¬
ful when analyzing a program involves_
the contents of each register or memory location and
updating each as it changes in the program.
4. ( writing ) When we talk of moving, loading, transfer¬
ring, or storing data, while working with the micro¬
processors in this text, are we referring to moving in
the sense that the data no longer exists in its original
location?
5. (No) When we talk about moving, loading, transfer¬
ring, or storing data, we are actually_the
data.
6. (copying) If you can type mnemonics into your com¬
puter or trainer, it must have an_
7. (assembler) What do microprocessors understand?
8. (binary numbers) An assembler translates mnemonics
into_
(binary numbers)
PROBLEMS
General
16-1. What does the NOP (no operation) instruction
do?
16-2. What are two purposes of the NOP instruction?
16-3. If you move, load, or transfer the contents of the
accumulator to a general-purpose register, what
is left in the accumulator?
6502 Family
16-4. What is the op code for the NOP instruction?
16-5. What is the op code for the BReaK instruction?
16-6. What is the op code for the TAX (Transfer
Accumulator to X register) instruction?
16-7. What does the TYA instruction do?
16-8. What does the mnemonic STX stand for?
16-9. Which instruction would you use to copy the
contents of the Y register into a memory loca¬
tion?
16-10. Write a program which will
a. Place the number 45 ]6 in the accumulator.
b. Transfer the contents of the accumulator to
the X register.
c. Stop.
6800/6808 Family
16-11. What is the op code for the NOP instruction?
16-12. What is the op code for the WAI instruction?
16-13. What is the op code for the TAB (Transfer
accumulator A to accumulator B) instruction?
16-14. What does the TBA instruction do?
16-15. What does the mnemonic CLRA stand for?
16-16. Which instruction would you use to copy the
contents of accumulator B into a memory loca¬
tion?
16-17. Write a program which will
a. Place the number 89 I6 in accumulator B.
b. Copy the contents of accumulator B to accu¬
mulator A.
c. Stop.
8080/8085/Z80 Family
16-18. What is the op code for the NOP instruction?
16-19. What is the op code for the HALT instruction?
16-20. What is the op code for the Mov A,D [LD A,D]
instruction?
16-21. What does the MOV B,C [LD B,C] instruction
do?
16-22. What does the mnemonic MVI A,dd [LD A,dd]
stand for?
16-23. Which instruction would you use to store the
contents of the accumulator in a memory loca¬
tion?
16-24. Write a program which will
a. Place the number 78 16 immediately into the
accumulator.
b. Copy the contents of the accumulator into
register C.
c. Stop.
8086/8088 Family
16-25. What is the DOS utility which we are using in
this text to do assembly, disassembly, running,
and debugging of 8086/8088 assembly-language
programs?
16-26. What three areas can serve as a source for the
8088 MOVe instruction?
Chapter 16 Data Transfer Instructions 261
16-27. What are the two areas which can serve as desti¬
nations for the 8088 MOV instruction?
16-28. Which area cannot be both a source and a desti¬
nation at the same time?
16-29. What is the source of a MOV AL,DL instruc¬
tion?
16-30. What is the destination of a MOV AL,76
instruction?
16-31. Does the instruction MOV B,[4456] move the
number 4456 or the contents of memory location
4456 16 to register B?
16-32. What does the DEBUG command “r” stand for
and what does it do?
16-33. What does the DEBUG command “a” stand for
and what does it do?
16-34. What does the DEBUG command “u” stand for
and what does it do?
16-35. What does the DEBUG trace command do?
16-36. What is the DEBUG quit command?
16-37. Using DEBUG, write an 8086/8088 assembly
program which will
a. Place the number 89 16 into the register BL.
b. Copy the contents of BL into CL.
{Note: Use DEBUG’s trace command to ex¬
ecute the program to see if it works.)
262
Digital Computer Electronics
Addressing Modes—I
New Concepts _
In this chapter we will study the simplest of the different
addressing modes. This will provide a foundation for the
next couple of chapters. In a later chapter we will look at
the more complex addressing modes. First we need to learn
what an addressing mode is.
17-1 WHAT IS AN ADDRESSING
MODE?
In an earlier chapter we used the system of addressing
homes as a way to describe memory addressing. Let’s use
the same idea to describe addressing modes.
If you are moving and want to describe to the movers
how to get to your new home so that they can deliver your
belongings, you would give them the name of the state,
city, street, and house number.
But what if you were moving to an apartment in Canada?
In that case you would give them the name of the country,
province, city, street, apartment complex, and apartment
number.
Or what if you were moving to a backwoods cabin for a
summer in the wilderness? You would give them the name
of the state, county, county road, the direction and number
of miles to travel on that county road, and finally landmarks
to help them find the cabin. (OK, you probably won’t have
a truck moving all of your belongings to a wilderness cabin,
but the analogy worked well up to that point.)
You can see that we need more than one way to ‘ ‘address”
or describe a location because not every method works in
every circumstance. This is what addressing modes are
about.
How you describe a location you want to transfer a
number to can depend on several factors. Remember that
while the addressing mode which should be used is very
apparent in some cases, in other cases choosing the best
addressing mode requires skill that must be developed over
time.
17-2 THE PAGING CONCEPT
Before we go any further into the subject of addressing
modes, we need to look at the concept of paging. Paging
is the concept of dividing memory into blocks of 256 bytes
each. Each block is called a page . We have to look at how
we count in hexadecimal to see why this number was
chosen.
The number 256 was chosen because that is how far you
can count using only two hex digits. Actually, FF, which
is the highest two-digit hex number, is 255 (decimal), but
if you count 00, you have 256 different numbers, or in this
case, memory locations.
Counting from 00 16 to FF 16 using four hex digits looks
like this:
0000
0001
0002
00FE
00FF
Notice that the left two digits are always 0. The range of
hex numbers from 00 to FF is called page 00 (sometimes
called the zero page).
The next number after 00FF is 0100. Let’s continue
counting from there:
0100
0101
0102
01FE
01FF
Notice that the left two digits are 01. This is called page
one.
263
The next number in the sequence is 0200. This is the
beginning of page two. Page two ends with CUFF, after
which comes 0300, the beginning of page three.
This process continues up to FFFF 16 . There are 256 of
these pages, with 256 bytes per page.
The addressing modes of the 8085 do not reference page
numbers; however, the 6800/6808 and 6502 do have
addressing modes that depend upon the concept of paging.
17-3 BASIC ADDRESSING MODES
We are now going to study the four most basic addressing
modes. As you read about each mode, first and foremost
try to understand the concept. The actual name of the
addressing mode may be different for the microprocessor
which you are using. After you read about these four modes,
go to the section which covers your particular micropro¬
cessor for specific details.
Implied Addressing
In implied addressing , sometimes called inherent address¬
ing , no address is necessary because the location is implied
in the instruction itself. It is the simplest of all addressing
modes. You used this mode in Chap. 16, which discussed
the CPU control instructions. Remember the NOP (no
operation) instruction? Do we have to tell it where to do
nothing? No. No addressing is necessary.
Another example would be the case of a microprocessor
which has only one accumulator and a certain index register.
The 6502, for example, has an instruction called
TAX
which means
Transfer Accumulator to X register
There is only one accumulator, and the specified register
is the X register. The microprocessor knows exactly where
the accumulator and the X register are, so we say that the
address is implied in the instruction itself. The data will be
transferred from the accumulator to the X register.
Register (Accumulator) Addressing
Register addressing , sometimes called accumulator ad¬
dressing, involves only internal registers or an accumula¬
tors) and no external RAM. For example, the 8085
microprocessor has an instruction called
MOV A,B
which means
MOVe data to A from B
Since the data is being moved from one register to another,
no other address information is needed. The names of the
registers are enough.
It should be noted that with some microprocessors it is
not clear whether this is considered to be a separate
addressing mode or a special subtype of the implied ad¬
dressing mode. See your particular microprocessor section
for details.
Immediate Addressing
Immediate addressing is a mode in which the number or
data to be operated on or moved is in the memory location
immediately following the instruction op code. For example,
the 6800/6808 microprocessor has an instruction called
LDAA #$dd
which means
LoaD Accumulator A with the two hexadecimal ($)
digits of data (dd) immediately (#) following this
op code
In the computer’s memory there will be the hex number
86, which is the op code for the LDAA immediate instruc¬
tion, followed immediately by the two hex digits which we
have called dd (since we don’t know what their actual value
is right now).
Direct Addressing
Direct addressing uses an op code followed by a 1- or
2-byte memory address where the data which is to be used
can be found. The data is outside of the microprocessor
itself, in one of the many thousands of memory locations.
The Z80 has an instruction called
LD A, (aaaa)
which means
LoaD the Accumulator with the data found at memory
location (aaaa)
Here of course the aaaa is four hex digits, which makes a
16-bit address. The microprocessor will go to memory
address aaaa and place a copy of the contents of that address
in the accumulator.
Keep in mind that some microprocessors do not call this
“direct” addressing and that some have more than one
form of this addressing mode.
264 Digital Computer Electronics
Specific Microprocessor
Families
Go to the section which discusses the microprocessor you
are using.
hexadecimal (not decimal). The dd stands for two hex digits
such as 35 or E2. To load the accumulator with the hex
number E2, you would type
LDA #$E2
17-4 6502 FAMILY
The 6502 uses the implied and immediate modes as described
in the New Concepts section of this chapter. The register
mode and direct mode are a little different.
Implied Addressing
For an example of implied addressing refer to the Data
Transfer Instructions part of the 6502 instruction set in the
Expanded Table of 6502 Instructions Listed by Category.
Find the TAX instruction, which is an example of implied
addressing as noted in the Address Mode column. Notice
that it Transfers the contents of the Accumulator to the X
register as indicated in the Operation and Boolean/Arith¬
metic Operation columns. Of course, no other information
is needed since both of these locations are inside the
microprocessor itself.
Direct Addressing
The 6502 has two different types of direct addressing. One
is called zero page addressing, and the other absolute
addressing.
Zero page addressing is direct addressing in which the
target address is in page zero of memory, somewhere in
the first 256 bytes of memory, between 0000 16 and 00FF, 6 .
Since the first two hex digits of any address in zero page
are 00s, the 00s can be omitted, making it possible to
describe the address with only 1 byte.
Absolute addressing is a form of direct addressing in
which the target address can be anywhere from 0000 16 to
FFFF 16 . This requires four hex digits, which is a 2-byte
address.
Referring again to the LDA instruction, the third form
down is the zero page addressing form of the instruction.
Notice that the assembler notation form appears as
LDA $aa
Register (Accumulator) Addressing
The 6502 doesn’t use register addressing as a dominant
addressing mode like the 8080/8085 does. It does use it in
four instances, however, and calls it accumulator address¬
ing.
For example, the 6502 instruction
The two lowercase a’s indicate a two-digit hex address.
The second form of the LDA instruction is the absolute
addressing form. The assembler notation in this case ap¬
pears as
LDA $aaaa
ASL
which stands for Arithmetic Shift Left, shifts every bit in
the accumulator to the left one place. The operand is in the
accumulator.
There are only four 6502 instructions which use the
register or accumulator addressing mode: they are ASL A
(Arithmetic Shift Left Accumulator), LSR A (Logical Shift
Right Accumulator), ROL A (ROtate Left Accumulator),
and ROR A (ROtate Right Accumulator). All these instruc¬
tions can be found in the Rotate and Shift Instructions
section of the Expanded Table of 6502 Instructions Listed
by Category.
which means that the address consists of four hex digits (2
bytes).
{Note: The 6502 microprocessor expresses addresses in
reverse low-byte/high-byte order!)
6502 Summary
Some examples are
NOP
ASL
LDA #$35
LDA $ IE
LDAS123D
Implied addressing
Register (accumulator) addressing
Immediate addressing
<— Direct (zero page) addressing
Direct (absolute) addressing
Immediate Addressing
Now let’s look at an example of immediate addressing. In
the Data Transfer section of the 6502 instruction set, notice
the first form of the LDA instruction. It uses immediate
addressing, which is what the # in the Assembler Notation
column stands for. The $ means that the number is
17-5 6800/6808 FAMILY
The 6800/6808 uses the implied and immediate modes as
described in the New Concepts section. The register and
direct modes are a little different.
Chapter 1 7 Addressing Modes — I 265
Implied Addressing
For an example of implied addressing, refer to the Data
Transfer Instructions part of the Expanded Table of 6800
Instructions Listed by Category.
Find the TAB instruction, which is an example of implied
addressing as noted in the Address Mode column. Notice
that it transfers the contents of accumulator A to accumulator
B as indicated in the Operation and Boolean/Arithmetic
Operation columns. No other information is needed since
both of these locations are inside of the microprocessor
itself.
which means there are only two hex address digits, indicated
by aa (a stands for address). The fourth LDAA form is the
extended addressing form of the instruction. The assembler
notation in this case appears as
LDAA $aaaa
which means that there are four hex address digits (2 bytes).
6800/6808 Summary
Some examples are
Register (Accumulator) Addressing
The 6800/6808 doesn’t use register addressing as a dominant
addressing mode the way the 8080/8085 does. Technically,
it does use it, however, and calls it accumulator addressing.
Since it is often considered a special form of implied
addressing by many who use the 6800/6808, it has not been
included in the Address Mode column of the instruction
sheets but rather falls under the title of Implied addressing.
TAB
TAB
LDAA #$35
LDAA $ IE
LDAA $123D
<— Implied addressing
<r- Register (accumulator) addressing
<— Immediate addressing
<— Direct addressing
Direct (extended) addressing
17-6 8080/8085/Z80 FAMILY
Immediate Addressing
Now let’s look at an example of immediate addressing. In
the Data Transfer section of the 6800/6808 instruction set
notice the first form of the LDAA instruction. It uses
immediate addressing, which is what the # in the Assembler
Notation column stands for. The $ means that the number
is hexadecimal (not decimal). The dd stands for two hex
digits such as E2. The instruction which would LoaD
accumulator A with the value E2 would appear as
LDAA #$E2
Direct Addressing
The 6800/6808 has two different types of direct addressing.
One is called direct addressing, and the other extended
addressing.
Direct addressing is a form of direct addressing in which
the target address is in page zero of memory—that is,
somewhere in the first 256 bytes of memory between 0000, 6
and 00FF, 6 . Since the first two hex digits of any address
in this range are 00, the 00s can be omitted, making it
possible to designate the address with only 1 byte.
Extended addressing is a form of direct addressing in
which the target address can be anywhere from 0000 16 to
FFFF 16 . This requires four hex digits, which is a 2-byte
address.
Referring to the LDAA instruction, notice that the second
form down is the direct addressing form of the instruction.
The assembler notation appears as
LDAA $aa
The 8080/8085/Z80 uses the implied, immediate, register,
and direct addressing modes as described in the New
Concepts section of this chapter.
Note that the Z80 has all of the addressing modes that
the 8080/8085 has, plus a number of addressing modes that
the 8080/8085 does not have. We do not include these
additional modes of the Z80 in either the text or the
instruction set tables in this book. Refer to one of the many
books available about the Z80 to learn about these other
modes.
We need to bring your attention to a sometimes confusing
fact about the 8080/8085/Z80 mnemonics. Look at the Data
Transfer Instructions section of the Expanded Table of
8080/8085/Z80 (8080 subset) Instructions Listed by Cate¬
gory. Now look at the MOV A,B [Z80 = LD A,B]
instruction (the second instruction in this section). Notice
in the Boolean/Arithmetic Operation column that the data
is moving from B toward A. This means that the mnemonic
places the destination register before the source register.
This is true of the entire 8080/8085/Z80 instruction set.
The MOV A,B instruction is moving data to A from B.
(Note: The 6502 and 6800/6808 are just the reverse.)
Implied Addressing
An example of implied addressing can be seen in the CPU
Control Instructions section of the 8080/8085/Z80 instruc¬
tion set. The NOP instruction uses implied addressing since
no address is necessary. In the Flag Instructions section
you can see another example. The STC (SeT Carry flag)
instruction uses implied addressing. The carry flag is inside
the 8080/8085/Z80 microprocessor. Therefore no other
address information is needed.
266 Digital Computer Electronics
Register (Accumulator) Addressing
This form of addressing is called register addressing with
the 8080/8085 (in contrast to the term accumulator ad¬
dressing used by the 6502 and 6808). The 8080/8085/Z80
uses this form of addressing very frequently. In fact, if you
browse through the Data Transfer Instructions section of
the Expanded Table of 8085/8080 and Z80 (8080 Subset)
Instructions Listed by Category, you will find that most of
these instructions use this form of addressing.
For example, the instruction MOV A,B [Z80 = LD A,BJ
moves or makes a copy of the data in the B register and
places it in the A register. (We normally call this the
accumulator.) Since external memory is not utilized, and
both the source of the data and its destination are inside
the microprocessor, this information is sufficient.
Immediate Addressing
The 8080/8085/Z80 microprocessors use the immediate
mode as described in the New Concepts section at the
beginning of the chapter.
To see an example of this mode, scan through the 8080/
8085/Z80 instruction set in the Data Transfer Section until
you come to the MVI A,dd [Z80 = LD A } dd] instruction
(the 64th instruction in that section). You’ll notice in the
Address Mode column that this is labeled as using the
immediate addressing mode. This means that the op code
for this instruction (3E) would be followed immediately by
the two hex digits we want moved.
If the Hex number C8 was the value we wanted to load
into the accumulator, the 8080/8085 assembly-language
notation would appear as
MVI A,C8 [LD A,C8]
The second instruction, in brackets and in italics, is the
Z80 form.
Direct Addressing
The direct addressing mode as implemented in the 8080/
8085/Z80 microprocessors works as described in the New
Concepts section of this chapter.
The 8080/8085/Z80 has only one form of direct address¬
ing. (The 6502 and the 6800/6808 have two forms of this
addressing mode.)
To find an example of this mode, scan through the Data
Transfer Instructions section of the 8080/8085/Z80 instruc¬
tion set until you find the LDA aaaa [LD A,(aaaa)[
instruction (the 78th instruction in this section). The op
code for this instruction is 3A. It uses 3 bytes of memory.
The 1st byte will be the op code, 3A. The 2d and 3d bytes
will be the address of the memory location where the data
can be found.
{Note: The 8080/8085/Z80 microprocessors express ad¬
dresses in reverse low-byte/high-byte order!) If we wanted
to load the accumulator from memory location 1234, the 3
bytes of object code would be
3A 34 12
in the op code/high-byte/low-byte sequence.
The assembly-language notation for this instruction would
appear as
LDA 1234 [LD A, (1234)]
8080/8085/Z80 Summary
Some examples are
NOP <— Implied addressing
MOV A,B [LD A,B] Register addressing
MVI A,C8 [LDA,C8] <— Immediate addressing
LDA 1234 [LD A, (1234)] <— Direct addressing
17-7 8086/8088 FAMILY
Most of the 8086/8088 instructions are implemented as
described in the New Concepts section of this chapter.
We need to bring to your attention a sometimes confusing
fact about 8086/8088 mnemonics. The 8086/8088 mne¬
monics place the destination register before the source
register. This is true of the entire 8086/8088 instruction set.
The MOV AL,BL instruction is moving data to AL from
BL. (Note: This is similar to the 8080/8085/Z80 micropro¬
cessors.)
Implied Addressing
Implied addressing works on the 8086/8088 microprocessors
as described in the New Concepts section of this chapter.
Two examples are HLT (halt) and NOP (no operation).
Register Addressing
Register addressing also works as described in the New
Concepts section of this chapter. Since the 8086/8088 chips
have eight 8-bit (or four 16-bit) general-purpose registers
in addition to a number of other special-purpose registers,
there are hundreds of move combinations. Let’s look at
one of them.
The instruction which moves the contents of the CX
register into the BX register looks like this:
MOV BX,CX
Again you should notice that where the data is going to
(BX) is written first, and where the data is coming from
(CX) is written last.
Chapter 17 Addressing Modes — I 267
Since only registers are involved, all of which are inside
the microprocessor, no other information is needed by the
microprocessor.
Immediate Addressing
Immediate addressing on the 8086/8088 is as described in
the New Concepts section of this chapter. For example, the
instruction MOV AL,37 would place the hexadecimal
number 37 in the AL register.
Memory Segmentation
Before we can discuss direct addressing, we need to look
at a feature of the 8086/8088 microprocessors which does
not exist in any of the 8-bit microprocessors used in this
book. That feature is memory segmentation.
Earlier in this chapter we discussed the paging concept.
Segmentation is an extension of that concept. The 8-bit
microprocessors use 16-bit addresses. That gives them a
range from 0000, 6 to FFFF 16 . In decimal that is 65,535,
which gives us a total of 65,536 different memory locations
counting location 0000 16 . Another way to express this is as
64 kilobytes, or 64K. Notice that the addresses from 0000 16
to FFFF 16 use four hex digits. The two right-most digits
express which byte is being referred to. The two left-most
digits express which page the bytes are in. There are 256
bytes per page and 256 pages from 0000 16 to FFFF 16 .
The 8086/8088 chips use a larger 20-bit address instead
of the 16-bit address used by the 8-bit chips. Twenty bits
is five hexadecimal digits. This provides a range from
00000 ]6 to FFFFF 16 . In decimal this is 1,048,575, which
gives us 1,048,576 memory locations (since we can count
00000 16 ), or 1 megabyte of memory.
A segment is a 64K block of memory; thus there could
be as many as 16 nonoverlapping segments in 1M (mega¬
byte) of memory. Unlike a memory page, however, a
segment is not bound to a certain location. The only
requirement is that a segment must start on a 16-byte
memory boundary. Segments can be nonoverlapping, they
can partially overlap, or they can be superimposed with
one exactly on top of the other. The 8086/8088 has four
segment registers and so can manage four different segments
at a time.
Direct addressing uses not only the address specified in
the instruction but also the address in one of the segment
registers. In the case of move instructions, the data segment
register is used. The process involves adding the address
you have specified to the address in the data segment register
after shifting the data segment register to the left one
hexadecimal digit. For example, if you said
MOV DL,[0100]
and if the data segment register contained 2000, the address
would be calculated in the following manner.
2000 data segment register (shifted left)
T 0100 address
20100 effective address
Notice that the contents of the data segment register have
been shifted to the left one place. (You can think of it as
adding a 0 to the right side of the data segment register.)
So the MOV DL,[0100] instruction places a copy of the
data found at memory location 20100 I6 (not location 0100 16 )
in the DL register.
We generally won't be concerned with segment registers
in this text since our programs are simple and very small.
All the segment registers will be the same, so the offset
(the address of the instruction pointer) will be all we must
pay attention to.
Direct Addressing
Except for memory segmentation, direct addressing on the
8086/8088 is quite like that used on the 8-bit chips. When
we use the term direct addressing in reference to the 8086/
8088, we are referring to the direct form of addressing used
when manipulating data. (See the following topic, Program
Direct Addressing, for the other use of direct addressing.)
For example, if the data segment register contains the
number 0723, and the instruction
MOV BE,[0100]
is encountered, the contents of memory location 07330, 6
(07230 + 0100 = 07330) would be copied into the BL
register.
Program Direct Addressing
Program direct addressing is no different from direct
addressing: It is simply direct addressing used for a different
purpose.
Program direct addressing is used with JMP and CALL
instructions. These instructions direct the “flow” of the
program. They are not used to manipulate data. Which
instruction or subroutine is to be executed next can be
altered with the JMP and CALL instructions.
For example, the instruction
JMP 100
tells the microprocessor to execute the instruction found at
location 0100 (hex) in the program segment. This is an
example of program direct addressing.
The offset (100 in the above example) is added to the
code segment register rather than the data segment register.
Remember that the contents of the code segment register,
like the data segment register, are shifted one hexadecimal
place to the left before being added to the offset.
268 Digital Computer Electronics
8086/8088 Summary
Some examples are
NOP <— Implied addressing
MOV BX,CX <— Register addressing
MOV AL,37
MOV BL,[0100]
JMP 100
Immediate addressing
Direct addressing
<— Direct (program direct) addressing
Chapter 17 Addressing Modes —I
269
Arithmetic and Flags
In this chapter we will study the arithmetic instructions of
each of our microprocessor families. We will also look at
the closely related topic of flags, at how they react to
arithmetic instructions, and at the instructions which control
them.
New Concepts _
There are several main topics in this chapter. We will learn
about (and review) the number systems microprocessors
use. We will study addition and subtraction (as well as
multiplication and division on the 16-bit 8086/8088). And
finally we will study the flags which are affected by these
arithmetic operations and how to alter the condition of those
flags.
18-1 MICROPROCESSORS AND
NUMBERS
We must first look at the kind of numbers a microprocessor
performs arithmetic operations on. You have already studied
much of this in earlier chapters.
Binary and Hexadecimal Numbers
We introduced binary numbers in Chap. 1. If that was the
first time you had ever seen numbers in another base system,
the whole subject may have been a bit confusing. It all
becomes quite natural, though, with time and experience.
At this point there are a couple of very important skills
which you must have. You should be able to look at an 8-
0000 0000
Fig. 18-1 Decimal values of each bit of an 8-bit binary
number.
bit binary number and know the decimal value of each of
the bit’s positions. This is illustrated in Fig. 18-1.
You should also be able to add the decimal values of
each binary digit to determine the decimal value of the
complete binary number. See Chap. 1 if you have forgotten
how to do this.
Another skill which was stressed in Chap. 1 is now
necessary if you are to work with microprocessors effec¬
tively. This is the ability to recognize any 4-bit binary
number, its hexadecimal equivalent, and its decimal equiv¬
alent. The table which illustrates this appeared in Chap. 1
as Table 1-4 and is repeated here as Fig. 18-2.
If you are unsure about any of these concepts, review
Chap. 1.
Binary-Coded Decimal Numbers
Binary-coded decimal numbers are just that: They are
decimal numbers that happen to have each digit represented
by its 4-bit binary equivalent. For example
0100 2 = 4 10 and 0001 2 = 1 1 0
Hexadecimal
Binary
Decimal
0
0000
0
1
0001
1
2
0010
2
3
0011
3
4
0100
4
5
0101
5
6
0110
6
7
0111
7
8
1000
8
9
1001
9
A
1010
10
B
1011
11
C
1100
12
D
1101
13
E
1110
14
F
1111
15
Fig. 18-2 Hexadecimal-binary-decimal conversion chart.
270
Therefore the BCD (Binary Coded Decimal) equivalent of
the decimal number 41 is
0100 0001
Each nibble (group of 4 bits) stands for one decimal digit.
The number as a whole is still a decimal number, however.
ASCII
ASCII code is different from decimal, binary, hexadecimal,
and BCD in that it is not a number system but rather a way
to represent various symbols with different patterns of Is
and 0s. Each pattern of Is and 0s stands for a different
letter of the alphabet (uppercase or lowercase), digit,
punctuation mark, or other useful character.
We use number systems to count and to perform math¬
ematical computations. We don’t use ASCII for these
purposes. We use ASCII code to represent characters used
in normal written communication.
Do not try to memorize the ASCII code. Using charts
when needed will suffice. If a large amount of data is
necessary, we usually have some device, primarily the
standard computer keyboard, to create these ASCII char¬
acters. A table (Table 1-6) showing the ASCII code appears
in Chap. 1.
Microprocessors and Number Conversions
Microprocessors “think” in binary numbers. They use
binary numbers for calculations and logical operations.
Since binary numbers can be displayed as hexadecimal
numbers with fewer digits, we often display binary numbers
as their hexadecimal equivalents when people must enter
or interpret those numbers.
The BCD numbers are used in certain situations to aid
the people who must read them. For this reason some
microprocessors have instructions which can convert an¬
swers resulting from binary mathematical operations to
binary-coded decimal numbers. We will look at these
operations later in this chapter.
Bit Positions
Sometimes students are confused when people talk about a
certain “bit.” There are two ways to describe a particular
bit: by the binary power of 2 reflected in its position and
by its location, from right to left. Look at Fig. 18-3.
You will see both methods used in the workplace and in
other textbooks, so you should become comfortable with
each.
18-2 ARITHMETIC INSTRUCTIONS
We will now review basic binary math and look at typical
microprocessor instructions which perform mathematical
0000 0000
2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 °
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0000 0000
8th bit 7th bit 6th bit 5th bit 4th bit 3d bit 2d bit 1st bit
Fig. 18-3 Two methods for describing bit positions.
computations. Remember that we are now discussing tech¬
niques and instructions which are common to most micro¬
processors. We will study instructions specific to each
microprocessor family in its appropriate section later in this
chapter.
Addition
Each microprocessor family included in this text has at
least one addition instruction. Most have more than one.
When adding binary numbers the microprocessor pro¬
duces two types of information: (1) the sum of the two
numbers (answer), (2) and information indicating whether
there were carries in certain columns.
If you don’t remember how to add binary numbers, you
may want to review Chap. 6 now. There are really only
five binary addition combinations to remember:
(1)
(2)
(3)
(4)
(5)
0
0
1
1
1
+ 0
+ 1
+ 0
+ 1
1
0
1
1
10
+ 1
11
The first three combinations produce the same answer as
they do in the decimal number base system. Combination
#4 is simply saying that 1 + 1=2, except that the 2 is
binary (10 2 = 2 10 ). You should say combination #4 to
yourself as, “1 plus 1 equals 0, carry 1.” Likewise, the
fifth combination is saying that 1 + 1 + 1 = 3, except
that the 3 is binary (1 I 2 “ 3 10 ). You should express
combination #5 as, “1 plus 1 plus 1 equals 1, carry 1.”
The last two combinations are the only new ones that you
should memorize, since they are the only two that are
different from our decimal number system.
To continue our review, let’s see how to add several
columns. It is common (and very practical) to show 8-bit
binary numbers in two groups of four (as 2 nibbles). Refer
to Fig. 18-4.
As you study Fig. 18-4, you will see that each of the
Chapter 18 Arithmetic and Flags 271
-Half-carry flag
i 11 i
1 0 0 1 1 1 0 1 157 10
+ 110 1 10 0 1 + 217 10
1 0 1 1 1 0 1 1 0 374 10
- Carry flag (9th bit)
Fig. 18-4 Multi-column addition.
individual additions in each column is one of the five
combinations we presented a moment ago.
Now let’s continue using this example as we talk about
two other closely related subtopics.
Carry Flag
The first flag we’ll study is the carry flag. The carry flag,
during addition, lets us know that the 8-bit sum is not the
complete answer. If the carry flag is set (has a value of 1),
it indicates that a 9th bit was produced.
Let’s look again at Fig. 18-4. Notice the sum shown in
the decimal version of the example. The decimal answer is
374. Now look at the binary version of the example. If you
were to use only the right-most 8 bits (the 8 least significant
bits), the sum would appear to be 118 l0 (0111 0110 2 =
118 10 ), which is not the correct sum. The 9th bit, which
appears at the far left (the most significant bit), would not
appear in an 8-bit accumulator. The 9th bit would exist in
the carry flag (so to speak). The 1 in the carry flag would
indicate a carry from column 8 to column 9. Again, we
cannot see a 9th bit since the accumulator only holds 8
bits. (If you are using a 16-bit microprocessor, the function
of the carry flag is the same as that described above except
that it indicates the presence of a 17th bit, which will not
fit into a 16-bit accumulator.
Substraction also affects the carry flag. We will discuss
that a little later in this chapter.
Half-Carry Flag
Some (but not all) of our microprocessors have a half-carry
flag. A half-carry flag indicates that a carry has occurred
from the 4th-bit column to the 5th-bit column. The half¬
carry has been marked in Fig. 18-4.
Overflow Flag
The overflow flag alerts the programmer to a condition that
is similar to, but not the same as, that to which the carry
flag alerts the programmer. All our featured microprocessor
families have an overflow flag except the 8080/8085. To
understand what the overflow flag does, we need to take a
closer look at 2’s-complement arithmetic and signed binary
numbers.
Each of our microprocessor families has one or more
99,999 00,000
(a) ( b)
Fig. 18-5 (a) Automobile odometer. ( b ) Automobile
odometer reset.
accumulators. All are 8-bit accumulators except the 8086/
8088, which has a 16-bit accumulator. Let’s focus our
discussion on the 8-bit microprocessors.
If we do not expect to ever need negative numbers in a
particular application, we can let the binary range of 0000
0000 to 1111 1111 represent decimal numbers 0 to 255.
These are called unsigned binary numbers. However, if we
need to represent negative numbers, we must use the 2’s-
complement form of the numbers we wish to make negative.
When we allow both positive and negative numbers, we
are using signed binary numbers.
We introduced 2’s-complement numbers in Chap. 6. The
concept was compared to that of the odometer on a car.
Remember that the accumulator, like the odometer of a
car, can contain only a certain number of digits. Most cars
display 5 digits plus lOths of a mile. If we disregard the
lOths digit, we have just 5 places. Of course, the highest
number which can be represented is 99,999 miles. There
aren’t enough digits to show 100,000 miles. The 1 is lost,
and only the 00,000 remains. The odometer has reset.
Figure 18-5 illustrates this.
The accumulator of a microprocessor has this same
limitation. If you continuously increment an 8-bit accu¬
mulator, you will eventually reach a maximum number
beyond which the accumulator would have to have another
digit. Figure 18-6 illustrates this. The accumulator, like the
odometer, will reset to zero if it is incremented one more
time.
When working with 2’s-complement binary numbers, we
assume that the accumulator can also be rolled backward,
so to speak, to represent negative numbers. One less than
zero is 11111111 ? » which would be equal to —1 10 . One
less than that would be 11111110 2 , which would be equal
to — 2 10 . This process would continue as shown in Fig.
18-7.
As Fig. 18-7 illustrates, -128 10 is as far as we can go
11111111
Fig. 18-6 Eight-bit accumulator.
272 Digital Computer Electronics
Therefore
0 1111111 +127
0 0 0 0 0 0 1 1 +3
00000010 +2
00000001 +1
00000000 0
11111111 -1
11111110 -2
1111110 1 -3
1 0 0 0 0 0 0 0 -128
Fig. 18-7 Eight-bit 2’s-complement range.
on the negative end. The reason for this is that one less
than 10000000 2 is 01111111 2 , which, if you look at the top
of Fig. 18-7, is already being used as the equivalent of
+ 127 10 . When working with 8-bit 2’s-complement num¬
bers, we regard all numbers which have a 1 as the MSB
(most significant bit) as negative. Numbers with a 0 in the
MSB are positive. This means that the range for 8-bit 2’s-
complement binary numbers is + 127 10 to - 128 10 inclusive.
Let’s review a little. If we are using all 8 bits to represent
numbers from 00 10 to 255 10 , we refer to these numbers as
unsigned binary numbers. If we are using the MSB to
signify whether a number is positive or negative, we have
a range of —128 10 to +127, 0 . These are called signed
binary numbers.
There is a simple procedure by which you can determine
how to form a negative binary (or hexadecimal) number.
First, write the binary equivalent of the positive form of
the number. For example
10 10 = 0000 1010 2 = 0A 16
Now invert each bit of the binary number.
0000 1010 becomes 1111 0101
Then add 1.
1111 0101
+_1
mi ono
-io 10 = mi ono 2 = F6 16
Notice that the MSB of the binary number is 1, as we said
it would be.
To determine what value a negative-signed binary number
represents, reverse the above process. If you had the binary
number
1111 0110 (the number created a moment ago)
invert each bit
0000 1001
and then add 1.
0000 1001
+_1
0000 1010
Notice that we now have the binary number for 10 lo . (A
small 1 indicates a carry.) We have found that the binary
number 1111 0110 is the signed binary number for — 10 lo .
The question now is how to interpret certain numbers.
For example,
125,0
0111
1101 2
125,o
+ 50 10
+ 0011
0010 2
+
©
©
175,0
1010
1111 2
81 io
We know that 125, 0
+ 50 10
II
--j
L/l
9
As you will notice
in this example, however, the binary number for 175 10
(which is 1010 1111 2 ) is also the binary number for — 81 10 .
So if we didn’t know what two numbers this was the sum
of, how would we know how to interpret this answer? If
we simply found the binary number 1010 1111 2 in a register,
how would we know if it was meant to be + 175, 0 or
— 81 10 ? The answer is that we wouldn’t. (The number
— 81 10 is, of course, the wrong answer. We will deal with
that part of the problem in just a bit.) We must know
whether we are using unsigned binary numbers or signed
binary numbers before we see the answer. It is simply a
matter of agreement beforehand.
We have been preparing to explain the purpose of the
overflow flag. We are now ready. The previous example,
which produced a sum of + 175, 0 (1010 1111 2 ) ? would
have set the overflow flag in an 8-bit microprocessor. The
overflow flag tells the programmer that the last answer
produced was outside the range of + 127 10 to - 128 10 (0111
1111 2 to 1000 0000 2 or 7F 16 to 80, 6 ). If the programmer
understood this answer to represent an unsigned binary
number, he or she would ignore the flag. If, however, this
Chapter 18 Arithmetic and Flags 273
was intended to be a signed binary number, the programmer
would know that this answer, if taken as a signed binary
number, is incorrect because it has exceeded the range for
8-bit signed binary numbers.
The range for unsigned 16-bit binary numbers is O 10
(0000 0000 0000 0000 2 or 0000 16 ) to 65,535 10 (Hll mi
1111 1111 2 or FFFF l6 ). The range for signed 16-bit binary
numbers is + 32,767 10 (0111 1111 1111 1111 2 or 7FFF 16 )
to — 32,768 10 (1000 0000 0000 0000 2 or 8000 16 ).
you its decimal value. For example, to calculate the value
of the binary number
0100 0001 0000 0010
you would enter
2 14 + 2 8 + 2 1 = 16,642 10
into your calculator to get the above answer.
Addition-with-Carry
The previous section on addition discussed the carry flag.
The carry flag signals the programmer that the result of an
operation has exceeded 8 bits.
The carry flag has another use, though. The carry from
the 8th bit to the 9th bit (which is what the carry represents)
can be used during multiple-precision arithmetic. We use
multiple-precision arithmetic when the accumulator cannot
accept numbers large enough for the desired operation.
Multiple-Precision Binary Numbers
Until now we have assumed that any numbers we want to
add would occupy only 1 byte of memory. This is called a
single-precision number. One-byte unsigned numbers can
range from 0 to 255. Two-byte unsigned numbers can range
from 0 to 65,535. These are called double-precision binary
numbers. Three-byte unsigned binary numbers can range
from 0 to 16,777,215. These are called triple-precision
numbers.
When we construct a double-precision number, we use
the same techniques to determine its value as when we
work with a single-precision number. Recall from earlier
chapters that each binary position has a value and that each
value is twice as large as the value to its right. If you have
a calculator which will calculate powers of a number, it is
quite easy to determine the value of a double-precision
binary number. Refer to Fig. 18-8.
You see that the least significant bit (LSB) has a value
of 2°. This is equal to the number 1. (If you try this on a
scientific calculator, it should give you that answer.) To
determine the value of a double-precision number, add the
value of each position which has a 1 in it. This will give
0000 0000 0000 0000
Fig. 18-8 Powers of 2 for a double-precision binary
number.
Add-with-Carry
Let’s step through a double-precision addition problem.
Remember that we will be using the carry flag. Figure
18-9 shows an example.
The least significant bytes (LSBs) are on the right. They
occupy the positions which have the least value. The most
significant bytes are on the left. They occupy the positions
which have the most value.
As you can see, several carries occur in this example.
We are interested in the carry from the LSB to the MSB.
That carry would actually be held in the carry flag of the
microprocessor.
A typical microprocessor program to add these two binary
numbers (using English phrases instead of microprocessor
instructions) would appear as follows:
CLEAR CARRY FLAG
LOAD ACCUMULATOR WITH LSB OF ADDEND
ADD THE LSB OF THE AUGEND TO THE
ACCUMULATOR
STORE THE LSB OF THE SUM IN MEMORY
LOAD THE ACCUMULATOR WITH THE MSB
OF THE ADDEND
ADD-WITH-CARRY THE MSB OF THE AUGEND
TO THE ACCUMULATOR
STORE THE MSB OF THE SUM IN MEMORY
Notice that we simply add the LSB of each number, but
we add-with-carry the MSB of each number. When the
microprocessor sees the add-with-carry instruction, it ac¬
tually adds three numbers. It adds the addend (MSB),
augend (MSB), and the carry flag. This brings the carry
from the LSB into the MSB.
- Carry (carry flag) from least significant
byte (LSB) being carried into the most
significant byte (MSB).
1111 i iii
0100 0111 0110 0101 Addend
+ 0010 0001 1101 0111 + Augend
0110 1001 0011 1100 Sum
MSB LSB
Fig. 18-9 Double-precision addition-with-carry.
274 Digital Computer Electronics
Subtraction
Each of the microprocessor families included in this text
has at least one subtraction instruction. Most have more
than one.
When subtracting binary numbers, the microprocessor
produces two types of information: (1) The difference
between the two numbers (answer) and (2) whether there
were borrows in certain columns.
If you don’t remember how to subtract binary numbers,
you may want to review Chap. 6 now. There are really
only four binary combinations you need to remember:
(1)
(2)
(3)
(4)
0
1
1
>0
-0
-0
-1
-1
0
1
0
1
The first three combinations produce the same answer as
they do in the decimal-number base system. Combination
#4 requires a borrow, which is shown by the small 1 set
as a superscript. You cannot have 0 and subtract 1 from it.
If you can borrow a 1 from the next-higher column, the
subtraction becomes possible. If there is a higher column
from which to borrow, this combination is really 2 l0 - 1 10
= 1 10 . That is, 10 2 is created after the borrow occurs, and
now the top number is larger than the bottom number. The
carry flag is used if there is no higher column from which
to borrow. You might say that it now becomes a “borrow”
flag.
The last combination is the only new one that you will
need to memorize since it is the only one that is different
from our decimal number system.
The above discussion appeared in Chap. 6 and has been
reviewed here for your convenience.
To continue our review, let’s see how to subtract several
columns. As in addition, it is common (and very practical)
to show 8-bit binary numbers in two groups of four (as two
nibbles). Refer to Fig. 18-10.
As you study Fig. 18-10, you will see that each individual
subtraction in each column is one of the four combinations
we presented a moment ago. When a borrow occurs, we
have shown the borrowed 1 as a superscript 1 next to the
0 which needed it. The 1 that was borrowed from is crossed
off, and its new value, 0, is shown above it.
Negative (Sign) Flag
The negative flag, sometimes called the sign flag , tells us
whether the number in the accumulator is a positive or
- From carry flag (indicates a borrow)
I- Half carry
w o *
^10/ ^ 0 1 1 339 (after borrow)
- 1 1 0 0 1 0 0 0 - 200
1 0 0 0 1 0 1 1 139
Fig. 18-10 Subtraction of binary numbers.
negative number. Since the most signficant bit of the
accumulator is the sign bit (when using signed binary
numbers), the negative flag simply reflects the status of that
bit. If the most significant bit is 0, the negative flag is 0,
and this is a positive number. If the most significant bit is
1, the negative flag will be 1, and this is a negative number.
While the negative flag always indicates the status of bit
7 of the accumulator, it is up to the programmer to determine
whether the number is to be interpreted as a signed or
unsigned binary number.
Figure 18-11 illustrates how the negative flag works.
Zero Flag
The zero flag shows that the last operation produced a result
of 0. This does not apply just to the accumulator but can
apply to other registers as well. This is especially helpful
when repeatedly decrementing (reducing by 1) an index
register to determine the number of times a loop has
executed. Knowing when a register has reached 0 is also
useful when branching to other parts of a program and
when determining whether or not to activate (call or enter)
certain subroutines.
The one unusual feature of the zero flag is that it contains
a 1 when the result is 0, and the flag is 0 when the result
is anything other than 0. While this may appear confusing
at first, it becomes second nature as you gain experience
with microprocessors.
The idea here is that a 0 says that something is false or
has not occurred. A 0 says, “No, this number was not the
number zero.”
A 1 says that something is true or has occurred. A 1
says, “Yes, this number is the number zero.”
Subtraction-with-Carry (Borrow)
The same carry flag that informs us that an addition problem
produced a sum which carried a 1 into the 9th bit also tells
us something about subtraction problems. Now it tells us
that to produce the answer (difference) the microprocessor
had to borrow a 1 from a 9th bit. This occurs when the top
number (minuend) is smaller than the bottom number
(subtrahend).
0110 0100
Accumulator
Positive signed
binary number
□
Negative flag
Negative signed
binary number
1 0 0 0 1 1 1 0 | | 1 |
Accumulator Negative flag
Fig. 18-11 The negative flag.
Chapter 18 Arithmetic and Flags 275
Refer again to Fig. 18-10. Notice that a borrow was
required from a column that doesn’t actually exist. There
is no 9th column. The carry flag acts as that column. It
tells us that a borrow from this “imaginary” column was
necessary.
Most microprocessors set the carry flag (make it a 1)
when a borrow is necessary (l=true). The exception to
this is the 6502 microprocessor. It clears the carry flag, as
though the borrow actually came from the flag itself. In the
6502 you must set the carry flag before you start a subtraction
problem so that, if a borrow is necessary, a 1 will be
present.
Some microprocessors also monitor the 4th bit during
subtraction. This is the half-carry flag which was mentioned
earlier in this chapter.
Multiplication and Division
The 8-bit microprocessors featured in this text do not have
multiplication or division instructions (the 6809, a relative
of the 6800 and 6808, does have a MULtiply instruction).
However, the 16-bit 8086/8088 has both multiply and divide
instructions, which will be discussed in the 8086/8088
section of this chapter.
There are several software algorithms for both multipli¬
cation and division which work well with the 8-bit micro¬
processors.
18-3 FLAG INSTRUCTIONS
Each of our microprocessors has instructions to alter the
state of its flags. Which of their flags and how many of
their flags can be directly altered vary.
The 8080/8085 has the fewest instructions for setting and
clearing flags. The 6502, 8086/8088, and 6800/6808 all
have the ability to set and clear many of their flags directly.
The 6800/6808 has an instruction which makes it possible
to move the status of all the flags into accumulator A and
to copy the contents of accumulator A into the flag register.
All our microprocessors except the 6800/6808 have the
ability to push all the flags onto the stack and retrieve them
from the stack. The 6800/6808 can accomplish the same
task by transferring the flags to accumulator A and then to
the stack in a two-step process.
We’ll discuss the specific uses for each flag instruction
in the Specific Microprocessor Families section of this
chapter. The uses for flag instructions can be generalized,
however. We use the flags primarily during arithmetic
operations and for control of loops, branches, and subrou¬
tines.
Since we use the flags to give us information about the
outcome of arithmetic operations, we often need to set or
clear flags before these math operations so that we are
certain of their exact condition before the operation begins.
We use flags to determine whether or not certain loops
should be repeated, whether branches into other parts of
the program should be taken, and whether certain subrou¬
tines should be called. Flags are used to make decisions
about which microprocessor instructions should be executed
next. This is the same as saying that the flags are used by
the program to make decisions. For these reasons we may
want to set or clear certain flags before or after certain
instructions are executed.
Specific Microprocessor
Families _
Let’s study the arithmetic and flag instructions for each of
our microprocessor families. We’ll be using short routines
to study operations for which each microprocessor has
specific instructions. We will not develop long routines to
facilitate arithmetic operations which are not inherent to
each microprocessor family. This will help you to become
familiar with your microprocessor’s basic arithmetic and
flag instructions.
18-4 6502 FAMILY
The 6502 probably has the fewest different arithmetic
instructions of any of our microprocessor families. However,
by conscientiously setting and clearing the appropriate flags
before arithmetic operations, this chip performs math op¬
erations adequately.
Arithmetic Instructions
The 6502 does not have normal add and subtract instruc¬
tions. It has only add-with-carry and subtract-with-carry.
Both of these instructions use the value in the accumulator
as one of their operands with another value which can be
an immediate value, or a value in memory, in addition to
the value in the carry flag. The value in memory can be
addressed any one of seven different ways. Let’s see how
to use these instructions.
Addition-with-Carry
Let’s start with a very simply addition program. Figure 18-
12 illustrates this type of program.
Notice first that we have used the CLC (CLear Carry)
instruction before we even loaded the accumulator with our
first operand. This is necessary when using the 6502
microprocessor. If the carry flag is set from a previous
operation, the ADC (ADd-with-Carry) instruction will add
276 Digital Computer Electronics
1 1
0 10 0
10 0 1
49 16
73 10
+ 0 0 0 1
1110
+ 1E,6
+ 30to
0 110
0 111
67 16
103 10
Addr
Assembler
Comment
0340
18
CLC
Prepare for addition problem
0341
A9
LDA #$49
Load accumulator with first number (49)
0342
49
0343
69
ADC #$1E
Add IE to the number in the accumulator
and place the answer in the accumulator
0344
IE
0345
00
BRK
Stop
Fig. 18-12 Simple 6502 addition problem.
the 1 in the carry flag to the answer and will cause the
answer to be incorrect (it will be 1 greater than the correct
result).
Pay particular attention to the accumulator and the
processor status register. Notice their contents both before
and after you run the program. (You may want to write
down their values before and after so that you can study
their behavior.) You will find that the accumulator will
have the number 67 16 in it (which is the correct answer)
and that only the BRK (BReaK) flag will be set.
Let’s look at the processor status register a little more
closely. Refer to Fig. 18-13 now.
Examining the flags from right to left, let’s consider eacn
and why it was or was not set during the last problem.
The carry flag would have been set if a carry from the
8th bit to the 9th bit (which doesn’t exist, so it goes into
the carry flag) had occurred, but none did.
The zero flag would have been set if the answer had
been 0, but it wasn’t.
Status register
Flags
N
V
—
B
D
1
z
c
0
0
X
1
0
0
0
0
1 - Carry flag
- Zero flag
- Interrupt flag
- Decimal mode flag
--- Break flag
- Unused
- Overflow flag
- Negative flag
Fig. 18-13 6502 processor status register.
Don’t worry about the interrupt flag since we haven’t
introduced this subject yet.
We dealt with the two operands as though they were
hexadecimal numbers so we didn’t set the decimal flag.
The break flag was set because we used the break
instruction to stop the program.
The status of the unused flag doesn’t matter.
We did not exceed the range of decimal + 127 to — 128
(hexadecimal 7F to 80); therefore the overflow flag was not
set.
Finally, we did not have a 1 in the 8th bit of the
accumulator so the answer could not have been negative;
therefore the negative flag was not set.
The Negative Flag
Let’s look at a problem which produces a negative answer.
Refer to Fig. 18-14 now.
Notice that this is exactly the same problem that was
used in Fig. 18-12 except that we have changed the first
operand, which used to be 49 16 into C9 16 , which is the
decimal number — 55 10 , if we consider these numbers to
be signed binary numbers. We know that — 55 10 + 30 lo
= — 25 10 . Since this is a negative answer, we know that
the negative flag should be set after the program is run.
Load the program and run it. Again write down the
contents of the accumulator and processor status register
before and after running the program so that you can
compare them. After the program is run, the accumulator
should contain the value E7 16 . The processor status register
should contain BO.
Let’s examine the status register again. The binary value
for B0 16 is 1011 0000 2 . If you put those bits into the
appropriate positions in the status register as shown in Fig.
18-15, you will see that 3 bits or flags are set.
The break flag is again set because we used the break
instruction to stop the program. We do not care about the
status of the unused bit.
Chapter 18 Arithmetic and Flags 277
1 1
110 0
100 1
C9i6
o
in
Lfi
1
+ 0 0 0 1
1110
+ IE,6
+ 30 10
1110
0 111
E7,6
-25 10
Obj
Assembler
Comment
18
CLC
Prepare for addition problem
A9
LDA #$C9
Load accumulator with first number (C9)
C9
0343
69
ADC #$1E
Add IE to the number in the accumulator
and place the answer in the accumulator
0344
IE
00
BRK
Stop
Fig. 18-14 Simple 6502 addition problem with negative
answer.
which produces a negative answer.
i iiii 1111
1100 1001
+0011 0111
1 0000 0000
The negative flag is now set, however. This is what we
expected to see. The sum of the addition problem was
— 25 10 (E7 16 ). If we assume that our numbers are signed
binary numbers, then any number that has a 1 in the 8th
bit is negative. E7 16 has a 1 in the 8th bit. The negative
flag simply reflects the state of the 8th bit.
The Zero Flag
Now let’s change the program so that we get a sum of 0.
Then we can see how the flags react to this situation.
Figure 18-16 shows the problem and the program to
solve the problem.
We are again assuming that our numbers are signed
binary numbers. The problem is C9 16 + 37 16 = 00 16 ,
which is — 55 10 + 55 10 = 0 lo . You should go through the
binary addition now before you run the program. Notice
both the answer and any carries.
Write down the contents of the accumulator and the
processor status register before and after running the pro¬
gram. You will notice that we are using the same program
as in the last problem but have again changed one of the
operands.
C9-J6 “55-iq
+ 37 16 + 55- tp
00 16 O-io
Addr
Comment
0340
18
CLC
Prepare for addition problem
0341
A9
LDA #$C9
Load accumulator with first number (C9)
0342
C9
69
ADC #$37
Add 37 to the number in the accumulator
and place the answer in the accumulator
1
37
00
BRK
Stop
Fig. 18-16 Simple 6502 addition problem which produces a
sum of 0.
278 Digital Computer Electronics
Now enter and run the program. The accumulator should
contain 00 16 , and the status register should contain 33. If
you place the bits of the status register in their proper places
as shown in Fig. 18-17, you will see how the flags have
responded to this problem.
Notice that the break flag and unused flag have again
been set as before. The value of the unused flag has no
meaning, and the break flag simply shows that we used a
break to stop the program.
The zero flag is set, as we supposed it would be. The
carry flag is also set. Notice in the binary addition that a
carry did indeed occur from the 8th to a nonexistent 9th
bit (which the carry flag acts as).
Status register
Flags
N
V
—
B
D
1
2
C
0
0
1
1
0
0
1
1
Fig. 18-17 6502 status register after an addition problem
which produces a sum of 0.
The Overflow Flag
When the overflow flag is set, it tells us that if the numbers
which were just added or subtracted are signed binary
numbers, then the valid range for such numbers has been
exceeded and the result is incorrect. The valid range for 8-
bit microprocessors, which the 6502 is, is + 127 to - 128.
Let’s change our problem to create an overflow.
Figure 18-18 shows our problem and program. Notice in
this problem that we are assuming that all values are to be
interpreted as signed binary values.
The problem shown here is 123 10 + llljo =_
First go through the binary addition and enter the program.
Then write down the values in the accumulator and processor
status register, run the program, and finally write down the
ending values of the accumulator and status register.
Status register
Flags
N
V
—
B
D
1
z
c
1
1
1
1
0
0
0
0
Fig. 18-19 6502 status register after an addition problem
which creates an overflow.
Figure 18-19 shows what the value in the status register
should be.
You should have a sum of EA 16 in the accumulator and
F0 l6 in the status register. EA 16 is the correct sum if you
are using unsigned binary numbers! If you interpret EA 16
as a signed binary number, it has a value of -22 10 . This
is not the correct answer. We have exceeded our valid
range for signed binary numbers.
The status register has a value of F0. This means that in
addition to the unused flag and the break flag, both the
overflow and the negative flags have been set.
It makes sense for the negative flag to be set because the
8th bit of the accumulator is set. This indicates a negative
number if the value is a signed binary number.
The overflow flag is set because we have exceeded our
range of 7F 16 (127 10 ) to 80 16 (— 128 10 ), giving an incorrect
result.
The Decimal Flag
Because of differences in the way binary and decimal
numbers round, and because numeric output to humans is
usually decimal, it is sometimes better to actually do
arithmetic calculations by using decimal numbers rather
than binary numbers. Actually, true decimal numbers are
not used. Rather, a mixture of binary and decimal, called
binary-coded decimal, is used. (The method used to create
BCD numbers is covered in Chap. 1 and they have been
discussed subsequently. You should review that section of
1111 iii
0 111 10 11 7B 16 123 10
+ 0110 1111 + 6F le + 111 10
1110 10 10 EA 16 234-iq
Addr
Obj
Assembler
Comment
0340
18
CLC
Prepare for addition problem
0341
A9
LDA #$7B
Load accumulator with first number (7B)
0342
7B
0343
69
ADC #$6F
Add 6F to the number in the accumulator
and place the answer in the accumulator
0344
6F
0345
00
BRK
Stop
Fig. 18-18 Simple 6502 addition problem which produces
an overflow.
Chapter 18 Arithmetic and Flags
279
Chap. 1 now if you are unsure of what BCD numbers are
or how they are formed.)
One of the problems encountered when using BCD
numbers is that, as the binary nibbles are added, invalid
results are sometimes obtained.
Most microprocessors have an instruction called decimal
adjust (or something similar). This instruction changes the
number in the accumulator to what it would be if the last
two numbers operated on had been BCD numbers instead
of binary numbers. The 6502 handles this a little differently.
It requires that you set a flag designed just for this purpose
and enter a ‘ ‘decimal mode, ’ ’ so to speak. When the decimal
0 1 0 0 0 1 1 1 BCD 47 10
+ 0011 0110 BCD + 36-iq
flag is set, all operands are assumed to be packed BCD
numbers.
Let’s look at an example. In Fig. 18-20 we have compared
a decimal addition problem to the binary version of the
same problem.
First notice the difference between BCD and binary
addition. BCD addition is not the same as binary addition.
BCD is decimal addition using four binary digits to represent
each decimal digit.
The program shown in Fig. 18-20 will help you understand
the difference between binary and BCD addition (and
subtraction). This program does the addition problem twice,
0 1 0 0 0 1 1 1 2 47-ie
+ 0 0 11 o i i o 2 + 36 16
7Di6 I
1 0 0 0 0 0 1 1 BCD 83 10 0 1 1 1 1 1 0 1 2
Decimal (BCD) Binary
This is not the same as this!
Assembler
Comment
0340
D8
CLD
Prepare to do binary addition
0341
18
mbm
A9
LDA #$47
This is being interpreted as a binary number
0343
A7
KOHOH
ADC #$36
This also is being considered a binary number
IKIHSI
8D
STA $03A0
We'll store the binary answer in memory location
03A0
A0
0348
03
0349
08
PHP
Put the flags on the stack
KB
68
PLA
Transfer flags from stack to accumulator
8D
STA $03A1
We'll store the status of the flags from the binary
addition in the memory location immediately
following the binary sum, which is location 03A1
034C
A1
034D
03
034E
■B
Prepare for decimal addition
034F
18
CLC
0350
A9
LDA #$47
This number is being interpreted as a decimal
number
KB
47
hum
69
ADC #$36
This number likewise is being considered a decimal
number
36
1 0354
8D
STA $03A2
We'll store the decimal answer in memory location
03A2
IIBB
A2
0356
03
0357
08
Put the flags on the stack [
0358
68
Transfer the flags to the accumulator
0359
8D
STA $03A3
We'll store the status of the flags resulting from this
decimal addition in the memory location immediately
following the decimal sum, that is, location 03A3
035A
A3
035B
03
035C
00
BRK
Stop
Fig. 18-20 Binary vs. BCD addition.
280 Digital Computer Electronics
once using binary numbers and once using BCD numbers.
The result of the binary addition is stored in memory
location 03A0 16 , and the resulting flags in location 03A1 16 .
The result of the BCD addition is stored in location 03A2 16 ,
and the resulting flags in location 03A3 16 . Enter and run
this program to see what results you get. (Don’t be concerned
about the reference to the stack in the program. We’ll study
the stack in a later chapter. For now just think of it as a
temporary storage area.) When we ran the program we
found the following:
location 03A0 16 =
location 03A1 16 =
location 03A2 16 =
location 03A3 16 =
binary sum = 7D
binary flags = 30
BCD sum = 83
BCD flags = F8
The status of the binary flags indicates only that the break
instruction had been used to stop the program. No other
flags were set.
The status of the flags after the BCD addition indicates
that the decimal flag was set. (We set this flag to get into
the "‘decimal mode.”) The negative flag was set but has
no valid meaning. It was simply following the state of the
8th bit of the accumulator. The overflow flag was set, but
it also has no valid meaning in BCD arithmetic.
Subtraction-with-Carry
Subtraction-with-carry is the opposite of addition-with-
carry. As in addition, there is no simple subtract instruction,
only subtract-with-carry.
The 6502 handles borrows differently from the way most
other microprocessors do. Most microprocessors set the
carry flag if either a carry or a borrow occurs. The 6502
sets the flag if a carry occurs and clears the flag if a borrow
occurs. It is important to remember that the carry flag must
be set before a subtraction problem (or the first section of
a multiple-precision subtraction problem) so that if a borrow
is needed , it can clear the carry flag, which then indicates
that the borrow has occurred. If the carry flag is not set
before starting the subtraction, the answer will be incorrect .
(It will be 1 less than the correct result.)
Figure 18-21 illustrates the correct way to write a program
to do single-precision subtraction.
You should assemble and run this program. When we
did, we found that the result in the accumulator was FF.
We also found that the overflow and negative flags had
been set. The negative flag was set because the 8th bit of
the answer is a 1, which indicates a negative-signed binary
number. The overflow flag was set because 7F 16 = 127 10 ,
and 80 l6 = - 128 10 ; therefore
127
- -128
255
and 255 10 is outside the valid range for 8-bit signed binary
numbers. (The valid range is + 127 10 to - 128 10 .)
18-5 6800/6808 FAMILY
The 6800/6808 has a variety of add and subtract instructions
which can use either of its two accumulators and can address
memory locations in several ways. The 6800/6808 can also
add and subtract binary-coded decimal (BCD) numbers.
Arithmetic Instructions
The 6800/6808 has add , subtract , add-with-carry, subtract-
with-carry, add accumulator A to accumulator B, subtract
accumulator B from accumulator A , and decimal adjust
accumulator A instructions. These instructions use the value
in one of the accumulators as one of their operands and
another value which can be an immediate value or a value
in memory. Let’s see how to use these instructions.
Addition
Let’s start with a very simple addition program. Figure
18-22 illustrates this type of program.
Pay particular attention to the accumulator and the
condition code register (status register). Notice their contents
both before and after you run the program. (You may want
to write down their values before and after so you can study
Addr
Obj
Assembler
Comment
0340
38
SEC
Remember this step!
0341
A9
LDA #$7F
0342
7F
0343
E9
SBC #$80
0344
80
0345
00
BRK
Fig. 18-21 Subtraction-with-carry.
Chapter 18 Arithmetic and Flags 281
1 1
0 10 0
10 0 1
49ie
o
00
I--*
+ 0 0 0 1
1110
+ 1 ^16
+ 30 10
0 110
0 111
67 16
1 03iq
Obj
Assembler
Comment
86
LDAA #$49
Load accumulator with first number (49)
49
8B
ADDA #$1E
Add IE to the number in the accumulator and
place the answer in the accumulator
0004
WAI
Stop
Fig. 18-22 Simple 6800/6808 addition problem.
their behavior.) You will find that the accumulator will
have the number 67 16 in it (which is the correct answer)
and that only the half-carry flag will be set.
Let’s look at the status register a little more closely.
Refer to Fig. 18-23 now.
Examining the flags from right to left, let’s consider each
and why it was or was not set.
The carry flag would have been set if a carry from the
8th bit to the 9th bit (which doesn’t exist, so it goes into
the carry flag) had occurred, but none did.
We did not exceed the range of +127 l0 to —128 10
(hexadecimal 7F to 80); therefore the overflow flag was not
set.
The zero flag would have been set if the answer had
been zero, but it wasn’t.
We did not have a 1 in the 8th bit of the accumulator so
the answer could not have been negative; therefore the
negative flag was not set.
Don’t worry about the interrupt flag since we haven’t
introduced this subject yet.
The half-carry flag was set because we had a carry from
the 4th bit to the 5th bit. (Information about the half-carry
is useful when dealing with BCD numbers.)
The status of the unused flags doesn’t matter.
The Negative Flag
Now let’s look at a problem that produces a negative
answer. See Fig. 18-24.
Notice that this is exactly the same problem as the last
one except that we have changed the first operand, which
was 49 16 , into C9 16 , which is the number — 55 10 if we
consider these numbers to be signed binary numbers. We
know that - 55 10 + 30 10 = — 25 10 . Since this is a negative
answer, we know that the negative flag should be set after
the program is run.
Write down the contents of the accumulator and processor
status register before running the program so that you know
what the initial conditions are. Now load the program and
run it. After you run the program, the accumulator should
Fig. 18-23 6800/6808 status register.
282 Digital Computer Electronics
1 1
110 0
10 0 1
C9 16
-55,o
+ 0 00 1
1110
+ 1E 16
+ 30,o
1110
0 111
CjO
r**
LU
-25,o
Addr
Obj
Assembler
Comment
0000
86
LDAA #$C9
Load accumulator with first number (C9)
0001
C9
8B
ADDA #$1E
Add IE to the number in the accumulator and
place the answer in the accumulator
IE
| 0004
3E
WAI
Stop
Fig. 18-24 Simple 6800/6808 addition problem with negative
answer.
contain the value E7 16 . The status register should contain
XX101000.
Let’s examine the status register again. If you put the
bits into their appropriate positions in the status register as
shown in Fig. 18-25, you will see that 2 bits or flags are
set.
Status register
Flags
1
1
H
1
N
Z
V
c
1
1
1
0
1
0
0
0
Carry flag
Overflow flag
Zero flag
Negative flag
Interrupt flag
Half-carry flag
Unused
Unused
Fig. 18-25 6800/6808 status register after an addition
problem which produces a negative answer.
i 1111 iii
1100 1001
+0011 0111
1 0000 0000
The half-carry flag is again set because we had a carry
from the 4th to the 5th bit of the result. The difference is
that the negative flag is now set. This is what we expected
to see. The sum of the addition problem was -25 10 (E7 16 ).
If we assume that our numbers are signed binary numbers,
then any number that has a 1 in the 8th bit is negative.
E7 16 has a 1 in the 8th bit.
The Zero Flag
Now let’s change the program slightly so that we get a sum
of 0. Then we can see how the flags react to this situation.
Figure 18-26 shows the problem and the program to
solve the problem.
We are again assuming that our numbers are signed
binary numbers. The problem is C9 16 + 37 16 = 00 16
( 55 iq + 55 10 = 0 lo ). You should go through the binary
addition of these two numbers now before you run the
program. Notice both the answer and the carries.
Again write down the contents of the accumulator and
the status register before and after running the program.
You will notice that we are using the same program as the
ast example but have changed one of the operands.
Now enter and run the program. The accumulator should
contain 00 16 , and the status register should contain XX100101 2 .
If you place the bits of the status register value in their
C9i 6 -55,o
+ 37 16 + 55- iq
00ie 0 10
I^S
Obj
Assembler
Comment
0000
86
LDAA #$C9
Load accumulator with first number (C9)
0001
C9
8B
ADDA #$37
Add 37 to the number in the accumulator and
place the answer in the accumulator
1
37
1 0004
3E
WAI
Stop
Fig. 18-26 Simple 6800/6808 addition problem which
produces a sum of 0.
Chapter 18 Arithmetic and Flags 283
D
n
D
n
D
E
I
□
D
D
D
D
D
D
m
D
Fig. 18-27 6800/6808 status register after an addition
problem which produces a sum of 0.
proper places as shown in Fig. 18-27, you will see how
the flags have responded to this problem.
Notice that the half-carry flag has again been set. The
zero flag is set, as we supposed it would be. The carry flag
is also set. Notice in the binary addition that a carry did
indeed occur from the 8th to a nonexistent 9th bit (which
the carry flag acts as).
The Overflow Flag
When the overflow flag is set, it tells us that if the numbers
which the microprocessor just added or subtracted are
signed binary numbers, the valid range for such numbers
has been exceeded and the result is incorrect. The valid
range for 8-bit microprocessors is +127 to —128. Let’s
change our problem to create an overflow.
Figure 18-28 shows our problem and program. Note that
in this problem we are assuming that all values are to be
interpreted as signed binary values.
This problem is 123 10 T 111 10 =-First g°
through the binary addition and enter the program. Then
write down the values of the accumulator and status register,
run the program, and finally write down the final values of
the accumulator and status register.
Figure 18-29 shows what the value in the status register
should be.
You should have a sum of EA 16 in the accumulator and
XX101010 2 in the status register. EA 16 is the correct sum
if you are using unsigned binary numbers! If you interpret
EA, 6 as a signed binary number, it has a value of -22 10 .
Status register
Flags
1
H
1
N
Z
V
D
D
a
D
a
D
a
a
Fig. 18-29 6800/6808 status register after an addition
problem which creates an overflow.
This is not the correct answer. We have exceeded our valid
range for signed binary numbers.
The status register has a value of XX101010. This means
that in addition to the half-carry flag, both the overflow and
the negative flags have been set.
It makes sense for the negative flag to be set because the
8th bit of the accumulator is set. This indicates a negative
number if the value is a signed binary number.
The overflow flag is set because we have exceeded our
range of 7F 16 (127 10 ) to 80 16 (— 128 10 ), and the result is
incorrect.
Decimal Addition
Because of differences in the way binary and decimal
numbers round, and because numeric output to humans is
usually decimal, it is sometimes helpful to actually do
arithmetic calculations by using decimal numbers rather
than binary numbers. Actually, true decimal numbers are
not used. Rather a mixture of binary and decimal, called
binary-coded decimal, is used. (The method used to create
BCD numbers is covered in Chap. 1, and they have been
discussed subsequently. You should review that section of
Chap. 1 now if you are at all unsure of what BCD numbers
are or how they are formed.)
One of the problems encountered in using BCD numbers
is that, as the binary nibbles are added, invalid results are
sometimes obtained.
Most microprocessors have an instruction called decimal
adjust (or something similar). This instruction changes the
1111 iii
0 111 10 11 7B 16 123i 0
+ 0110 1111 + 6F 16 +m 10
1110 10 10 EA 16 234,0
■Snag
— 1 —
E
Fig. 18-28 Simple 6800/6808 addition problem which
produces an overflow.
284 Digital Computer Electronics
number in the accumulator to what it would be if the last
two numbers operated on were packed BCD (binary-coded
decimal) numbers instead of binary numbers.
Let s look at an example. Figure 18-30 compares a
decimal addition problem to the binary version of the same
problem.
Notice first the difference between BCD and binary
addition. BCD addition is not at all the same as binary
addition. BCD is decimal addition using four binary digits
to represent each decimal digit.
The program shown in Fig. 18-30 will help you understand
the difference between binary and BCD addition (and
subtraction). This program does the addition problem twice,
once using binary numbers and once using BCD numbers.
The result of the binary addition is stored in memory
location A0 16 , and the resulting flags in location Al 16 . The
result of the BCD addition is stored in location A2 16 , and
the resulting flags in location A3 16 . Enter and run this
program to see what results you obtain. When we ran the
program, we found the following:
location A0 16 = binary sum = 7D
location Al 16 = binary flags = 000000
0 1 0 0 0 1 1 1 BCD 47 10
+ 0011 0110 BCD + 36 10
location A2 16 = BCD sum = 83
location A3 16 = BCD flags = 001000
The status of the binary flags indicates that no flags were
set as a result of the binary addition. After the BCD
addition, the negative flag was set but has no valid meaning.
It is simply following the state of the 8th bit of the
accumulator.
Subtraction
Subtraction is the opposite of addition. All the flags operate
the same except the carry flag. After subtraction, the carry
flag indicates whether or not a borrow has occurred. You
can think of it as a 4 ‘borrow” flag. A 1 in the carry flag
position indicates that a borrow from the nonexistent 9th
bit was required to do the subtraction. A 0 indicates that
no borrow from the 9th bit was required.
Figure 18-31 illustrates how to write a program to do
single-precision subtraction.
You should assemble and run this program. When we
did, we found that the result in the accumulator was FF.
0 10 0 o 1 1 1 2 47 16
+ 0011 0 1 1 0 ? + 36 16
7D 16 |
1 0 0 0 0 0 1 1 BCD 83 10 | 0111 1 1 0 1 2
Decimal (BCD) Binary
This is not the same as this 1
Addr
Obj
Assembler
Comment
86
LDAA #$47
This is being interpreted as a binary number
47
8B
ADDA #$36
This also is being considered a binary number
0003
36
0004
97
STAA #A0
We'll store the binary answer in memory location
03A0
IWIliSi
A0
0006
07
TPA
Transfer flags to accumulator
0007
97
STAA #A1
We'll store the status of the flags from the binary
addition in memory location A1
0008
A1
0009
86
LDAA #$47
This number is being interpreted as a decimal number
000A
47
8B
ADDA #$36
This number likewise is being considered a decimal
number
oooc
36
000D
19
DAA
Make the answer decimal
000E
_ 97
STAA $A2
We'll store the decimal answer in memory location
03A2
000F
CM
<
IHKwflil
07
TPA
Transfer the flags to the accumulator
0011
97
STAA $A3
We'll store the status of the flags resulting from
this decimal addition in memory location A3
0012
A3
0013
3E
WAI
Stop |
Fig. 18-30 Binary vs. BCD addition.
Chapter 18 Arithmetic and Flags 285
Addr
Assembler
Comment
0000
86
LDAA #$7F
0001
7F
0002
01
SUBA #$80
80
0004
3E
WAI
Fig. 18-31 Subtraction.
We also found that the overflow, negative, and carry flags
had been set. The negative flag was set because the 8th bit
of the answer is a 1, which indicates a negative-signed
binary number. The overflow flag was set because 7F 16 =
127 10 , and 80 16 = - 128 10 ; therefore
127
-(-128 )
255
and 255 10 is outside the valid range for 8-bit signed binary
numbers (the valid range is + 127, 0 to — 128, 0 ). The carry
flag was set because a borrow from a 9th bit was needed
to complete the subtraction.
18-6 8080/8085/Z80 FAMILY
The 8080/8085/Z80 family has a variety of add and subtract
instructions. The 8080/8085/Z80 can also work with binary-
coded decimal (BCD) numbers.
1 1
0100 1001
+ 0001 1110
0110 0111
Arithmetic Instructions
The 8080/8085/Z80 family has add , subtract , add-with-
carry, subtract-with-borrow, immediate mode and decimal
adjust accumulator A instructions. These instructions use
the value in the accumulator as one of their operands and
another value in one of the other registers as the other
operand. Let’s see how to use these instructions.
Addition
Let’s start with a very simple addition program. Figure
18-32 illustrates this type of program.
Pay particular attention to the accumulator and the status
register. Notice their contents both before and after you
run the program. (You may want to write down their values
before and after so that you can study their behavior.) You
will find that the accumulator will have the number 67 16 in
it (which is the correct answer) and that only the half-carry
flag will be set.
Let's look at the status register a little more closely.
Refer to Fig. 18-33.
49t6 73 10
+ 1 E 16 + 30i q
67 16 103 10
Addr
Obj
Assembler
Comment
1800
3E
MVI A,49
Load accumulator with first number (49)
1801
49
1802
C6
ADI IE
Add IE to the number in the accumulator and
place the answer in the accumulator
1803
IE
1804
76
HALT
Stop
(8080/8085 mnemonics)
Obj
Comment
| 1800
3E
LD A,49
Load accumulator with first number (49)
49
1802
C6
ADD A,IE
Add IE to the number in the accumulator and
place the answer in the accumulator
1803
IE
1804
76
HALT
Stop
(Z80 mnemonics)
Fig. 18-32 Simple 8080/8085/Z80 addition problem.
286 Digital Computer Electronics
Fig. 18-33 8080/8085/Z80 status registers after addition
problem.
Examining the flags from right to left, let’s consider each
and why it was or was not set.
The carry flag would have been set if a carry from the
8th bit to the 9th bit (which doesn’t exist, so it goes into
the carry flag) had occurred, but none did.
(Note to Z80 users: Ignore the negative flag.)
The parity flag was not set because the answer 0110
0111 2 has an odd number of Is. That is to say it has odd
parity, which is indicated by a 0. (Note to Z80 users: We
did not exceed the range of decimal +127 to -128-
hexadecimal 7F to 80; therefore the parity!overflow flag
was not set.)
The microprocessor set the auxiliary carry (half-carry)
flag because we had a carry from the 4th bit to the 5th bit.
(Information about the half-carry is useful when dealing
with BCD numbers.)
The zero flag would have been set if the answer had
been zero, but it wasn’t.
We did not have a 1 in the 8th bit of the accumulator so
the answer could not have been negative; therefore the sign
flag was not set.
The status of the unused flags doesn’t matter.
The Sign Flag
Let s look at a problem that produces a negative answer.
See Fig. 18-34.
Notice that this is the same problem as the last one
except that we have changed the first operand. It used to
49 16 , but it is now C9 16 , which is the decimal number
-55 10 if we consider these numbers to be signed binary
numbers. We know that -55 10 + 30 10 = -25 10 . Since
this is a negative answer, we know that the sign flag should
be set after the program is run.
Write down the contents of the accumulator and status
register before running the program so that you know the
initial conditions. Load the program and run it. After the
program is run, the accumulator should contain the value
E7 16 . The status register should contain 10-1-1-0 [Z80 =
10 - 1 - 000 ].
Let’s examine the status register. If you put the status
register bits into the appropriate positions in the status
register as shown in Fig. 18-35, you will see what the bits
indicate.
The auxiliary-carry [half-carry] is set again because we
had a carry from the 4th to the 5th bit of the result.
The difference this time is that the sign flag is now set.
This is what we expected to see. The sum of the addition
problem was — 25 10 (E7 16 ). If we assume our numbers are
signed binary numbers, then any number that has a 1 in
the 8th bit is negative. E7 16 has a 1 in the 8th bit. The sign
flag simply reflects the state of the 8th bit.
[Note to 8085 users: Your parity flag is 1 this time
because the answer (E7 16 ) has an even number of Is in it
and even parity is indicated by a 1 in the parity flag. Note
to Z80 users: Your parity!overflow flag is 0 just like last
time because the answer did not exceed the range from
+ 127 l0 to -128 l0 .]
The Zero Flag
Now let’s change the program slightly so that we get a sum
of 0. That way we can see how the flags react to this
situation.
Figure 18-36 shows the problem and the program to
solve the problem.
We are again assuming that our numbers are signed
binary numbers. The problem is C9 16 + 37 16 = 00 16
Chapter 18 Arithmetic and Flags 2S7
1 1
110 0
100 1
C9ie
-55 10
+ 00 0 1
1110
+
m
CD
+ 30io
1110
0 111
E7 16
-25 10
Obj
Assembler
Comment
1800
3E
1801
C9
■■
C6
ADI IE
Add IE to the number in the accumulator and
place the answer in the accumulator
1803
IE
1804
76
HALT
Stop
(8080/8085 mnemonics)
Addr
Obj
Assembler
Comment
1800
3E
LD A,C9
Load accumulator with first number (C9)
1801
C9
C6
ADD A # 1E
Add IE to the number in the accumulator and
place the answer in the accumulator
IE
1804
76
HALT
Stop
(Z80 mnemonics)
Fig. 18-34 Simple 8080/8085/Z80 addition problem with
negative answer.
(-55 10 + 55 10 = O 10 ). You should go through the binary
addition of these two numbers now before you run the
program. Notice both the answer and the carries.
Again write down the contents of the accumulator and
the status register before and after running the program.
You will notice that we are using the same program but
have changed one of the operands.
Now enter and run the program. The accumulator should
contain 00! 6 and the status register should contain 01-1-1-1
[Z80 = 01-1-001]. If you place the bits of the status
register value in their proper places as shown in Fig.
18-37, you will see how the flags have responded to this
problem.
Notice that the half-carry flag has again been set.
The zero flag is set, as we supposed it would be.
The carry flag is also set. Notice in the binary addition
Fig. 18-35 8080/8085/Z80 status registers after an addition
problem which produces a negative answer.
Status register
Flags
S
z
—
H
—
P
N
c
1
0
—
1
—
0
0
0
1 - Carry flag (CY)
- Negative flag
- Parity/overflow (PV)
- Unused
- Half carry
- Unused
- Zero flag
-—- Sign flag
Z80 Status register
288 Digital Computer Electronics
1 1111 111
11 00 1 0 0 1 C9 16 -55 10
+ 0 0 1 1 0 1 1 1 + 37 i 6 + 55 -iq
1 0000 0000 00 16 0 10
Obj
Assembler
Comment
1800
3E
MVI A,C9
Load accumulator with first number (C9)
C9
C6
ADI 37
Add 37 to the number in the accumulator and
place the answer in the accumulator
■sa
37
76
HALT
Stop
(8080/8085 mnemonics)
Addr
Obj
Assembler
Comment
3E
LD A,C9
Load accumulator with first number (C9)
C9
C6
ADD A,37
Add 37 to the number in the accumulator and
place the answer in the accumulator
37
76
HALT
Stop
(Z80 mnemonics)
Fig. 18-36 Simple 8080/8085/Z80 addition problem which
produces a sum of 0.
that a carry did indeed occur from the 8th bit to a nonexistent
9th bit (which the carry flag acts as).
The 8085 parity flag is set indicating an even number of
Is. (Note to Z80 users: Your parity!overflow flag is cleared
indicating you have not exceeded the range for 8-hit signed
binary numbers , from + 727 10 to -72<S 10 .)
The Parity Flag [Z80: Parity/Oveiflow Flag]
The 8080/8085 and Z80 microprocessors differ slightly in
the function of this flag. Let’s look at the 8080/8085 first.
Status register
Flags
S
z
—
A
—
P
—
C
0
1
—
1
—
1
—
1
8080/8085 Status register
Status register
Flags
S
Z
—
H
—
P
N
C
0
1
—
1
—
0
0
1
Z80 Status register
Fig. 18-37 8080/8085/Z80 status registers after an addition
problem which produces a sum of 0.
The 8080/8085 microprocessors have a parity flag which
simply tells us how many Is are in the accumulator after
an arithmetic or a logic operation. Even parity exists when
an even number of Is are in the accumulator. Odd parity
exists when an odd number of Is exist in the accumulator.
Even parity is shown by a 1 in the parity flag, and odd
parity by a zero in the parity flag.
The Z80 has a combination parity/overflow flag. During
logic operations it indicates parity as just described for the
8080/8085. During arithmetic operations, however, it acts
as an overflow flag.
When an overflow flag is set, it tells us that if the
numbers which were just added or subtracted are signed
binary numbers, then the valid range for such numbers has
been exceeded and the result is incorrect. The valid range
for 8-bit microprocessors is +127 to -128. Let’s change
our problem to create an overflow.
Figure 18-38 shows our problem and program. In this
problem it is important to note that we are assuming that
all values are to be interpreted as signed binary values.
This problem is + 123 10 + 111 10 =-First go
through the binary addition and enter the program. Then
write down the values in the accumulator and status register,
run the program, and finally write down the values of the
accumulator and status register after the program has run.
Figure 18-39 shows what the value in the status register
should be.
You should have a sum of EA 16 in the accumulator and
10-1-0-0 [Z80: 10-1-100] in the status register. EA 16 is the
correct sum if you are using unsigned binary numbers! If
Chapter 18 Arithmetic and Flags 289
1111 111
0 111
10 11
7B 16
123iq
+ 0110
1111
+ 6F 16
+ 111io
1110
10 10
ea 16
234 10
Assembler
Comment
1800
3E
MVI A,7B
Load accumulator with first number (7B)
1801
7B
1802
C6
ADI 6F
Add 6F to the number in the accumulator and
place the answer in the accumulator
1803
6F
1804
76
HALT
Stop
(8080/8085 mnemonics)
Addr
Obj
Assembler
Comment
1800
3E
LD A,7B
Load accumulator with first number (7B)
1801
7B
1802
C6
ADD A,6F
Add 6F to the number in the accumulator and
place the answer in the accumulator
im
6F
1804
76
HALT
Stop
(Z80 mnemonics)
Fig. 18-38 Simple 8080/8085/Z80 addition problem which
produces an overflow.
you interpret EA 16 as a signed binary number, it has a value
of — 22 10 . This is not the correct answer. We have exceeded
our valid range for signed binary numbers.
The status registers of both the 8080/8085 and the Z80
microprocessors have a 1 in the half-carry flag as before.
Now however, both also have a sign flag that is set. It
makes sense for the sign flag to be set because the 8th bit
of the accumulator is set. This indicates a negative number
if the value is a signed binary number.
Status register
Flags
S
Z
—
A
—
P
—
c
1
0
—
1
—
0
—
0
8080/8085 Status register
Status register
Flags
S
Z
—
H
—
P
N
C
1
0
—
1
—
1
0
0
Z80 Status register
Fig. 18-39 8080/8085/Z80 status registers after an addition
problem which creates an overflow.
The parity flag of the 8080/8085 is 0 because the answer
(EA 16 ) contains five Is and 5 is an odd number. However,
the parity/overflow flag of the Z80 acts as an overflow flag
during an arithmetic instruction and is 1 because we have
exceeded our range of 7F 16 (127 10 ) to 80 16 (— 128 10 ) for
8-bit signed binary numbers, and the result is therefore
incorrect.
Decimal Addition
Because of differences in the way binary and decimal
numbers round, and because numeric output to humans is
usually decimal, it is sometimes useful to do arithmetic
calculations by using decimal numbers rather than binary
numbers. Actually, true decimal numbers are not used.
Rather a mixture of binary and decimal, called binary-
coded decimal is used. (The method used to create BCD
numbers is covered in Chap. 1, and they have been discussed
subsequently. You should review that section of Chap. 1
now if you are unsure of what BCD numbers are or how
they are formed.)
One of the problems involved in using BCD numbers is
that as the binary nibbles are added, invalid results are
sometimes obtained.
Most microprocessors have an instruction called decimal
adjust (or something similar). This instruction changes the
number in the accumulator to what it would be if the last
two numbers operated on had been packed BCD numbers
instead of binary numbers.
290 Digital Computer Electronics
Let’s look at an example. Figure 18-40 compares a
decimal addition problem to the binary version of the same
problem.
Notice first the difference between BCD and binary
addition. BCD addition is not at all the same as binary
addition. BCD is decimal addition using 4 bits to represent
each decimal digit.
The program shown in Fig. 18-40 will help you understand
the difference between binary and BCD addition (and
subtraction). This program does the addition problem twice,
once using binary numbers and once using BCD numbers.
The result of the binary addition is stored in memory
location 18A0 16 , and the resulting flags in location 18A1 16 .
The result of the BCD addition is stored in location 18A2 16 ,
0 1 0 0 0 1 1 1 BCD 47 10
+ 0011 0110 BCD + 36 10
■ 1000
and the resulting flags in location 18A3 16 . Enter and run
this program to see what results you get. When we ran the
program, we found the following:
location 18A0 16 = binary sum = 7D
location 18A1 16 = binary flags = 00-0-1-0
[Z80:00-0-000]
location 18A2 l6 = BCD sum = 83
location 18A3 16 = BCD flags = 10-1-0-0
[Z80:10-1-000]
The status of the flags after the binary addition indicates
that no flags were set (except the 8080/8085 parity flag
indicating even parity).
0 1 0 0 0 1 1 1 2 47 16
+ 0 0 1 1 0 1 1 0 2 + 36 16
~7Di6 I
0 0 11 BCD 83 10 | , 0 111 110 1
Decimal (BCD) Binary
This is not the same as this!
Addr
Obj
Assembler
Comment
1800
3E
MVI A,47
This is being interpreted as a binary number
1801
47
1802
C6
ADI 36
This also is being considered a binary number
1803
36
1804
32
STA 18A0
We'll store the binary answer in memory location
18 A0
1805
A0
1806
18
1807
F5
PUSH PSW
Put the flags and accumulator in stack
1808
Cl
POP B
Retrieve flags and accumulator into register B and C
1809
79
MOV A,C
Move the flags from register C to the accumulator
180A
32
STA 18A1
We'll store the status of the flags from the binary
addition in memory location 18A1
180B
A1
180C
18
180D
3E
MVI A, 47
This is being interpreted as a decimal number
180E
47
180F
C6
ADI 36
This also is being considered a decimal number
1810
36
1811
27
DAA
Convert the answer to decimal
1812
32
STA 18A2
We'll store the decimal answer in memory location
18A2
1813
A2
1814
18
1815
F5
PUSH PSW
Put the flags and accumulator in stack
1816
Cl
POP B
Retrieve flags and accumulator into registers B and C
1817
79
MOV A,C
Move the flags from register C to the accumulator
1818
32
STA 18A3
We'll store the status of the flags from the binary
addition in memory location 18A3
1819
A3
181A
18
181B
76
HALT
Stop
(8080/8085 mnemonics)
Fig. 18-40 Binary vs. BCD addition. (Continued on next page.)
Chapter 18 Arithmetic and Flags 291
Addr
Obj
Assembler
Comment
1800
3E
LD A,47
This is being interpreted as a binary number
1801
47
1802
C6
This also is being considered a binary number
mem
36
1 1804
32
We'll store the binary answer in memory location
18A0
1805
A0
1806
18
1807
PUSH AF
Put the flags and the accumulator in stack
1808
Retrieve flags and accumulator into registers B and C
1809
79
LD A,C
Move the flags from register C to the accumulator
180A
32
LD<18A1),A
Well store the status of the flags from the binary
addition in memory location 18A1
180B
A1
180C
18
180D
3E
LD A, 47
This is being interpreted as a decimal number
! 180E
47
180F
C6
ADD A,36
This also is being considered a decimal number
1810
36
1811
27
DAA
Convert the answer to decimal
1812
32
LD (18A2), A
We'll store the decimal answer in memory location
18A2
1813
A2
1814
18
1815
F5
PUSH AF
Put the flags and accumulator in stack
1816
Cl
POP BC
Retrieve flags and accumulator into registers B and C
^hh^h
79
LD A,C
Move the flags from register C to the accumulator
32
LD (18A3),A
We'll store the status of the flags from the binary
addition in memory location 18A3
1819
A3
181A
18
181B
76
HALT
Stop
(Z80 mnemonics)
Fig. 18-40 (Continued)
After the BCD addition, the sign flag was set, but it has
no valid meaning. It simply follows the state of the 8th bit
of the accumulator.
Several points must be kept in mind when doing decimal
addition and subtraction on the 8080/8085 and Z80 micro¬
processors.
With the 8080/8085 microprocessors, the DAA instruc¬
tion only works after addition. Also, the DAA instruction
works only with the accumulator.
With the Z80 microprocessor, the DAA instruction can
be used after either addition or subtraction. This is made
possible by the addition of the negative flag which the
8080/8085 does not have. This flag simply keeps track of
whether an addition or subtraction was just performed. This
flag is used in combination with the half-carry flag to correct
the BCD answers.
Subtraction
Subtraction is the opposite of addition. All the flags operate
the same except the carry flag. After subtraction, the carry
flag indicates whether a borrow has occurred. You can
think of it as a k ‘borrow” flag. A 1 in the carry flag position
indicates that a borrow from the nonexistent 9th bit was
required to do the subtraction. A 0 indicates that no borrow
from the 9th bit was required.
Figure 18-41 illustrates how to write a program to do
single-precision subtraction.
You should assemble and run this program. When we
did, we found that the result in the accumulator was FF.
We also found that the overflow (. Z80 ), sign, and carry
flags had been set. The sign flag was set because the 8th
bit of the answer is a 1 which indicates a negative-signed
binary number. The overflow flag was set because 7F 16 =
127 10 and 80 16 = — 128 10 ; therefore
127
-(-128 )
255
and 255io is outside the valid range for 8-bit signed binary
numbers. (The valid range is + 127, 0 to — 128 10 .) The
292 Digital Computer Electronics
Addr
Obj
Assembler
Comment
1800
3E
MVI A,7F
1801
7F
1802
D6
SUI80
1803
80
1804
76
HALT
(8080/8085 mnemonics)
Addr
Obj
Assembler
Comment
1800
3E
LD A,7F
1801
7F
1802
D6
SUB A,80
1803
80
1804
76
HALT
(280 mnemonics)
Fig. 18-41 Subtraction.
carry flag was set because a borrow from a 9th bit was
needed to complete the subtraction.
18-7 8086/8088 FAMILY
The 8086/8088 has a variety of arithmetic instructions and
various support instructions. The 8086/8088 can also work
with ASCII and binary-coded decimal (BCD) numbers.
Arithmetic Instructions
The 8086/8088 has add , subtract , add-with-carry, subtract-
with-borrow, ASCII adjust, multiply, divide, integer mul¬
tiply, integer divide, and conversion instructions. These
instructions use a value in one of the registers, memory,
or an immediate number as their operands. Let’s see how
to use these instructions.
DEBUG Revisited
In just a moment we are going to begin studying some
sample arithmetic programs for the 8086/8088 micropro¬
cessor. However, we must first learn more about the DEBUG
utility.
Until now, we have assembled each program with
DEBUG and then executed the program by using the trace
command. Trace executes one instruction, displays the
contents of the registers and flags, and then stops. This
works well when the program is only a few lines long or
when you must carefully observe the effect each instruction
has on the registers. It is very slow, however.
DEBUG has another command which executes an entire
program without stopping until the end. This is the g (go)
command. Of course, the computer has to know where to
start. If you just use the g command the computer assumes
that it should start program execution at the memory location
indicated by the instruction pointer (IP). If that is not where
you want to start, such as when you want to execute a
program for the second time, you have two ways to specify
where to start. One way is to change the instruction pointer
with the r (register) command. This is accomplished as
follows:
-rip
IP 0100
:0100
You should start your assembly-language programs at or
after address 0100H. The other way is to specify a starting
point as part of the g (go) command. To start at memory
location 0100H, for example, you would type
g = 0100
Execution would start at address 0100 even though the
instruction pointer might not contain that address.
When you use the g (go) command, the computer also
has to know where to stop. You might think that the HLT
(HaLT) instruction would work just fine. When you are
using DEBUG, however, a different instruction is needed
to stop the program. You are using DEBUG to control the
computer. When your assembly-language routine is finished,
control of the computer must be returned to DEBUG. DOS
(the computer’s disk operating system) has a routine which
will do this. This routine is accessed by executing the
Chapter 18 Arithmetic and Flags 293
INT 20 instruction. For example, the arithmetic program
we’re going to study shortly looks like this:
MOV AL,49
ADD AL,1E
INT 20
Notice the use of INT 20 to stop program execution. There
are a number of these DOS functions which handle the
computer’s housekeeping chores.
The g command is faster than individual t (trace) com¬
mands, and we can tell the computer where to start and
stop, but it has one major disadvantage. When you use the
r (register) command to view the registers after the program
has run, they will have the same values they had in them
before the program was run. This doesn’t give you a chance
to study the registers and flags to learn about how the
program works.
The solution to this problem is breakpoints. A breakpoint
is an address where you want program execution to stop.
A breakpoint is specified as part of the g command. The
difference between using a breakpoint to stop the program
and INT 20 is that, when the breakpoint is reached, all the
registers will be automatically displayed and their contents
will not have been returned to their previous values. This
allows you to see what all the registers and flags look like
at that exact point in the program. For example:
g 0104
tells DEBUG to start program execution at the address
indicated by the instruction pointer and to stop at address
0104. Notice that the instruction at address 0104 will not
be executed. Instructions or data at address 0103 will be
the last that the program will use. After the program stops
at address 0104, the contents of the registers and flags will
be automatically displayed.
The starting and stopping points for program execution
can be combined into one command. For example:
g = 0100 0104
will cause program execution to start at address 0100 and
to stop at address 0104. The contents of the registers and
flags will be automatically displayed.
When you run programs using a breakpoint, you need to
remember that the instruction pointer will not be reset.
Therefore, you’ll have to change it back to the program’s
starting point if you wish to run the program more than
once or specify the starting point in the g command as just
shown.
If you wish, the t (trace) command can still be used to
execute instructions one at a time.
Now let’s try running a short program which will show
you how to use these DEBUG commands and will allow
you to learn about the 8086/8088 ADD instruction.
Addition
Let’s start with a very simple addition program. Figure
18-42 illustrates this type of program.
We have shown the program twice: the first time using
the g command without a breakpoint, showing that the
registers will in fact be the same as before the program was
run, and the second time using the g command with a
breakpoint, showing that the contents of the registers will
reflect how the program alters them. From this point on in
this text we will use a breakpoint to stop program execution.
Being able to see how a program affects the registers is
important since our primary purpose is to explain what the
program has accomplished and how it functions by studying
the registers and flags after it has run.
Pay particular attention to AL and the flags. Notice their
contents both before and after the program is run. You will
And that the accumulator will have the number 67 ]6 in it
(which is the correct answer) and that only the auxiliary
flag will be set.
Let’s look at the flags a little more closely. Examining the
flags from right to left, let’s consider each and why it was
or was not set. Refer to the bottom portion of Fig. 18-42.
There was no carry (NC) because no carry from the 8th
bit to the 9th bit (which doesn’t exist so it goes into the
carry flag) occurred.
The parity was odd (PO) because the answer, 0110 0111 2 ,
has an odd number of Is.
There was an auxiliary carry (AC) because we had a
carry from the 4th bit to the 5th bit. (Information about the
half-carry is useful when dealing with BCD numbers.)
There was no zero (NZ) because the answer wasn’t 0.
The answer was positive or “plus” (PL) because we did
not have a 1 in the 8th bit of the accumulator so the answer
could not have been negative.
Don’t worry about the enable interrupt (El) or auto¬
increment (UP) flags for the moment.
There was no overflow (NV) because we did not exceed
our range for valid 8-bit signed binary numbers +127 to
-128.
In fact, if you compare the state of the flags before the
program was run with the state of the flags after it was run,
only one of them changed. That was the auxiliary carry
(AC) flag.
The Sign Flag
Let’s look at a problem that produces a negative answer.
See Fig. 18-43 at this time.
Notice that this is exactly the same problem as the last
one except that we have changed the first operand, which
used to be 49 16 into C9 16 (— 55 10 if we consider these
numbers to be signed binary numbers). We know that
— 55 10 + 30 10 = -25 10 . Since this is a negative answer,
we know that the sign flag should be set after the program
is run.
294 Digital Computer Electronics
1 1
0100 1001
+ 0001 1110
0110 0111
49i6
73-10
m
O)
+ 30io
67 16
103 10
B>DEBUG
-r
AX=DDD0 BX=0000 CX=DDDD
DS=BFFD ES=BFFD SS=BFFD
BFFD:0100 7420 JZ
-a
BFFD:0100 mov al,<q
BFFD:0102 add al,le
BFFD:0104 int 20
BFFD: 010L
-u 0100 0105
BFFD:D10D
BQ^q
MOV
AL,^q
BFFD:0102
041E
ADD
AL , IE
BFFD : 0104;
CD2D
INT
20
-g
Program terminated normally
-r
AX=0000 BX=0000 CX=D00D DX=0000 SP=FFEE BP=DDD0 SI=DD0D DI=0000
DS^BFFD ES=BFFD SS=BFFD CS=BFFD IP=0100 NV UP El PL NZ NA PO NC
BFFD:DIDO BO^q MOV AL,^q
Program assembled, unassembled, and executed
without using a breakpoint to stop program
(notice that registers have returned to their previous state)
DX=QDDD SP=FFEE BP=0000 SI=0DDD DI=0DDD
CS=BFFD IP=D1DD NV UP El PL NZ NA PO NC
0122
B>DEBUG
-r
AX^OOOO BX=0000 CX=DDQD
DS^BFFD ES=BFFD SS=BFFD
BFFD:7420 JZ
-a
BFFD:0100 mov al,4q
BFFD:0102 add al,le
BFFD:0104 int 20
BFFD:010L
-u 0100 0105
BFFD:0100 B04q
MOV
AL,45
BFFD:0102 041E
ADD
AL , IE
BFFD:0104 CD20
INT
20
-g 0104
AX=00b7 BX=0000 CX=0000 DX=0000 SP=FFEE BP=0000 SI=000D DI=D000
DS=BFFD ES=BFFD SS—BFFD CS=BFFD IP=D104 NV UP El PL NZ AC PO NC
BFFD:0104 CD20 INT 20
Program assembled, unassembled, and executed using a
breakpoint to stop and display contents of registers and flags
(notice that registers have not returned to their previous state)
Fig. 18-42 Simple 8086/8088 addition problem.
DX=0000 SP=FFEE BP=0000 31=0000 DI=0000
CS=flFFD IP=0100 NV UP El PL NZ NA PO NC
0122
Chapter 18 Arithmetic and Flags 295
1 1
110 0
10 0 1
C9ie
-55iq
+ 0 0 0 1
1110
+ lE-ie
+ 30-|o
1110
0 111
E7 16
-25 10
-r
RX=0DD0 BX=000Q
DS=AFFD ES=AFFD
AFFD:Dion Bocq
CX^DDDD
SS=AFFD
MOV
DX=0DD0
CS—AFFD
AL, CS
SP=FFEE
IP=D10D
BP=DDDD SI-DDDD DI=DD00
NV UP El PL NZ NA PO NC
-a
AFFD: mov al/C^
AFFD:D1DE add al,le
AFFD: 01jD4 int ED
AFFDiDlOL
-u DIDO D104
AFFD:01D0 BDC^
AFFD:D1DE D41E
AFFD: D1D4 CDED
MOV AL f C9
ADD AL,IE
INT ED
-g 104
AX=00E7 BX=DOOO CX^ODOO DX=0DQD
DS-AFFD ES=AFFD SS=AFFD CS=AFFD
AFFDldlD A CDED INT ED
SP-FFEE
IP=0104
BP=ODDD SI-DDDd DI=DDOO
NV UP El NG NZ AC PE NC
Fig. 18-43 Simple 8086/8088 addition problem with a
negative answer.
Assemble the program and run it. Observe the contents
of AL and the status register before and after running the
program so that you can compare them. After the program
is run, AL should contain the value E7 16 . The status register
shows that only two flags have changed in exactly the same
way as in the last example. The parity flag indicates even
parity, and we have an auxiliary carry, just like the last
example.
The difference this time is that we have a negative (NG)
answer. This is what we expected to see. The sum of the
addition problem was — 25 10 (E7 16 ). If we assume that our
numbers are 8-bit signed binary numbers, then any number
that has a 1 in the 8th bit is negative. E7 16 has a 1 in the
8th bit. The sign flag simply reflects the state of the most
significant bit (8th or 16th depending on whether we are
using 8-bit or 16-bit numbers).
have a half-carry (AC), we have even parity (PE), and of
course the zero flag indicates that our answer was in fact 0
(ZR). You should be able to look at the problem itself and
at the flags before and after the program was run and be
able to see why the flags have responded the way they
have.
The Parity Flag
The 8086/8088 microprocessor has a parity flag which
simply tells us how many Is are in the accumulator after
an arithmetic or logic operation. Even parity exists when
an even number of Is are in the accumulator. Odd parity
exists when an odd number of Is exist in the accumulator.
Even parity (PE) and odd parity (PO) are indicated in the
flags section of the DEBUG display.
The Zero Flag
Now let’s change the program slightly so that we obtain a
sum of 0. Then we can see how the flags react to this
situation.
Figure 18-44 shows the problem and the program to
solve the problem.
We are again assuming that our numbers are signed
binary numbers. The problem is C9 16 + 37 16 = 00 16 ,
which is — 55 10 + 55 10 = 0 10 . You should go through the
binary addition of these two numbers now before you run
the program. Notice both the answer and the carries. Notice
also that we are using the same program as in the last
example but have changed one of the operands.
We have a carry out of the most-significant bit (CY), we
Overflow Flag
When the overflow flag is set, it tells us that if the numbers
which were just added or subtracted are signed binary
numbers, then the valid range for such numbers has been
exceeded and the result is incorrect. The valid range for
8-bit calculations is +127 to —128. The valid range for
16-bit calculations is +32,767 to —32,768. Let’s modify
our problem to create an overflow.
Figure 18-45 shows our problem and program. Remember
that we are assuming that all values are to be interpreted
as 8-bit signed binary values.
This problem is 123 10 + 111 10 =-First go
through the binary addition and enter the program. Then
write down the values you think will be found in AL and
296 Digital Computer Electronics
1 1111 1111
110 0
100 1 C9 16
-55 10
+ 0011
0 111 + 37 16
+ 55 10
1 0 0 0 0
0 0 0 0 00, 6
°io
-r
RX=D000 BX=0000
CX=0000
DX—0DD0 SP-FFEE
BP=0000 SI=0000
DI=DDDD
DS=AFFD ES=AFFD
SS=flFFD
CS=AFFD IP=0100
NV DP El PL NZ
NA PO NC
flFFD: 0100 7450
JZ
□122
-a
AFFD:0100 raov al,
CS
AFFD:0102 add al.
3?
AFFD:0104 int 50
AFFD: 010L
-u 0100 0104
AFFD:0100 BOCR
MOV
AL, CH
AFFD:0105 043?
ADD
AL , 37
AFFD:0104 CD50
INT
20
-g 104
fiX=0000 BX=0000
CX=DDD0
DX=Q000 SP=FFEE
BP=0000 SI=0000
DI=DDDD
DS=AFFD ES=AFFD
SS=flFFD
CS=flFFD IP=D1D4
NV DP El PL ZR
AC PE CY
AFFD:0104 CD50
INT
20
Fig. 18-44 Simple 8086/8088 addition problem which
produces a sum of 0.
the status register, run the program, and finally note the
final values of AL and the status register.
You should have a sum of EA, 6 in the accumulator and
should find that there has been an auxiliary carry (AC),
that the sign bit indicates that this is a negative number
(NG), and that there has been an overflow (OV). EA 16 is
the correct sum if you are using unsigned binary numbers!
If you interpret EA I6 as a signed binary number, it has a
value of — 22 10 . This is not the correct answer. We have
exceeded our valid range for 8-bit signed binary numbers.
1111 1111
0 111
10 11 7B 16
123 10
+ 0110
1111 + 6F,g
+ 111,0
1110
10 10 ea, 6
234,o
-r
AX=0000
BX=00Q0
cx^oooo
DX=0000 SP=FFEE
BP=0000
si=oooa
Di=oooa
DS=flFFD
ES=flFFD
SS=AFFD
CS=fiFFD IP=0100
NV UP El
PL NZ
NA PO NC
flFFD:DIDO
7420
JZ
0122
-a
flFFD: 0100
mov al,
7b
flFFD: 0102
add al.
fcf
flFFD:0104
int 20
flFFD:010L
-U 0100 0104
flFFD:
BO? B
MOV
AL, 7B
flFFD:0102
04LF
ADD
AL, LF
flFFD:DICK
CD20
INT
20
-g 104
AX=00EA
BX=0D00
cx^oooo
DX=000Q SP-FFEE
BP=0 000
SI=000D
Di=oaaa
DS=flFFD
ES^flFFD
SS=flFFD
CS = flFFD IP=0104
0V UP El
NG NZ
AC PO NC
AFFD: aim
CD20
INT
20
Fig. 18-45 Simple 8086/8088 addition problem which
produces an overflow.
Chapter 18 Arithmetic and Flags 297
0 10 0
0 111
BCD
47io
0 10 0
0 1 1 1 2
47 16
+ 0011
0 110
BCD
+ 36-jo
+ 0011
0 1 1 0 2
+ 36 16
10 0 0
0 0 11
BCD
o
co
00
, 0 111
1 1 0 1 2
7D 16
Decimal (BCD) Binary
This
is not the same as
this!
-r
AX=DODD BX=ODOO
DS=flFFD ES=AFFD
flFFD:0100 74E0
CX=0000 DX=DDDD SP^FFEE BP=0000 SI=ODDD DI=0000
SS=flFFD CS=flFFD IP=D1D0 NV UP El PL NZ N A PO NC
JZ DIES
-a
flFFD: 0100
flFFDiOlOE
flFFD: 0104
flFFD : 0107
flFFD: OlOfl
flFFD:OIOS
flFFD: 010D
flFFD: Q1QF
flFFD:Dill
flFFD:0110
flFFD:0115
flFFD:011b
6FFD:0117
flFFD:01IB
flFFD : dliID
mov al,47
add al,3L
mov [01A0],al
pushf
pop bx
mov [01Al],bx
mov al,47
add al,3L
daa
mov [01A3]/al
pushf
pop bx
mov [01A4],bx
int E0
1st operand (binary)
add Ed/ put sum in al (binary)
store sum
copy flags
retrieve flags
store flags
1st operand
add Ed, put sum in al (binary)
convert sum to BCD
store BCD sum
copy flags
retrieve flags
store flags
return to DEBUG
-g 011b
AX~0 0 A3 BX = FAT2
DS=AFFD ES=AFFD
flFFD:011B CDE0
CX-OOOD DX-Q000 SP=FFEE BP=0000 SI=0000 DI=D00D
SS=flFFD CS=flFFD IP-QllB OV UP El NG NZ AC P0 NC
INT E0
-d 01A0 01AF
flFFD:01A0 7D 0L FE S3 TE FA 73 LE-74 LI 7fl ED G5 7E LF }. yntax erro
Fig. 18-46 Binary vs. BCD addition.
Decimal Addition
Because of differences in the way binary and decimal
numbers round, and because numeric output to humans is
usually decimal, it is sometimes helpful to do arithmetic
calculations by using decimal numbers rather than binary
numbers. Actually, true decimal numbers are not used.
Rather a mixture of binary and decimal, called binary-
coded decimal, is used. (The method used to create BCD
numbers is covered in Chap. 1, and they have been discussed
subsequently. You should review that section of Chap. 1
now if you are unsure of what BCD numbers are or how
they are formed.)
One of the problems involved in using BCD numbers is
that as the binary nibbles are added invalid results are
sometimes obtained.
Most microprocessors have an instruction called decimal
adjust (or something similar). This instruction changes the
number in the accumulator to what it would be if the last
two numbers operated on had been packed BCD numbers
instead of binary numbers.
Let’s look at an example. Figure 18-46 is a decimal
addition problem which is compared to the binary version
of the same problem.
Notice first the difference between BCD and binary
addition. BCD addition is not at all the same as binary
addition. BCD is decimal addition using 4 bits to represent
each decimal digit.
The program shown in Fig. 18-46 will help you understand
the difference between binary and BCD addition (and
subtraction). This program does the addition problem twice,
once using binary numbers and once using BCD numbers.
The result of the binary addition is stored in memory
location 01A0 I6 , and the resulting flags in locations 01A1, 6
and 01A2 16 . The result of the BCD addition is stored in
location 01A3 16 , and the resulting flags in locations 01A4 !6
and 01A5 16 . Assemble and run this program to see whether
you obtain the same results. When we ran the program we
found the following:
location 01A0 16 = binary sum = 7D
location 01A1 16 = binary flags (low byte) = 06
298 Digital Computer Electronics
Fig. 18-47 8086/8088 flag chart.
location 01A2 16 — binary flags (high byte) = F2
location 01A3 16 = BCD sum = 83
location 01A4 16 = BCD flags (low byte) = 92
location 01A5 16 = BCD flags (high byte) = FA
Figure 18-47 will help you understand what the stored
flag values mean.
When you store the value of the flag register (status
register), you can place the hexadecimal values on the chart
in Fig. 18-47. You can then convert the hexadecimal values
to binary values and look in the 0 row or 1 row to see what
conditions the flags indicate existed at a certain point in the
program.
In this example we have placed the values of the flags
after the binary addition in Fig. 18-48.
First notice that we have reversed the order of the
hexadecimal values for the flags. The PUSHF instruction
pushes the current value of the flags onto the stack. The
POP BX then retrieves that value into the BX register. At
this point the values are still in their correct order. In fact,
if you will refer to Fig. 18-46, those areas have been printed
in bold to illustrate this fact. Notice that BX contains
FA92 16 . Look at memory locations 01A4 16 and 01A5 16 .
Notice that those 2 bytes have been reversed. PUSH and
POP instructions do not reverse the bytes. However, MOV
instructions do. The MOV instruction places the data into
memory in a low-byte/high-byte order, which has the effect
of reversing the bytes when the memory locations are
examined.
The binary addition problem produced an answer of 7D, 6 ,
as we expected. There were no carries or overflows, and
we have even parity. These conditions are shown in bold
type in Fig. 18-48.
The BCD addition produced a sum of 83 BCD , as we
thought it would. Don’t be concerned about the flags at this
point. Simply notice that they are different. They reflect
Fig. 18-48 Conditions after the binary addition.
Chapter 18 Arithmetic and Flags 299
Fig. 18-49 Conditions after the BCD addition.
conditions that result from the conversion from binary to
BCD (see Fig. 18-49.)
Subtraction
Subtraction is the opposite of addition. All the flags operate
the same except the carry flag. After subtraction, the carry
flag indicates whether a borrow has occurred or not. You
can think of it as a “borrow” flag. A 1 in the carry flag
position indicates that a borrow from a nonexistent bit was
required to do the subtraction. A 0 indicates that no borrow
was required.
Figure 18-50 illustrates how to write a program to do
single-precision subtraction.
You should assemble and run this program. When we
did, we found that the result in AL was FF. We also found
that there was an overflow, the answer was negative, and
there was a carry. The answer was negative because the
8th bit of the answer is a 1, which indicates an 8-bit
negative signed binary number. There was an overflow
because 7F 16 = 127 1 0 and 80 16 = — 128 IO ; therefore
127
-(-128 )
255
and 255 10 is outside the valid range for 8-bit signed binary
numbers. (The valid range is + 127 I0 to -128 10 .) There
was a carry because a borrow from a 9th bit was needed
to complete the subtraction.
Multiplication
The 8-bit microprocessors featured in this text do not have
a multiply instruction. To multiply, the programmer must
use many instructions to accomplish what the 8086/8088
does with just one instruction.
There are several ways the 8086/8088 can multiply. It
can multiply signed binary numbers by using the Integer
MULtiply (IMUL) instruction. It can also multiply unsigned
binary numbers by using the MULtiply (MUL) instruction.
Whether signed or unsigned, the 8086/8088 can multiply
two 8-bit binary numbers to produce a 16-bit answer or
two 16-bit binary numbers to produce a 32-bit answer.
AX=aDDD BX=DDDD CX=00DD DX=00DD SP=379E BP=D0DD SI=DDDD DI=DDDD
DS=qCQL. ES=9CflL SS=qCflb CS=9CflL IP=D1DD NV UP El PL NZ NA PO NC
SCflbrDIDD flBFE MOV DI,SI
-a
RCatrOlOO mov al,7f
9Cflt:D105 sub al,A0
qCAb:0104 int 20
qCAbrDlOb
-g 010<
AX=0QFF BX=000D CX=00D0 DX=0000 SP=3?qE BP=0000 SI=0000 DI=0000
Ds=qcab Es=qcAt ss^qcat cs=qcat, ip=oio< ov up ei ng nz na pe cy
qcat:0104 CD20 INT 2D
;load first operand
;subtract second operand
;return control to DEBUG
Fig. 18-50 Subtraction.
300 Digital Computer Electronics
IE
X FC
1 DBB
B>DEBUG
-r
AX=0000 BX=0000 CX=0000 DX=0000 SP=3?qE BP=0000 SI^OOOO DI=ODOO
DS=qCAb ES^qCAb SS=SCflb CS=qCAb IP=01D0 NV UP El PL NZ NA PO NC
qCAbrOlOO ABFE MOV DI,SI
-a
RCAb:0100
qCflt:0102
qCAb:0104
qCflb: 010 b
qCAb:D10A
-g 10b
AX=1DA A BX^OOFC CX=0000 DX-0000 SP=3?SE BP=OODO 31=0000 DI=DDDD
DS=qC6 b- ES=q efiL S3 =qCflb - CS=qCflb - IP=010b -&V—UP El P L NZ NA PO CY
qCAb:010b CDED INT ED
mov
al / IE
;first operand
mov
bl, FC
;second operand
mul
bl
;mul automatics
int
E0
;return control
(no immediate mode allowed)
lly uses value value in al or ax
to DEBUG
Fig. 18-51 Eight-bit multiplication on the 8086/8088.
If two 8-bit numbers are to be multiplied, one of them
must be placed in AL. The other can be in a register or
memory location. Immediate mode multiplication is not
allowed . That is, you cannot do this:
mov al,lE
mul al,FC
int 20
You cannot specify a number to be multiplied by the number
in AL in the instruction itself. You must move it to a
register or memory location.
The problem IE x FC and the program to solve it are
shown in Fig. 18-51.
FFE 2
X 12 D 3
Notice that we moved the first number into AL and then
the second into BL. We then only needed to say
mul bl
because the microprocessor assumes that the first number
is in AL. The answer is placed in AX.
The only two flags that have any meaning after a MUL
or 1MUL instruction are the overflow and carry flags. If
the upper byte of the answer (AH) is 00, then both of these
flags will be cleared. Any other result in AH causes both
of these flags to be set. Since the value in AH in our
example is not 0, both the overflow and carry flags are set
after the program is run.
Figure 18-52 illustrates a 16-bit multiplication problem.
12 DOCB 46
B>DEBUG
-r
AX=0000 BX-DDDD
DS=9BBE ES=qBBF
-a
SBBF:DlDb
SBBF:DIDA
C3
mov
ax,
FFEE
mov
bx,
12D3
mul
bx
int
E0
CX=0000
SS^qBBF
RET
DX-0000 SP=4<0E BP=0000 SI=0000 DI=0000
CS=SBBF IP=0100 NV UP El PL NZ NA PO NC
;first lb-bit operand
;second lb-bit operand
;multiply ax by bx
;return control to DEBUG
-g 10 A
AX = CB 4 b
DS=qBBF
BX=1ED3
ES=SBBF
qBBF: 010 A CDE0
CX=0000 DX = 12D0 SP^^iOE
SS=RBBF CS=qBBF IP=010A
INT ED
BP—0000 SI=0000 DI=000D
OV UP El PL NZ NA PO CY
Fig. 18-52 Sixteen-bit multiplication on the 8086/8088.
Chapter 18 Arithmetic and Flags 301
58 remainder 2
FB ) 564A
B>DEBUG
-r
RX=DC1DD BX=0000 CX=DDOO DX=OOOD SP=4SDE
DS==IBRE ES=qBA2 SS= C 1BR5 CS=qBAE IP=01D0
^BRE:ElEtRlDS RND [D5A1],SP
-a
3BA2: Q1DD
mov
ax f
5L4 A
;dividend
(IL-bits
3BAE : D1D3
mov
bl /
EB
;divisor
(fl-bits)
3BA2:D1D5
div
bl
;divide ax by bl
3BAE:DliD?
int
2D
jreturn control to
3BA2:DlQq
-g ID?
Ax=oasa
BX=DDEB
CX=DDD0
DX=DDDD
SP=< 5DE
DS^RBAE!
E5=3BAE
SS=RBA2
CS=qBA2
IP=D1D7
3BAE:□!□?
CD20
INT 2D
BP=DDDD SI=DDDD DI=0DDD
NV UP El PL NZ NA P0 NC
DS : □ 5A1=E C 103
DEBUG
BP=DDDO SI=DDDD DI=DDDD
NV UP El PL NZ AC PO CY
Fig. 18-53 A 16-bit number divided by an 8-bit number
using the 8086/8088 DIV instruction.
The process is similar to that used in 8-bit multiplication.
You use 16-bit registers instead of 8-bit, and the answer is
32-bits wide! The upper 2 bytes (16 bits) are found in DX,
and the lower 2 bytes are found in AX.
The flags respond as they do for 8-bit multiplication.
Division
We handle division in a way which is similar to, yet the
opposite of, the way multiplication is handled.
When division is done, the dividend (number to be
divided) must be twice as wide (16 or 32 bits) as the divisor
(8 or 16 bits). Figure 18-53 illustrates how a 16-bit dividend
is divided by an 8-bit divisor.
Notice how we again moved the operands into a register
to prepare for the actual division. Our 16-bit dividend
(564A 16 ) was placed in AX and the 8-bit divisor (FB 16 ) was
placed in BL. Notice that we simply say
div bl
and the microprocessor assumes we are dividing BL into
AX.
Now notice how the answer is displayed. The answer is
58 16 , with a remainder of 2 16 . The quotient appears in the
lower half of AX (AL), and the remainder is in the upper
half of AX (AH). This is where the answer to a problem
which divides a 16-bit number by an 8-bit number is found.
Figure 18-54 illustrates how to divide a 32-bit binary
number by a 16-bit binary number.
To perform this type of problem, you must place the
most significant 16 bits of the dividend in register DX.
Place the least significant 16 bits of the dividend in register
AX. Then place the 16-bit divisor in BX or CX. After the
division the answer (quotient) will be found in register AX,
with the remainder in register DX.
GLOSSARY
ASCII American Standard Code for Information Inter¬
change. A binary code in which letters of the alphabet,
numbers, punctuation, and certain control characters are
represented.
BCD (binary-coded decimal) Decimal numbers which
replace each decimal digit with its 4-bit binary equivalent.
multiple-precision number A number which is composed
of more than one binary word.
single-precision number A number which is composed
of one binary word. In an 8-bit microprocessor this is an
8-bit number, and in a 16-bit microprocessor this is a 16-
bit number.
302 Digital Computer Electronics
_ 789A remainder 8
45CE } 20E28DF4
B>DEBUG
-r
AX=ODOQ BX=DDDD CX=DDDD DX=ODDD SP=4ECE BP=DDDD SI=DDDD DI=DDDD
DS=RB13 ES^BBIB SS=9B13 CS=SB13 IP=Q1DD NV UP El PL NZ NA PO NC
3B13: D1DD 7420 JZ 0125
-a
SB13:0100 mov dx,5DE5
3B13 : EI103 mov ax,flDE4
3B13:DIDO mov bx,45CE
3B13:0103 div bx
3B13:010B int 50
3B13:01DD
;most significant word of dividend
;least significant word of dividend
;divisor
;divide DXAX register pair by BX
;return control to DEBUG
-g 10b
AX = 7 AT A BX=4SCE CX=0D0 D DX = D006 SP=4ECE BP=DGD0 SI=DDD 0 DI=DDDD
DS=9B1.3 ES=qB13 SS^GBIB CS=RB13 IP=D10B NV UP El NG NZ AC PE CY
3B13:010B CD50 INT 50
Fig. 18-54 A 32-bit number divided by a 16-bit number
using the 8086/8088 microprocessor.
SELF-TESTING REVIEW
Read each of the following and provide the missing words.
Answers appear at the beginning of the next question.
1. Binary-coded decimal numbers are decimal numbers
in which each digit is represented by its_-
_equivalent.
2. (4-bit binary) What is the binary value for 10 lo ?
3. {1010 2 ) When 8-bit binary numbers are added, the
carry flag indicates when a carry from the
_bit to the_bit has oc¬
curred.
4. (8th, 9th) When 8-bit binary numbers are added, the
half-carry flag indicates when a carry from the
_bit to the_bit has oc¬
curred.
5. (4th, 5th) A number which can be represented by 1
byte is called a_-precision number.
6. (single) After subtraction, the carry flag indicates
whether or not a_has occurred.
7. (borrow) Do the 8-bit microprocessors featured in
this text have multiply or divide instructions?
(No)
PROBLEMS
General
18-1. What two types of information are generated by
a microprocessor during addition?
18-2. What does 1 2 + 1 2 + I 2 = ?
18-3. What is
1010 1110 2
+ 0011 0111 2
18-4. What is
0111 1111 0110 1101
+ 0001 1000 1111 quo
18-5. When we are using all 8 bits to represent the
numbers 1 10 to 255 10 , we refer to these as_
binary numbers.
18-6. When we use 8-bit binary numbers to represent
values from — 128 10 to 3-127 10 , we refer to
these as_binary numbers.
18-7. Find the 8-bit signed binary value for — 100 10 .
18-8. What flag warns the programmer that the last
answer produced exceeds the valid range for
signed binary numbers?
18-9. What flag tells the programmer whether the
number in the accumulator is positive or nega¬
tive?
Chapter 18 Arithmetic and Flags 303
Specific Microprocessor Families
Solve the following problems using the microprocessor of
your choice.
18-10. Write a program which will add the unsigned
binary numbers 67 16 and 23 16 . Determine which
flags are altered by the program and why.
18-11. Write a program which will subtract the signed
binary number 4D 16 from 7F 16 . Determine which
flags are altered by the program and why.
18-12. Write a program which will add the decimal
numbers 40 10 and 52 I0 .
18-13. With your computer or microprocessor trainer
store the unsigned binary numbers 67 16 and 23 16
in two consecutive memory locations. Now write
a program which will find the sum of these two
numbers and store the sum in a free memory
location. (8086/8088 users: To store 67 16 and
23 16 in memory locations use the DEBUG e
(enter) command. For example, typing
-e 0180 67 23 00 00
will enter 67, 23, 00, and 00 into memory loca¬
tions 0180, 0181, 0182, and 0183, respectively.)
304 Digital Computer Electronics
Logical Instructions
This chapter discusses the logical instructions of our featured
microprocessors. These instructions, along with the arith¬
metic and shift and rotate instructions, give us the ability
to alter bits and bytes (data) in a predictable fashion.
You may wish to review logic gates before beginning
this chapter. Microprocessors use logical instructions the
way digital circuits use logic gates.
New Concepts
There are really only four basic logical functions: and, or,
exclusive-or, and not. The nand, nor, exclusive-nor,
and NEGate functions are simply extensions of the four
basic functions.
We will look at each of the basic four plus a couple of
other special instructions some of the microprocessors have.
We will also discuss masking, a primary use of the logical
instructions.
19-1 THE and INSTRUCTION
When we and 2 bits or conditions, we are saying that the
output bit, or condition, is true only if both the input bits,
or conditions, are true. For example, there will be a voltage
at the output of a circuit only if there is voltage at both of
Input
Output
B
A
Y
0
0
0
0
1
0
1
0
0
1
1
1
Fig. 19-1 and truth table.
0110 1110
AND 1 1 0 0 0 1 0 0
0100 0100
Fig.
19-2 ANDing 2 bytes together.
0 AND 0
1 AND 0
1 AND 1
1 AND 0
0 AND 0
1 AND 0
1 AND 1
0 AND 1
is 0
is 0
is 1
is 0
is 0
is 0
is 1
is 0
its inputs. Or, a bit in memory will be 1 only if 2 other
input bits are also 1. Or, a drill will begin to lower only if
the workpiece has been secured and the worker’s hands are
away from the bit.
ANDing Bits
The truth table to and 2 bits, or conditions, is shown in
Fig. 19-1. Notice that the only way to get a 1 out is to put
two Is in.
ANDing Bytes
We can and entire bytes, or words also. We simply apply
the logic shown in the table to each bit. It’s almost like
turning a truth table on its side. For example, a problem in
which we must and 2 bytes is shown in Fig. 19-2.
Notice that we have applied the logic from the and truth
table to each bit. The only Is in the answer are in columns
where both the inputs are also 1.
EXAMPLE 19-1
Solve the following logical problem.
1011 1110 and 0111 0001 is ???? ????
305
SOLUTION
1011 1110
AND 01110001
0011 0000
Masking
A common use of the and instruction is to and bits or
bytes with a mask. A mask allows us to change some bits
in a certain way while allowing others to pass through
unchanged. Look at the example shown in Fig. 19-3.
Notice that the upper nibble of the data byte passed
through the Is of the mask unchanged. However, every bit
of the lower nibble passing through the 0s was cleared.
ANDing a mask to data can be viewed in either of two
ways. You can say that selected data bits pass through
unchanged while all others are cleared. Or, you can say
that selected data bits are cleared while others pass through
unaltered.
EXAMPLE 19-2
Devise a mask which when ANDed to an 8-bit data byte
will clear all bits except the’first 2 (2 least significant bits).
SOLUTION
0000 0011
For example:
11111111 data
and 0000 0011 <— mask
0000 0011
Input
Output
B
A
Y
0
0
0
0
1
1
1
0
1
1
1
1
Fig. 19-4 or truth table.
look at it another way, the only way to get a 0 out is to
have 0s at both inputs.
ORing Bytes
We can or entire bytes, or words also. We simply apply
the logic shown in the table to each bit. For example, the
same problem used in the previous section, but now ORing
the 2 bytes together, is shown in Fig. 19-5.
Notice that we have used the logic from the or truth
table and applied it to each bit. The only 0s in the answer
are in columns where both the inputs are also 0.
EXAMPLE 19-3
Solve the following logical problem.
1011 1110 or 0111 0001 is ???? ????
SOLUTION
1011 1110
OR 0111 0001
mi mi
19-2 THE or INSTRUCTION
When we or 2 bits or conditions, we are saying that the
output will be true (or 1) if either of the input bits or
conditions is true (1) or if both of the input bits or conditions
are true.
ORing Bits
The truth table to OR 2 bits or conditions is shown in Fig.
19-4.
Notice that you get a 1 out if any input is a 1. Or, to
Masking
A common use of the or instruction is to or bits or bytes
with a mask. A mask allows some bits to pass through
unchanged while others are changed in a certain way. Look
at the example shown in Fig. 19-6.
0 110 1110
OR 1 1 0 0 0 1 0 0
1110 1110
0 AND 0 is 0
1 AND 0 is 1
1 AND 1 is 1
1 AND 0 is 1
0 AND 0 is 0
1 AND 0 is 1
1 AND 1 is 1
0 AND 1 is 1
AND
10 0 1
1111
10 0 1
0 0 0 0
• data
■ mask
1001 0000
Fig. 19-3 Using the and instruction to mask bits.
Fig. 19-5 ORing two bytes together.
306 Digital Computer Electronics
1 0 0 1 1 0 0 1 --data
OR 1 1 1 1 0 0 0 0 -*-mask
1111 1001
Fig. 19-6 Using the or instruction to mask bits.
Notice that the lower nibble of the data byte passing
through the 0s of the mask was unchanged while every bit
of the upper nibble passing through the Is was set.
ORing a mask to data can be viewed in either of two
ways. You can allow selected data bits to pass through
unchanged while all others are set. Or, you can allow
selected data bits to be set while all others pass through
unaltered.
EXAMPLE 19-4
Devise a mask which when ORed to an 8-bit data byte will
set all bits except the first 2 (2 least significant bits).
SOLUTION
mi noo
For example:
0000 0000 <— data
or 1111 1100 <— mask
1111 1100
0 110 1110
XOR 1 1 0 0 0 1 0 0
1010 1010
0 and 0 is 0
1 AND 0 is 1
1 AND 1 is 0
1 AND 0 is 1
0 AND 0 is 0
1 AND 0 is 1
1 AND 1 is 0
0 AND 1 is 1
Fig. 19-8 xoRing two bytes together.
Notice that the only way to get a 1 out is to have one,
but not both, of the inputs be a 1.
xoRing Bytes
We can xor entire bytes, or words also. We simply apply
the logic shown in the table to each bit. For example, the
same problem shown in the previous two sections, but this
time xoRing the 2 bytes, is shown in Fig. 19-8.
Notice that we have used the logic from the xor truth
table and applied it to each bit. The only Is in the answer
are in columns where one but not both the inputs are 1.
EXAMPLE 19-5
Solve the following logical problem.
19-3 THE EXCLUSIVE-OR (EOR, XOR)
INSTRUCTION
When we exclusively or (eor, xor) 2 bits or conditions,
we are saying that the output bit or condition is true only
if one or the other of the input bits or conditions is true,
but not both. For example, there will be a voltage at the
output of a circuit only if there is voltage at one or the
other, but not both, of its inputs.
xoRing Bits
The truth table to xor 2 bits or conditions is shown in Fig.
19-7.
Input
Output
B
A
Y
0
0
0
0
1
1
1
0
1
1
1
0
Fig. 19-7 xor truth table.
1011 1110 XOR 0111 0001 is ???? ????
SOLUTION
1011 1110
xor 0111 0001
noo mi
Masking
A common use of the xor instruction is to xor bits or
bytes with a mask. A mask allows some bits to pass through
unchanged while others are changed in a certain way. Look
at the example shown in Fig. 19-9.
Notice that the lower nibble of the data byte passed
through the 0s of the mask unchanged while every bit of
the upper nibble passing through the Is was inverted.
xoRing a mask to data can be viewed in either of two
ways. You can allow selected data bits to pass through
1 0 0 1 1 0 0 1 -data
xor 1 1 1 1 0 0 0 0 -mask
0110 1001
Fig. 19-9 Using the xor instruction to mask bits.
Chapter 19 Logical Instructions 307
unchanged while all others are inverted. Or, you can allow
selected data bits to be inverted while all others pass through
unaltered.
EXAMPLE 19-6
Devise a mask which when xoRed to an 8-bit data byte
will invert all bits except the first 2 (2 least significant bits).
SOLUTION
mi lioo
For example:
mi mi
<—data
xor nil noo
<— mask
0000 0011
19-4 THE not INSTRUCTION
When we not or invert bits or conditions, we are saying
that the output bit or condition is the opposite of the input
bit or condition. For example, if there is a voltage at the
input, there will not be one at the output; or if there is no
voltage at the input, there will be a voltage at the output.
NOT-ing (Inverting) Bits
The truth table for the not function is shown in Fig.
19-10.
Input
Output
A
Y
0
1
1
0
Fig. 19-10 not truth table.
NOT-ing (Inverting) Bytes
We can not or invert entire bytes, or words also. We
simply apply the logic shown in the table to each bit. An
example of inverting or complementing a number is shown
in Fig. 19-11.
NOT 1111 0000 is 0000 1111
Fig. 19-11 “NOT-ing” or inverting a binary number.
Notice that we have changed every 0 to a 1 and every 1
to a 0—that is, we have inverted every bit of the byte.
This is the l’s complement of the number.
EXAMPLE 19-7
Solve the following logical problem.
not 1011 1110 is ???? ????
SOLUTION
0100 0001
19-5 THE neg (negATE)
INSTRUCTION
The NEGate instruction finds the 2’s complement of a
number. To find the 2’s complement, we first find the l’s
complement and then add 1. An example is shown in Fig.
19-12.
Specific Microprocessor
Families
Let’s see how these instructions work in the different
microprocessor families.
19-6 6502 FAMILY
The 6502 has three of the instructions discussed in the New
Concepts section of this chapter plus one instruction not
discussed there. These are the and, or, eor, and bit
instructions. Let’s look at each.
The and Instruction
The 6502 and instruction works exactly as described in the
New Concepts section. If we use the same example we
used in Fig. 19-3 in the New Concepts section, we will
find that the 6502 does in fact and bytes as discussed.
Figure 19-13 shows our original problem and solution
plus a 6502 program which solves the problem. After
running this program, you will find that the accumulator
contains 90, 6 . This is exactly what we expected after 99 16
was masked with F0 16 .
1111 0000 - number
0 0 0 0 1 1 1 1 - 1's complement
+_1_ -add 1
0001 0000 -2's complement (original number NEGated)
Fig. 19-12 NEGating a number (2’s complement).
308 Digital Computer Electronics
1 0 0 1 1 0 0 1 --data
and 1 1 1 1 0 0 0 0 -* -mask
1001 0000
0340 AO qq LDA *$qq
0345 30 FO AND #$FO
□ 344 □□ BRK
Fig. 19-13 Using the 6502 and instruction to mask bits.
1 0 0 1 1 0 0 1 --data
OR 1 1 1 1 0 0 0 0 -* -mask
1111 1001
U3AU ar qq lda #$qq
□ 343 00 FO ORA #$FO
3344 00 BRK
Fig. 19-14 Using the 6502 or instruction to mask bits.
If you check the 6502 instruction set, you will find that run the program. We expected the accumulator to have 69 16
the and instruction affects the negative and zero flags. In after EORing.
this case the negative flag is set because the 8th bit of the The eor instruction also affects the negative and zero
accumulator is 1, indicating a 2’s-complement negative flags. This time neither is set; the result is neither negative
number. nor zero.
;load A with 1001 1001
;OR mask
; stop
;load A with 1001 1001
;AND mask
; stop
The or Instruction
The 6502 or instruction also works exactly as described in
the New Concepts section. If we use the example from Fig.
19-6 in the New Concepts section, we find that the 6502
does or bytes as discussed there.
Figure 19-14 shows our original problem and solution
plus a 6502 program which solves the problem. After
entering and running the program, you will find that the
accumulator contains F9 16 . This is the value we expected
the accumulator to have.
The or instruction also affects the negative and zero
flags. You will find that the negative flag is again set
because the 8th bit is 1, indicating a 2’s-complement
negative number.
The eor Instruction
The 6502 eor instruction also works as described in the
New Concepts section. If we use the example from Fig.
19-9 in the New Concepts section, we’ll find that the 6502
does eor bytes as discussed there.
Figure 19-15 shows our original problem and solution
plus a 6502 program which solves the problem. Enter and
The bit Instruction
The bit instruction was not described in the New Concepts
section and is somewhat unusual. Refer to the bit instruction
in the Expanded Table of 6502 Instructions Listed by
Category.
The bit instruction ands a memory location with the
accumulator. However, the result is not stored anywhere.
Neither the accumulator nor the memory location is changed.
If the result of the and is zero, the zero flag is set. If
the result is not zero, the zero flag is not set.
The negative and overflow flags are affected in an unusual
way. The status of the negative and overflow flags is not
determined by the result of the and process but rather is
copied from bits 6 and 7 (7th and 8th bits) of the memory
location.
A program which illustrates the operation of the bit
instruction is shown in Fig. 19-16.
The bit instruction is useful when using the flags to
control branching. You can alter the flags with a logical
condition without actually changing the accumulator or
memory location.
1 0 0 1 1 0 0 1 -data
EOR 1 1 1 1 0 0 0 0 -mask
0110 1001
□ 340 Aq qq LDA #$qq ;load A with 1001 1001
□ 343 40 FO EOR #$F0 ;E0R mask
□ 344 00 BRK ;stop
Fig. 19-15 Using the 6502 eor instruction to mask bits.
Chapter 19 Logical Instructions 309
034D
A3
CO
LDA
#$CO
;load A with
1100 □□□□
□ 342
AD
A0
□ 3
STA
#Q3AD
;store HDD
□□□□ in location
□ 3AD
□ 34 5
Ag
□ □
LDA
#$□□
; load A with
□□□□ □□□□
□ 34 7
EC
A0
□ 3
BIT
$□3 AD
;AND A (□□□□
□□□□) with D34D
(HDD
□ 34 A
□ □
BRK
; stop
After running the program:
negative flag = 1/ overflow flag = 1, break flag = 1/ zero flag = 1, accumulator = □□
Fig. 19-16 Using the 6502 bit instruction.
19-7 6800/6808 FAMILY
The 6800/6808 has all the instructions discussed in the New
Concepts Section plus one instruction not discussed there.
These are the anda/andb, oraa/orab, eora/eorb, bita/
bitb, com/coma/comb, and neg/nega/negb instructions.
Notice that each instruction has a mnemonic for each
accumulator and that some (com and neg) have one for
memory locations also. Let’s look at each.
Clearing the Flags
The 6800/6808 examples which follow cover both the result
of the logical operation and the condition of the flags. It is
helpful to be able to clear the flags before the examples are
run so that the previous condition of the flags is not confused
with the effect the example had on the flags.
Place the following program in an area of memory you
do not plan to use for the examples. Then run this program
to clear both accumulators and all flags before running each
example program.
xxxx 4F
CLRA
;clear A
xxxx 5F
CLRB
; clear B
xxxx 06
TAP
;clear flags
xxxx 3E
WAI
;stop
The anda/andb Instruction
The 6800/6808 and instruction works exactly as described
in the New Concepts section. If we use the same example
we discussed in the New Concepts section (Fig. 19-3), we
will find that the 6800/6808 does in fact and bytes as
discussed.
Figure 19-17 shows our original problem and solution
plus a 6800/6808 program which solves the problem. If
you will notice the condition of the accumulator and flags
after running this program, you will find that the accumulator
contains 90, 6 as we expected.
If you check the 6800/6808 instruction set, you will find
that the and instruction affects the negative and zero flags.
(The overflow flag is always cleared.) In this case the
negative flag is set because the 8th bit of the accumulator
is 1, indicating a 2’s-complement negative number. (It is
assumed that the flags just discussed were cleared before
the program was started.)
The oraa/orab Instruction
The 6800/6808 oraa/orab instruction also works exactly
as described in the New Concepts section. We’ll use the
example found in Fig. 19-6 in the New Concepts section.
Figure 19-18 shows our original problem and solution
plus a 6800/6808 program which solves the problem. After
entering and running the program, you will find that the
accumulator contains F9 16 . This is what we expected.
The or instruction also affects the negative and zero
flags. (The overflow flag is always cleared.) The negative
flag is again set because the 8th bit of A is 1, indicating a
2’s-complement negative number.
The eora/eorb Instruction
Let’s look at the 6800/6808 eora/eorb instruction. If we
use the example from Fig. 19-9 in the New Concepts
section, we will find that the 6800/6808 does eor bytes as
discussed.
Figure 19-19 shows our original problem and solution
from Fig. 19-9 plus a 6800/6808 program which solves the
problem. Enter and run the program. You will find that the
accumulator contains 69, 6 .
The eor instruction also affects the negative and zero
flags. (The overflow flag is always cleared.) In this case
neither was set; the result is neither negative nor zero.
1 0 0 1 1 0 0 1 -data
and 1 1 1 1 0 0 0 0 -mask
1001 0000
□□□□ al gg
□ □□e A4 FO
□ □□4 3E
ldaa #$gg
ANDA #$F0
WAI
Fig. 19-17 Using the 6800/6808 and instruction to mask bits.
;load A with 1QD1
;AND mask
; stop
310 Digital Computer Electronics
1 0 0 1 1 0 0 1 -data
OR 1 1 1 1 0 0 0 0 -mask
1111 1001
□□□□ at sr ldaa #$qq
□ 002 aA FO ORAA *$FO
0004 3E WAI
Fig. 19-18 Using the 6800/6808 oraa/orab instruction to
mask bits.
;load A with 1001 1001
;0R mask
; stop
1 0 0 1 1 0 0 1 -data
XOR 1 1 1 1 0 0 0 0 -mask
0110 1001
□ooo at qq ldaa #$qq
□002 aa FO EORA #$FO
UUUA 3E WAI
Fig. 19-19 Using the 6800/6808 eora/eorb instruction to
mask bits.
;load A with 1001 1001
;EOR mask
; stop
The bita/bitb Instruction
The bit instruction was not described in the New Concepts
section. Refer to the bit instruction in the Expanded Table
of 6800/6808 Instructions Listed by Category.
The bit instruction ands a memory location with one of
the accumulators. However, the result is not stored any¬
where. Neither the accumulator nor the memory location
is changed.
If the result of the and is zero, the zero flag is set. If
the result is not zero, the zero flag is not set. If the result
of the and is a negative 2’s-complement number, the
negative flag is set. Regardless of the result, the overflow
flag is cleared.
A program which illustrates the operation of the bit
instruction is shown in Fig. 19-20.
The bit instruction is useful when the flags are used to
control branching. You can alter the flags with a logical
condition without actually changing the accumulator or
memory location.
The com/coma/comb Instruction
The complement instruction (com/coma/comb) finds the
l’s complement of each bit in the byte that’s being
complemented. That is, it inverts every bit in the byte. An
example problem and a 6800/6808 program to solve the
problem are shown in Fig. 19-21.
After running this program, you should find 55 16 in A
and the carry flag set.
Referring to the 6800/6808 instruction set, you will find
that the com instructions affect the negative and zero flags.
In addition, they always clear the overflow flag and set the
carry flag. In this example the negative flag is clear because
the result (55 ]6 ) is not a negative number. Nor is it zero;
therefore the zero flag is not set. The overflow flag is
automatically cleared, and the carry flag automatically set.
The NEG/NEGA/NEGB Instruction
The neg/nega/negb (negate) instructions are very similar
to the com/coma/comb instructions. The neg instructions,
□000 at FF
□□□2 as co
UUUA 3E
LDAA #$FF
BITA #$co
WAI
;load A with 1111 1111
;AND A with 1100 0000
; stop
After running the program:
A = FF flags = 001000
Fig. 19-20 Using the 6800/6808 bita instruction.
10 10 10 10 -original number (AA-| 6 )
0 10 1 0 10 1 -1's complement of original number (55 16 )
□ □□□ at, AA LDAA *$AA
0002 A 3 COMA
0003 3E WAI
Fig. 19-21 Using the 6800/6808 com/coma/comb
instructions.
;load A with 1010 1010
;invert all bits (0101 0101) (55h)
; stop
Chapter 19 Logical Instructions 311
-*-original number (95 -iq)
-Vs complement
-plus 1
-2's complement (-95 -iq)
;load A with DID! 1111
; E 1 s complement of A
; stop
0 10 1
1111
10 10
0 0 0 0
+
1
10 10
0 0 0 1
□□□□
AG 5F
LDAA#$5F
□ DDE
A 0
NEGA
□ □□3
3E
WAI
Fig. 19-22 Using the 6800/6808 neg/nega/NEGB
instructions.
however, find the 2’s complement of a number instead of
the l’s complement. Recall that the 2’s complement is
found by first finding the l’s complement and then add¬
ing 1.
Figure 19-22 shows an example problem and program
using the negate instruction.
After running the program you will have Al 16 in the
accumulator and the negative and carry flags set.
The negative flag is set because the 8th bit of A is set
indicating a 2’s-complement negative number.
Why the carry flag is set requires a little explanation.
One way to look at a 2’s-complement number is to view it
as a l’s-complement number with 1 added to it. There is
another point of view, however.
Remember how we described the creation of negative
numbers as being like rotating an odometer backward? The
original number used in this example is 0101 1111 2 , which
is 95 10 . If we rotate our odometer backward from 00 by 95
places, we will arrive at the binary number 1010 0001.
Rotating the odometer backward from 00 is the same as
subtracting from 00.
Now think about subtracting a number from 00. Would
a borrow from the carry bit be required? Yes, because any
number is larger than 0 and a borrow would be required to
subtract it from 00. To subtract 95 from 00 requires a
borrow, which is why the carry flag is set.
If you think about it, the carry flag would have been set
regardless of what number we would have used. When you
use the NEG instruction, the only time the carry flag won’t
be set is if you negate the number 00, because subtracting
00 from 00 does not require a borrow.
19-8 8080/8085/Z80 FAMILY
The 8080/8085/Z80 has four of the instructions discussed
in the New Concepts section, although one has a different
name. These are the and (ana [and]), or (ora [OR]), xor
(xra [XOR]), and not (CMA [CPL]) instructions. (Z80 mne¬
monics are shown in brackets.) Let’s look at each.
The ana [and] Instruction
The 8080/8085/Z80 ana [and] instruction works as de¬
scribed in the New Concepts section. If we use the example
from Fig. 19-3 in the New Concepts section, we will find
that the 8080/8085/Z80 does in fact and bytes as discussed.
Figure 19-23 shows our original problem and solution
plus an 8080/8085/Z80 program which solves the problem.
If you will notice the condition of the accumulator and flags
after running this program, you will find that the accumulator
has a 90 16 in it as we expected. The sign, auxiliary carry,
and parity flags will be set.
If you check the 8085/Z80 instruction set, you will find
that the and instruction affects the sign, zero, and parity
1 0 0 1 1 0 0 1 -data
and 1111 0000 -*-mask
1001 0000
A0A5 program
1 ACID
3E
qq
m vi A,qq
; load A with
1001
1DD1
1A02
0G
FO
MVI B f FO
;load B with
mask
(1111
DDDD)
1AD4
AQ
ANA B
;AND A with
mask
IADS
?G
HLT
; stop
ZAD ;
program
1 ADO
3E
qq
ld A,qq
;load A with
1DD1
1D01
1ADE
□ G
FO
LD B,FO
;load B with
mask
(1111
0000 )
iack
AD
AND B
; AND A with
mask
1AD5
7G
HALT
; stop
Fig. 19-23 Using the 8080/8085/Z80 ana [and] instruction
to mask bits.
312 Digital Computer Electronics
10 0 1 1
OR 1111 0
1111 1
fiOflB
program
1600
3E 33
MVI A f 33
IflO 3
0b FO
MVI B,FO
1A04
B0
ORA B
1605
7b
HLT
ZAO
program
1600
3E 33
LD A,33
1603
0b FO
LD B,FO
1A 04
B0
OR B
1605
7b
HALT
Fig. 19-24 Using the 8085/Z80 or instruction to mask bits.
flags. The and instruction always sets the auxiliary carry
[half-carry] flag and always clears the carry flag. (Note: If
you are using an 8080 microprocessor, the auxiliary flag
works a little differently than it does in the 8085 and Z80.
Check the Expanded Table.)
The sign flag is set because this is a negative number.
The zero flag is clear because the result was not zero. The
auxiliary flag is set because it is always set by this instruction.
The parity flag is set because there are an even number of
Is. And the carry flag is clear because that flag is always
cleared by the and instruction.
The ora [or] Instruction
The 8085/Z80 or instruction also works as described in the
New Concepts section. We’ll use the example from Fig.
19-6 in the New Concepts section.
Figure 19-24 shows our original problem and solution
plus an 8085/Z80 program which solves the problem. After
entering and running the program, you will find that the
0 1 -*-data
0 0 -*-mask
0 1
;load A with number (1001 1001)
;load B with mask (1111 □□□□)
;0R number and mask
; stop
;load A with number (!□□! !□□!)
;load B with mask (1111 □□□□)
;OR number and mask
; stop
accumulator has a value of F9 16 and that the sign and parity
flags have been set.
We expected the accumulator to have F9 16 after ORing.
The or instruction set the sign flag because F9 16 is a 2’s-
complement negative number. The parity flag is set because
there are an even number of Is in F9 16 (1111 1001 2 ). The
zero flag is clear because the result (F9 16 ) is not zero. All
other flags are automatically cleared by the or instruction.
The xra [xor] Instruction
Let’s look at the 8085/Z80 xor instruction. If we use the
example from Fig. 19-9 in the New Concepts section, we’ll
find that the 8085/Z80 does xor bytes as discussed.
Figure 19-25 shows our original problem and solution
plus an 8085/Z80 program which solves the problem. After
entering and running the program, you will find that the
accumulator contains 69 16 and that only the parity flag is
set. Examine the figure and the Expanded Table to find
why this is so.
1 0 0 1 1 0 0 1 -data
xor 1 1 1 1 0 0 0 0 -mask
0110 1001
6065
program
1 ADD
3E 33
MVI A,33
; load
A with
number (10D1 1001)
1603
0b FO
MVI B,FO
; load
B with
mask (1111 0000)
1604
Afl
XRA B
; XOR
number
with mask
1605
7b
HLT
; stop
zao
program
1600
3E 33
LD A,33
; load
A with
number (1001 1D01)
1603
0b FO
LD B,FO
; load
B with
mask (1111 0000)
1604
Afl
XOR B
; XOR
number
with mask
1605
7b
HALT
; stop
Fig. 19-25 Using the 8085/Z80 xor instruction to mask
bits.
Chapter 19 Logical Instructions 313
NOT 1010 1010 is 0101 0101
A0A5
program
1A 0 0
BE AA
MVI A , A A
;load A
with 1010
1010
1A0E
2F
CMA
;invert
all bits
(0101
0101)
(S5h)
1A03
7b
HLT
; stop
ZAO
program
1A 00
BE AA
LD A,AA
;load A
with 1010
1010
1A 02
2F
CPL
;invert
all bits
(0101
0101)
(5Sh)
1A03
7b
HALT
; stop
Fig. 19-26 Using the 8085/Z80 complement instruction.
The cma [cpl] Instruction
The complement instruction (cma [CPL]) finds the l’s
complement of each bit in the byte that’s being comple¬
mented. That is, it inverts every bit in the byte. An example
problem and an 8085/Z80 program to solve the problem
are shown in Fig. 19-26.
After running this program, you should find the value
55 16 in A. If you are using an 8085, you will find that none
of the flags has been affected or changed by the CMA
instruction. If you are using a Z80, you will find that the
half-carry and parity flags have been set. The Z80 always
sets these two flags after the CPL instruction.
19-3 in the New Concepts section, we find that the 8086/
8088 does in fact and bytes as discussed.
Figure 19-27 shows our original problem and solution
plus an 8086/8088 program which solves the problem.
Notice the condition of the accumulator and flags before
and after running this program.
After masking 99 16 with F0 16 , 90 16 is exactly what we
expected. If you check the 8086/8088 instruction set, you
will find that the and instruction affects the sign, zero, and
parity flags. The overflow and carry flags are always cleared
(NV, NC), and the auxiliary flag is undefined. In this case
the sign flag is set (NG) because the 8th bit of the accumulator
is 1, indicating a 2’s-complement negative number.
19-9 8086/8088 FAMILY
The 8086/8088 has all the instructions discussed in the New
Concepts section. These include the and, or, xor, not,
and neg instructions. Let’s look at each.
The and Instruction
The 8086/8088 and instruction works as described in the
New Concepts section. If we use the example from Fig.
The or Instruction
The 8086/8088 OR instruction also works as described
earlier in the New Concepts section. We’ll use the example
from Fig. 19-6 in the New Concepts section.
Figure 19-28 shows our original problem and solution
plus an 8086/8088 program which solves the problem. After
entering and running the program, you will find that AL
has a value of F9, 6 as we expected.
1 0 0 1 1 0 0 1 -data
and 1 1 1 1 0 0 0 0 -mask
1001 0000
ax=oodo bx=oooo cx^ooaa dx=oooo sp=f?be bp=dddd si^odoo di^oooo
ds^boaa es=roaa ss^qoaA cs=qoAA ip=qioo nv up ei pl nz na po nc
qoa a:B ern mov AL,qq
-a 100
R0AA:010D MOV AL,qq
BOA A : 0102 AND AL/EO
BOflAiOlO^ INT 50
B0AA:010b
-g U1UA
AX=00B0 BX=0000 CX=0000 DX=0□□□ SP=F75E BP=D00D SI=DDDD DI=0000
DS=B0AA ES=B0AA SS=B0AA CS=BDAA IP=01Q A NV UP EI NG NZ NA PE NC
BOAAiDIO A CD20 INT ED
;load A with 1001 1001
; AND A with mask
;return control to DEBUG
Fig. 19-27 Using the 8086/8088 and instruction to mask bits.
314 Digital Computer Electronics
1001 1001
OR 1 1 1 1 0 0 0 0
1111 1001
data
mask
-r
flX=DD00 BX=0D00 CX=D00D DX=0CD0 SP=Ffl3E BP=0DDD SI=0DDD DI=DDDD
DS=qo7c Es=qa?c ss=qo?c cs=qa?c ip=oiod nv up ei pl nz nr po nc
3D7C:BDqq MOV AL,qq
-a
^□?C:D1DQ MOV AL,99
907C:D1CIE OR AL,F0
907C:D1D4 INT ao
9D7C:Dint
-g IUA
flX=DOFq BX=DDDD CX=0000 DX=D0DD SP=Ffl3E BP=000D SI =0000 DI=DD00
DS=qD7C ES=q07C SS=qD7C CS=qD?C IP= 01 CK NV UP EI NG NZ NR PE NC
C \U?C:UIUA CDED INT EG
;load A with number (IDDl !□□!)
;OR number and mask
; stop
Fig. 19-28 Using the 8086/8088 or instruction to mask bits.
The or instruction also affects certain flags. The sign
flag is set (NG) because this is a 2’s-complement negative
number. The overflow flag is cleared (NV) because the or
instruction always clears it. The carry flag is also cleared
for the same reason (NC). We have even parity (PE), and
the result is not zero (NZ).
The xor Instruction
Let’s look at the 8086/8088 xor instruction using the
example from Fig. 19-9 in the New Concepts section.
Figure 19-29 shows our original problem and solution
plus an 8086/8088 program which solves the problem. After
entering and running the program, you will find that AL
has a value of 69 16 . This is what we expected.
The xor instruction affects the flags in the same way as
the OR and and instructions. Examine the flags that are
affected by this instruction to see whether they responded
as you expected.
The not Instruction
The invert instruction (NOT) finds the l’s complement of
each bit in the byte that’s being complemented. That is, it
inverts every bit in the byte. An example problem and an
8086/8088 program to solve the problem are shown in Fig.
19-30.
After running this program, you should find the value
55 16 in AL. And since this instruction does not affect any
1 0 0 1 1 0 0 1 -data
XOR 1 1 1 1 0 0 0 0 -mask
0110 1001
-r
AX^DDDD BX=DDCm
DS =c i □ 9F ES=909F
9D9F:7<ED
-a
9D9F:MOV AL
909F:D1DE XOR AL
9G9F:DICK INT EG
9D9F
-g IDA
AX=00L9 BX=DG0Q CX^DDOD DX=0GGD SP=FLGE BP-DGGD SI=000D DI=DG0G
DS=9G9F ES=9G9F SS=9G9F CS=9D9F IP=G1D< NV UP EI PL NZ NA PE NC
9D9F:Q1D4 CDED INT ED
Fig. 19-29 Using the 8086/8088 xor instruction to mask bits.
CX=DDDD DX=DDG0 SP=FLDE BP=00D0 SI=DDDD DI=DDDD
SS=9D9F CS=909F ip=dioo nv up EI PL nz na po nc
JZ D1EE
;load A with number (1D01 IDDl)
;XOR number with mask (1111 □□□□)
;return control to DEBUG
Chapter 19 Logical Instructions 31 5
NOT 10 10 10 10 is 0 10 1 0 10 1
-r
ax=oooo bx=oooo cx=oooo dx=oooq sp=fbie bp=oooo si=dodo di=dddd
DS-HOAE ES=H0AE SS=H0AE CS=R0AE IP=0100 NV UP El PL NZ NA PO NC
HOAE:0100 74E0 JZ 01EE
-a
HOAE:0100 MOV AL, A A
HOAE:010E NOT AL
H0AE:D1Q< INT ED
HOAE:DIDO
-g 104
AX=0055 BX=DDDD CX=OODO DX^OOOO SP-F51E BP=OOOD SI=0000 DI=0000
DS=SOAE ES=SOAE SS=HOAE CS^HOAE IP=0104 NV UP El PL NZ NA PO NC
HDAE:DICK CDED INT EO
Fig. 19-30 Using the 8086/8088 not instruction.
;load A with number (1010 1D1D)
;invert all bits of number (D1D1 D1D1) (55h)
;return control to DEBUG
flags, you should find that every flag is exactly as it was
before the instruction was executed.
The neg Instruction
The neg (negate) instruction is very similar to the not
instruction. The neg instruction, however, finds the 2’s
complement instead of the l’s complement. Recall that the
2’s complement is found by first finding the l’s complement
and then adding 1.
Figure 19-31 shows an example problem and program
using the negate instruction. After running the program,
you will have Al 16 in the accumulator.
Notice also that the sign flag is set (NG) as well as the
carry flag (CY).
The negative flag is set because the 8th bit of AL is set
indicating a 2’s-complement negative number.
Why the carry flag is set requires a little explanation.
One way to look at a 2’s-complement number is to view it
as a l’s-complement number with 1 added to it. There is
another point of view, however.
Remember how we described the creation of negative
numbers as being like rotating an odometer backward? The
original number we used in this example is 0101 111 1 2 ,
which is 95 10 . If we rotate our odometer backward from
00 by 95 places, we will arrive at the binary number 1010
0001. Rotating the odometer backward from 00 is the same
as subtracting from 00.
Now think about subtracting a number from 00. Would
a borrow from the carry bit be required? Yes, because any
0 10 1 1111 -original number (95qo)
1 0 1 0 0 0 0 0 -Vs complement
+ 1 -plus 1
1 0 1 0 0 0 0 1 -2's complement (-95io)
-r
AX-0000 BX=D0DD
DS=R0EA ES=H0EA
R0EA:0100 74E0
-a
HDEA:0100 MOV AL
HDE A : OIjOE NEG AL
HOEA:0104 INT E0
HOEA:Q1QL
-g 104
AX=00A1 BX=0000 CX=0000 DX=0000 SP^FISE BP=0000 SI=0000 DI=0000
DS=H0EA ES=H0EA SS^HOEA CS^ROEA IP=D104 NV UP El NG NZ NA PO CY
HOEA:0104 CDE0 INT E0
Fig. 19-31 Using the 8086/8088 neg instruction.
CX^OOOO DX=00□0 SP=F15E BP=0000 SI=0000 DI^OOOO
SS^HOEA CS=H0EA IP=0100 NV UP El PL NZ NA PO NC
JZ 01EE
,5F ;load A with number (0101 1111)
;find E*s complement of number in AL
;return control to DEBUG
316 Digital Computer Electronics
number is larger than 00 and a borrow would be required
to subtract it from 00. To subtract 95 from 00 required a
borrow, which is why the carry flag was set.
If y<> u think about it, the carry flag would have been set
regardless of what number we used. When you use the neg
instruction, the only time the carry flag won’t be set is
when you negate the number 00 itself, because subtracting
00 from 00 does not require a borrow.
SELF-TESTING REVIEW
Read each of the following and provide the missing words.
Answers appear at the beginning of the next question.
1. Name the four basic logical instructions.
2. (and, or, xor, and NOT) When we and 2 bits, we
are saying that the output bit will be 1 only if both
inputs bits are_
3. (1) A mask allows us to change some bits in a byte
while allowing others to pass through_
4. ( unchanged ) When we_two bits together,
we are saying that the output bit will be a 1 if either
or both of the input bits are 1.
5. (OR) When ORing bits, the only way to get a_
out is to have both inputs be_
6. (0 y 0) When using the XOR instruction, if both input
bits are the same, the output bit will be a_(0, 1).
7. (0) When xoRing bits, the only way to get a 1 out is
for (both, either)-of the input bits to be
a 1.
8. (either) When we not or invert bits, we are saying
that the output bit is the_(same as, oppo¬
site of) the input bit.
9. (opposite of) To NEGate a number is to find the 2’s
complement of the number. This involves finding the
-and then adding_
(1' s complement, l)
PROBLEMS
General
19-1. 1011 1100
AND 0110 1Q1Q
19-2. Devise a mask which, used with the and in¬
struction, would allow all bits to pass through
unaltered except the most significant. The most
significant should be cleared.
19-3. 01101110
or 0011 0101
19-4. Devise a mask which, used with the or instruc¬
tion, would allow all bits to pass through unal¬
tered except the most significant. The most sig¬
nificant should be set.
19-5. 0101 0101
xor oon mi
19-6. Devise a mask which, used with the xor in¬
struction, would invert all bits except the 2 most
significant. The 2 most significant should pass
through unaltered.
19-7. Invert the binary number 0111 1011.
19-8. Negate the number 0110 1110 (8-bit answer).
Specific Microprocessor Families
Solve the following problems by using the microprocessor
of your choice.
19-9. Write and run a program which will place the
binary number 1100 1001 in the accumulator and
then and it with the binary number 1011 1101.
19-10. Write and run a program which will place the
number CC 16 in the accumulator and then use
the or instruction to set every bit in the lower
nibble of the accumulator while allowing every
bit in the upper nibble to remain unchanged.
Advanced Problems
Solve the following problems using the microprocessor of
your choice.
19-11. Write and run a program which will;
a. place 45 16 in the accumulator.
b. add 2F, 6 to the number in the accumulator.
c. use a mask to invert every bit in the lower
nibble of the sum yet not alter the upper
nibble.
d. subtract 0001 1100 2 from the last result.
e. create another mask (using the AND instruc¬
tion) which will allow all bits of the last result
to remain unchanged except the least signifi¬
cant 3 bits which should be cleared.
Chapter 19 Logical Instructions 317
19-12. ASCII values for the digits 0 through 9 are
shown below.
0 00110000
1 00110001
2 00110010
3 0011 0011
4 00110100
5 0011 0101
6 0011 0110
7 00110111
8 0011 1000
9 00111001
It may sometimes be desirable to change an ASCII number
into its binary equivalent. For this problem, write and run
a program which uses a mask to change the ASCII value
for 5 into its binary equivalent.
318
Digital Computer Electronics
Shift and Rotate Instructions
In this chapter we’ll study two relatively straightforward
concepts— shifting and rotating. Shifts and rotates can be
used for parallel-to-serial data conversion, serial-to-parallel
data conversion, multiplication, division, and other tasks.
New Concepts _
The concepts of rotating and shifting are quite simple. Let’s
look at each in its “generic” form; then, as usual, we’ll
study each microprocessor family. The microprocessors’
instructions which perform each of these functions differ
only slightly.
20-1 ROTATING
Rotating bits is exactly what it sounds like—moving bits
in a circle. Let’s look at a typical rotate instruction to start
our discussion. Figure 20-1 shows a typical rotate left
instruction.
Figure 20-2 illustrates each step involved when a bit is
rotated eight times. Figure 20-2 first shows an 8-bit accu¬
mulator and carry flag. The accumulator is loaded with the
value 01 16 , and the carry flag is cleared. Next, a sequence
of eight rotate lefts are performed. Notice that the 1 just
keeps moving 1 bit position each time.
Microprocessors can rotate toward the right or left. Some
also have other forms of rotation in which the carry flag is
involved in a slightly different way. We’ll look at those in
the Specific Microprocessor Families section.
20-2 SHIFTING
Shifting, like rotating, is exactly what it sounds like. And,
like rotating, shifting can be toward the left or right. The
-7 ... 0 -
-► C -
Fig. 20-1 Typical rotate left instruction.
8080/8085 is the only microprocessor family being studied
in this text which does not have shift instructions. The
8080/8085 has only rotate instructions.
Let’s look first at the concept of shifting toward the left.
Figure 20-3 illustrates what is known as a logical shift left
or arithmetic shift left . Bits are shifted one at a time toward
the left, with the bit in the 8th position (bit 7) being shifted
into the carry flag.
Two things should be noticed which make this instruction
different from the rotate instruction. First, the contents of
the carry flag do not “wrap around” to bit 0; its contents
are simply lost. Second, 0s are automatically shifted into
bit 0 (least significant bit).
Look at Fig. 20-4 for an example of this type of shifting.
We have loaded the value 99 16 into the accumulator and
have cleared the carry flag. Next we execute eight consec¬
utive shifts. Notice that
1. 0s keep coming in from the left.
2. The bits in the accumulator keep shifting 1 bit to the
left.
3. The bits shift from the most significant bit of the
accumulator into the carry flag.
4. Bits shifting out of the carry flag are lost.
Shifts to the right are possible also. Figure 20-5 shows
a typical logical shift to the right. This is basically the
opposite of the shift left.
Figure 20-6 shows a typical arithmetic shift to the right.
The arithmetic shift right instruction duplicates whatever
was in the most significant bit and moves copies of it to
the right with each shift.
319
C -7 ... 0 - 0
Fig. 20-3 Typical arithmetic shift left or logical shift left.
_ Accumulator
0
Carry flag
Fig. 20-2 Rotating left eight times.
20-3 AN EXAMPLE
Let’s look at an example which uses the rotate instruction.
It is often useful to be able to move a nibble of data from
one part of a register to the other.
For example, let’s say we wanted to clear every bit in
320 Digital Computer Electronics
Fig. 20-6 Typical arithmetic shift right.
the upper nibble of the accumulator and then move every
bit of the lower nibble into the upper nibble. There are no
instructions for moving a nibble from one place to another.
The rotate instruction can help accomplish this, though.
Figure 20-7 shows our problem.
First, we’ll use a mask to clear out the upper bit. This
is shown in Fig. 20-8.
Next we’ll clear the carry bit (since this bit will be rotated
into the least significant bit of the lower nibble). Then we’ll
rotate toward the left four times. This is shown in Fig.
20-9.
If you compare the final value in Fig. 20-9 with our
initial value in Fig. 20-9, you’ll see that we have moved
the lower nibble into the upper nibble, which is what we
wanted to do.
Upper nibble
Lower nibble
110 0
110 1
Fig. 20-7 Situation in which we want to clear the upper
nibble and then move every bit of the lower nibble into the
upper nibble.
1100 1101
AND 0000 1111
0000 1101
Fig. 20-8 Using the and instruction to mask off the upper
nibble.
Initial value
After 1 rotate to the left
After 2 rotates to the left
After 3 rotates to the left
Final value—after 4 rotates to
the left
Fig. 20-9 Using the rotate through carry instruction to
move the lower nibble into the upper nibble.
Specific Microprocessor
Families
□ □□1
0340
. org
f $D34□
□ □□2
□ 340
;
□ □03
034 0
1A
CLC
□ □□4
0341
A3 01
LDA
#$□1
□ □□5
0343
2 A
ROL
A
□ 00b
□ 344
3 A
ROL
A
□ □□7
0345
3 A
ROL
A
□ □□A
□ 34 0
3 A
ROL
A
□ DDR
0347
3 A
ROL
A
□ 010
034 A
3 A
ROL
A
□ Oil
0343
3 A
ROL
A
0013
□ 34 A
3 A
ROL
A
0013
□ 34B
00
BRK
0014
034C
1
0015
034C
.end
Fig. 20-11 6502 program which rotates left eight times.
The ROR (ROtate Right) instruction uses the same
concept as the ROL instruction and affects flags in the same
way. It simply rotates the bits in the opposite direction.
Figure 20-11 shows a program which clears the carry
flag and rotates the accumulator toward the left eight times.
If you have a monitor which can single-step (“walk”)
through the program, cause it to do so, and check the
accumulator and carry flag after each step.
If you cannot single-step, then use a break (BRK)
instruction after each ROL instruction so that you can
observe the movement of the bits in the accumulator. After
each BRK you will have to make your trainer or computer
begin program execution again at the next ROL instruction
to see the shifting action continue.
Let’s study the shift and rotate instructions for each of our
microprocessor families.
20-4 6502 FAMILY
The 6502 has two rotate instructions and two shift instruc¬
tions. Let’s look at them.
The ROL and ROR Instructions
The 6502 ROL (ROtate Left) instruction works as described
in the New Concepts section of this chapter and as shown
in Fig. 20-10. Figure 20-10 is taken from the Rotate and
Shift Instructions section of the Expanded Table of 6502
Instructions Listed by Category.
In Fig. 20-10 the “7 . . . 0” represents bits 0 through
7 of a byte. Here the “byte” is the value in the accumulator.
The “C” represents the carry bit of the status register.
The ROL instruction causes each bit to move to the left
one place. Bit 7 moves into the carry bit (flag), and the
carry bit moves into bit 0.
- 7 ... 0 -
-► C -
Fig. 20-10 6502 ROtate Left instruction.
The ASL and LSR Instructions
The 6502 shift instructions also work as described in the
New Concepts section of this chapter. The Arithmetic Shift
Left instruction is shown in Fig. 20-12.
C -7 ... 0 - 0
Fig. 20-12 6502 arithmetic shift left instruction.
The Logical Shift Right instruction is shown in Fig.
20-13. Both are quite simple.
0 -► 7 ... 0-► C
Fig. 20-13 6502 logical shift right instruction.
An Example
Let’s look at the same example which was used in the New
Concepts section. Remember, our objective was to clear
the upper nibble and then to move the lower nibble of the
accumulator into the upper nibble of the accumulator.
Figure 20-14 shows our original problem.
Upper nibble
Lower nibble
110 0
110 1
Fig. 20-14 Situation in which wc want to clear the upper
nibble and then move every bit of the lower nibble into the
upper nibble.
Chapter 20 Shift and Rotate Instructions 321
□□□1
□ 34 □
-org $0340
□ DDE
□ 340
*
ano3
□ 34 □
E3 OF
AND #$OF
□ □□4
□ 34E
1A
CLC
□ □□5
□ 343
E A
ROL A
□ □□b
□ 344
E A
ROL A
□□□?
□ 345
EA
ROL A
□ □DA
□ 34b
EA
ROL A
□ □03
□ 347
□ □
BRK
□ □ID
□ 34 A
*
□ □11
□ 3 4 A
.end
Fig. 20-15 6502 program which clears the upper nibble of
the accumulator and then moves the lower nibble into the
upper nibble.
A 6502 program which can solve this problem is shown
in Fig. 20-15. Manually place the initial value of CD 16 in
the accumulator before running the program. After the
program is run, you should find the value D0 16 in the
accumulator.
20-5 6800/6808 FAMILY
The 6800/6808 has two rotate instructions and three shift
instructions.
The ROL/ROLA/ROLB and ROR/RORA/RORB
Instructions
The 6800/6808 ROL/ROLA/ROLB instructions work as
described in the New Concepts section and as shown in
Fig. 20-16. Figure 20-16 is taken from the Rotate and Shift
Instructions section of the Expanded Table of 6800/6808
Instructions Listed by Category.
In Fig. 20-16 the “7 . . . 0” represents bits 0 through
7 of a byte. In this case the “byte” is the value in a
memory location, accumulator A, or accumulator B. The
“C” represents the carry bit of the status register.
The ROL/ROLA/ROLB instructions cause each bit to
move to the left one place. Bit 7 moves into the carry bit
(flag), and the carry bit moves into bit 0.
The ROR/RORA/RORB (ROtate Right) instructions use
the same concept as the ROL/ROLA/ROLB instructions
and affect flags in the same way. They simply rotate the
bits in the opposite direction.
Figure 20-17 shows a program which clears the carry
flag and rotates accumulator A toward the left eight times.
- 7 ... 0 -
-► C -
Fig. 20-16 6800/6808 ROL/ROLA/ROLB instructions.
;mask off upper nibble
;clear the carry flag
;rotate left four times
□ □□1
□ □□□
. org
$□□□□
□ □□E
□ □□□
»
□ □□3
□ □□□
□ C
CLC
□ □□4
□ □□1
Ab □!
LD A A
& $ □ 1
□ □□5
□ □□3
43
ROLA
□ □□b
□ □□4
43
R0LA
□ □□?
□ □□5
43
ROLA
□ □□A
□ □□b
43
ROLA
□ □□3
□ □□?
43
ROLA
□ □!□
□ □□A
43
ROLA
□ □11
□ □□3
43
ROLA
□ □IE
□ □□A
43
ROLA
□ 013
□ □□B
3E
WAI
□ 014
□ □□C
»
□ □15
□ □□C
. end
Fig. 20-17 6800/6808 program which rotates left eight
times.
If you have a monitor which can single-step (“walk”)
through the program, cause it to do so and check the
accumulator and carry flag after each step.
The ASL/ASLA/ASLB, ASR/ASRA/ASRB, and
LSR/LSRA/LSRB Instructions
The 6800/6808 shift instructions also work as described in
the New Concepts section of this chapter. The Arithmetic
Shift Left instruction is shown in Fig. 20-18.
The Arithmetric Shift Right instruction is shown in Fig.
20-19. The Logical Shift Right instruction is shown in Fig.
20-20. All are quite simple.
C -7 ... 0 - 0
Fig. 20-18 6800/6808 arithmetic shift left instruction.
I-► 7...0-► C
Fig. 20-19 6800/6808 arithmetic shift right instruction.
0 -► 7 ... 0-► C
Fig. 20-20 6800/6808 logical shift right instruction.
322 Digital Computer Electronics
7 . . . 0
An Example
Let’s look at the same example which was used in the New
Concepts section. Remember, our objective was to clear
the upper nibble and then to move the lower nibble of the
accumulator into the upper nibble of the accumulator.
Figure 20-21 shows our original problem.
Upper nibble
Lower nibble
110 0
110 1
Fig. 20-21 Situation in which we want to clear the upper
nibble and then move every bit of the lower nibble into the
upper nibble.
A 6800/6808 program which can solve this problem is
shown in Fig. 20-22. Manually place the initial value of
CD i6 in the accumulator before running the program. After
the program is run, you should find the value D0 I6 in the
accumulator.
20-6 8080/8085/Z80 FAMILY
The 8080 and 8085 have four rotate instructions and no
shift instructions. We will place the Z80 form of the
instructions in square brackets. (The Z80 does have several
multibyte shift instructions which we will not study at this
time because the 8080 and 8085 do not share these
instructions.)
The RAL [RLA] and RAR [RRA] Instructions
The 8080/8085/Z80 RAL [RLA] (Rotate A Left [Rotate
Left A] instructions work as described in the New Concepts
section and as shown in Fig. 20-23. Figure 20-23 is taken
from the Rotate and Shift Instructions section of the
Expanded Table of 8080/8085/Z80 Instructions Listed by
Category.
In Fig. 20-23 the “7 . . . 0” represents bits 0 through
7 of a byte. In this case the “byte” is the value in the
accumulator. The “C” represents the carry bit of the status
register.
i-c-1
Fig. 20-23 The 8080/8085/Z80 RAL [RLA] instruction.
The RAL [RLA] instruction causes each bit to move to
the left one place. Bit 7 moves into the carry bit (flag), and
the carry bit moves into bit 0.
The RAR [RRA] instruction uses the same concept as
the RAL [RLA] instruction and affects flags in the same
way. It simply rotates the bits in the opposite direction.
Figure 20-24 shows a program which clears the carry
flag and rotates the accumulator toward the left eight times.
If you have a monitor which can single-step (“walk”)
through the program, cause it to do so and check the
accumulator and carry flag after each step.
The RLC [RLCA] and RRC [RRCA] Instructions
The RLC [RLCA] (Rotate Left with Carry [Rotate Left
with Carry A]) and RRC [RRCA] (Rotate Right with Carry
[Rotate Right with Carry A]) instructions work just a little
differently from the other rotate instructions we have
discussed. The RLC [RLCA] instruction is shown in Fig.
20-25.
The RRC [RRCA] instruction is shown in Fig. 20-26.
In the case of the RLC [RLCA] instruction, all bits in
the accumulator move toward the left. The bit rotating out
of bit 7 goes into the carry flag and around into bit 0 of
the accumulator.
In the case of the RRC [RRCA] instruction, all bits in
the accumulator move toward the right. The bit rotating
out of bit 0 goes into the carry flag and around into bit 7
of the accumulator.
An Example
Let’s look at the same example which was used in the New
Concepts section. Remember, our objective was to clear
the upper nibble and then to move the lower nibble of the
accumulator into the upper nibble of the accumulator.
Figure 20-27 shows our original problem.
□ □□1
□ □□□
. org
$□□□0
□ □□a
□ □□□
;
□ □□3
□ □□□
A4 OF
ANDA
#$0F
□ □□4
□ □□a
OC
CLC
□ □□5
□ □□3
43
ROLA
□ DDE,
□□□<
43
ROLA
□ □□?
□ □□5
43
ROLA
□ □□A
□ □□□
43
ROLA
□ □□q
□ □□?
3E
WAI
□ □ID
□ □□a
t
□ nn
□ □□A
. end
Fig. 20-22 6800/6808 program which moves the lower
nibble of the accumulator into the upper nibble.
;mask off upper nibble
;clear the carry flag
;rotate left four times
Chapter 20 Shift and Rotate Instructions 323
ADAD/ADAB program
ZAD program
□ □□1
IflDD
.org lADDh
□ 001
1 ADD
.org lADDh
□ □□3
1ADD
j
□ DDE
1 ADD
;
□ □□3
IflDD
3E □!
MVI A,D1H
DDD3
1 ADD
BE D1
LD A,D1H
uuua
1AD3
1?
RAL
UUUA
1A D3
17
RLA
□ □□5
1AD3
17
RAL
□ □□5
1AD3
17
RL A
□ □□b
1AD4
17
RAL
DDDb
1AD4
17
RLA
□ □□7
ians
17
RAL
□ □□7
1AD5
17
RLA
□ □□A
lADb
17
RAL
□ □□A
lADfc
17
RLA
□ □□3
1A 07
17
RAL
□ DDR
1AD7
17
RLA
□ □ID
1ADA
17
RAL
□ □ID
1 AD A
17
RLA
□ nil
iaoq
17
RAL
□ Dll
1 ADR
17
RLA
□ □13
1A DA
7b
HLT
□ □13
1ADA
7b
HALT
□ □13
1A0B
9
□ □13
1ADB
9
uuia
1ADB
. end
uuia
1ADB
. end
Fig. 20-24 8080/8085 and Z80 programs which rotate left eight times.
C —i-7 ... o
Fig. 20-25 8080/8085/Z80 RLC [RLCA] instruction.
I-^ 7...0-r—C
Fig. 20-26 8080/8085/Z80 RRC [RRCA] instruction.
An 8080/8085/Z80 program which can solve this problem
is shown in Fig. 20-28. Manually place the initial value of
CD 16 in the accumulator before running the program. After
the program is run, you should find the value D0 16 in the
accumulator.
Upper nibble
Lower nibble
110 0
110 1
Fig. 20-27 Situation in which we want to clear the upper
nibble and then move every bit of the lower nibble into the
upper nibble.
20-7 8086/8088 FAMILY
The 8086/8088 has four rotate instructions and three shift
instructions. They are discussed starting on the next page.
ADAD/ADA5 p
rogram
□ □□1
1 ADD
.org lADDh
□ □□3
1 ADD
y
□ □□3
IflDD
Eb
OF
ANI DFH
mask off upper nibble
UQUA
1AD3
37
STC
set the carry flag then
□ □□5
1 ADB
3F
CMC
complement it
□ □□b
1AD4
17
RAL
rotate left four times
□ □□7
1AD5
17
RAL
□ □□A
1 ADb
17
RAL
□ □□R
1AD7
17
RAL
□ □ID
1ADA
7b
HLT
□ Dll
1 ADR
>
□ □13
IflDR
. end
ZAD program
□ □□1
IflDD
.org lADDh
□ □□3
IflDD
>
□ □□3
IflDD
Eb
OF
AND DFH
mask off upper nibble
UUUA
1AD3
37
SCF
set the carry flag then
□ □□5
1AD3
3F
CCF
complement it
DDDb
1AD A
17
RLA
rotate left four times
□ □□7
1 ADB
17
RLA
□□□a
IflOb
17
RLA
□ □□R
1AD7
17
RLA
□ □ID
IflDfl
7b
HALT
□ □11
IflDR
>
□ □13
IflDR
. end
Fig. 20-28 8080/8085 and Z80 programs which clear the upper nibble of
the accumulator and then move the lower nibble into the upper nibble.
324 Digital Computer Electronics
The RCL and RCR Instructions
The RCL and RCR instructions work as described in the
New Concepts section of this chapter and as shown in Fig.
20-29. Figure 20-29 is taken from the Rotate and Shift
Instructions section of the Expanded Table of 8086/8088
Instructions Listed by Category.
In Fig. 20-29 the “MSB . . . LSB” represents bits 0
- -MSB ... LSB -*-1
-*- C-
Fig. 20-29 The 8086/8088 RCL and RCR instructions.
through 7 of a byte or bits 0 through 15 of a word. The
“C” represents the carry bit of the status register.
The RCL instruction causes each bit to move to the left
one place. The MSB moves into the carry bit (flag), and
the carry bit moves into the LSB.
The RCR instruction uses the same concept as the RCL
instruction and affects flags in the same way. It simply
rotates the bits in the opposite direction.
Figure 20-30 shows a program which clears the carry
flag and rotates AL toward the left eight times. We then
single-step through the program. Follow each step and pay
particular attention to AL and the carry flag.
C>DEBUG
-r
AX=DQDD
BX=0QDD
CX=DDDD
DX=00D0
SP=FFEE
D S=7 7 SB
ES=7?5B
SS=7 7 5B
BS=775B
IP=D1DD
77 SB:DIDO
74E0
JZ
□ 1EE
-a
775B:
CLC
775B:0101
MOV AL,
□ 1
77 SB:D103
RCL AL,
1
77SB:0105
RCL AL,
1
775B:D1D7
RCL AL,
1
775B:010S
RCL AL,
1
775B:Q10B
RCL AL,
1
775B:D10D
RCL AL,
X
775B:D1DF
RCL AL,
1
775B :0111
RCL AL,
1
77SB:D113
INT E0
77SB:0115
-r
AX=DDQ0 :
BX=DD0D
CX=00D0
DX=DD0D
SP=FFEE
DS=77SB
ES=77 SB
SS-775B
CS—77 5B
IP
775B:
Ffl
CLC
-t
AX=D0DD 1
BX=0DD0
CX=D000
DX=DD00
SP^FFEE
DS=775B ES=775B
SS=775B
CS=77 SB
IP=D1D1
77SB:Q101
BDD1
MOV
AL,
□ 1
-t
AX=0DD1 BX=00D0
CX=DDD0
DX=00DD
SP=FFEE
DS=775B ES=775B
SS=7 7 SB
CS=77 SB
IP=D103
77 SB:D1D3
DDD0
RCL
AL,
1
-t
AX=0DDE BX=acma
CX=D0D0
DX=DDD0
SP=FFEE
DS=775B ES=775B
SS=775B
CS—77 SB
IP=D1D5
7? SB:D1D5
DDD0
RCL
AL,
X
-t
ax=oooz Bx=oaaa
CX=DDDD
DX=0DD0
SP=FFEE
DS=77 SB ES=7?5B
SS=7 7 SB
CS=77 SB
IP=D1D7
77SB :D1D7
DDDD
RCL
AL,
1
-t
AX=000fl BX=0Q00
CX=DDD0
DX=DDD0
SP=FFEE
DS=775B ES=775B
SS=77 SB
CS=77SB
ip^axos
77 SB:DIOR
DDD0
RCL
AL,
X
-t
BP=D000 SI=D0DD DI=D0Q0
NV UP El PL NZ. N'A PQ NC.
BP=D000 SI=000D DI=0000
NV OP El PL NZ NA PO NC
BP=Q0DD SI=0D00 DI=D00D
NV UP El PL NZ NA PO NC
BP=D0D0 SI=0000 DI=00D0
NV UP El PL NZ NA PO NC
BP=D000 SI=0D00 DI=0000
NV UP El PL NZ NA PO NC
BP=ODD0 SI=D000 DI=00D0
NV UP El PL NZ NA PO NC
BP=[]000 SI=00DD DI=0000
NV UP El PL NZ NA PO NC
Fig. 20-30 8086/8088 RCL instruction.
Chapter 20 Shift and Rotate Instructions 325
AX=DD1D BX=DOOO
DS=775B ES=775B
775B:D1DB DDDD
-t
RX=DDED BX=DDOD
DS=77 SB ES=77SB
775B:D1DD DDDD
-t
AX-DD4D BX=OOOD
DS=77SB ES=775B
77SB:DIOF DODD
-t
AX=DDflO BX=ODDO
DS=775B ES=775B
77SB:Dill DDDD
-t
AX=OOOD BX=DDOD
DS=77SB ES=77BB
775B:D113 CD2D
-t
Fig. 20-30 (cont.)
CX=00DQ DX=DDDD SP=FFEE
SS=775B CS=77SB IP=D1DB
RCL AL/1
CX=DDDD DX=DDDD SP—FFEE
SS=775B CS=77SB IP=01DD
RCL AL 1 1
CX=00Q0 DX=DDDD SP-FFEE
SS=775B CS=77SB IP=D1DF
RCL AL/1
CX=D0DD DX=DD□□ SP=FFEE
SS=77SB CS=775B IP=D111
RCL AL/1
CX=DDD0 DX=DDDD SP=FFEE
SS=775B CS=7?5B IP=D113
INT 20
BP=D0DD SI=DODO DI=ODDD
NV UP El PL NZ NA PO NC
BP=DDDD SI=D000 DI=DDDD
NV UP El PL NZ NA PO NC
BP=00D0 SI^DDDD DI=ODDD
NV UP El PL NZ NA PO NC
BP-DDDD SI=DDDD DI=DDDD
OV UP El PL NZ NA PO NC
BP=DDD0 SI=00DD DI=DDDD
OV UP El PL NZ NA PO CY
The ROL and ROR Instructions
The ROL (ROtate Left) and ROR (ROtate Right) instruc¬
tions work just a little differently from the other rotate
instructions we have discussed. The ROL instruction is
shown in Fig. 20-31.
The ROR instruction is shown in Fig. 20-32.
The drawings shown here are slightly different from
those shown in the instruction-set description, but if you’ll
look closely, you’ll see that they are really the same.
In the case of the ROL instruction, all bits move toward
the left. The bit rotating out of the MSB goes into the carry
flag and around into the LSB.
In the case of the ROR instruction, all bits move toward
the right. The bit rotating out of the LSB goes into the
carry flag and around into the MSB.
C
MSB ... LSB
Fig. 20-31 8086/8088 ROL instruction.
MSB ... LSB
Fig. 20-32 8086/8088 ROR instruction.
C
20-34. The SHift logical Right instruction is shown in Fig.
20-35. All are quite simple.
C -MSB ... LSB - 0
Fig. 20-33 8086/8088 SAL/SHL instruction.
I-► MSB ... LSB-► C
Fig. 20-34 8086/8088 shift arithmetic right instruction.
0 -► MSB ... LSB-► C
Fig. 20-35 8086/8088 shift logical right instruction.
An Example
Let’s look at the same example which was used in the New
Concepts section. Remember, our objective was to clear
the upper nibble and then to move the lower nibble of AL
into the upper nibble of AL. Figure 20-36 shows our original
problem.
An 8086/8088 program which can solve this problem is
shown in Fig. 20-37. Manually place the initial value of
CD 16 in AL before running the program. After the program
is run, you should find the value D0 16 in AL.
The SAL/SHL, SAR, and SHR Instructions
The 8086/8088 shift instructions work as described in the
New Concepts Section of this chapter. The Shift Arithmetic
Left/SHift logical Left instruction is shown in Fig. 20-33.
The Shift Arithmetic Right instruction is shown in Fig.
Upper nibble
Lower nibble
110 0
110 1
Fig. 20-36 Situation in which we want to clear the upper
nibble and then move every bit of the lower nibble into the
upper nibble.
326 Digital Computer Electronics
ODEBUG
-r
AX=GD00 BX=QDDQ
DS=77BQ ES=77B0
77BD:2ZDF
-rax
AX 0000
: DOcd
CX=0D00 DX=D0DD SP=FFEE
SS=77BD BS=?7B0 IP=D10D
AND AL,GF
BP=00Q0 SI=G00G DI=0G0G
NV UP El PL NZ NA P0 NC
-a
77BD:Q1QD AND AL, OF
77B0:0102 CLC
77B0 :0103 RCL AL,1
77B0:0105 RCL AL,1
77B0:0107 RCL AL,1
77B0:010 C I RCL AL,1
77B0:010B INT 20
77B0: 010D
;mask off upper nibble
;clear the carry flag
rrotate left four times
-r
AX=00CD BX=0000
DS=?7B0 ES=77B0
77BQ:0100 240F
-g 01Gb
CX=0000 DX=0000 SP=FFEE
SS= 77BQ CS=77B0 IP=0100
AND AL,OF
BP=0000 SI=0QQQ DI=GDDG
NV UP El—Pi NZ NA PO NC
AX=D0Dd BX=00QQ
DS=77BD ES=77BD
77BD:D1DB CD2G
CX=000D DX=G0GQ SP=FFEE
SS=??BQ CS=77BG IP=01DB
INT 2D
Fig. 20-37 8086/8088 program which clears the upper nibble
of AL and then moves the lower nibble into the upper
nibble.
BP=00Q0 SI=0000 DI=DD0D
OV UP El PL NZ NA PO NC
SELF-TESTING REVIEW
Read each of the following and provide the missing words.
Answers appear at the beginning of the next question.
1. Does rotating or shifting move the carry bit into one
of the ends of the affected register?_
2. (Rotating) Does rotating or shifting move 0s into one
of the ends of the affected register?_
3. (Shifting) Which of the following instructions dupli¬
cates the current value of the most significant bit and
makes it the new value of the most significant bit?
Rotate right, rotate left, logical shift right, logical
shift left, arithmetic shift right, or arithmetic shift
left?
(Arithmetic shift right)
PROBLEMS
Specific Microprocessor Families
Solve the following problems using the microprocessor of
your choice.
20-1. Write a program which will place the number 34 16
in the accumulator, clear the lower nibble (F),
and then move the upper nibble (C) into the lower
nibble by using a rotate instruction. (Write the
program so that if the carry flag happens to be set
(1) prior to running the program, it will not rotate
the 1 from the carry flag into the upper nibble of
the accumulator.)
20-2. The ASCII value for numbers is the same as the
hex value for numbers except that the ASCII
value has a 3 as a prefix. For example, the ASCII
value for 0 is 30, the ASCII value for 1 is 31, the
ASCII value for 2 is 32, the ASCII value for 3 is
33, and so on.
Chapter 20 Shift and Rotate Instructions 327
Write a program that will place the hex value
23 in the accumulator and will then take the upper
nibble (2h), change it to its ASCII value (32h),
and store it in a memory location. The program
should then take the lower nibble (3h), change it
to its ASCII value (33h), and store it in another
memory location.
Restrictions: (1) You cannot use shift instruc¬
tions (but you may use rotate instructions). (2)
You must make the program so that it will work
for any original value, not just 23h. (That value
was picked randomly.)
Hints: (1) You should store the original value
(23) in a memory location so that you can use it
more than once. (2) You will need to use rotate
instructions, masks, and arithmetic instructions.
(3) You need to set aside three memory locations:
one for the original value (23h), one for the ASCII
value for 2 (32h), and one for the ASCII value
for 3 (33h).
20-3. Place the ASCII value for 8 (38h) in one memory
location and the ASCII value for 9 (39h) in an¬
other location. Then write a program which will
take these two ASCII values, convert them to
their hex equivalents (8h and 9h), and combine
them into a 1-byte, 2-digit, hex number (89h).
20-4. Since the value of a binary digit doubles in value
each time it is moved to the left by one place,
and becomes one-half of its previous value each
time it is moved to the right one place, it is
possible to multiply and divide by shifting/rotat¬
ing.
Write a program which will load the value 1C 16
into the accumulator and multiply it by 8 by
shifting it.
6502, 6800/6808, and 8086/8088 users: You
should use the arithmetic shift left type of instruc¬
tion because it automatically shifts 0s into the
least significant bit.
8086/8088 users: You have an actual multiply
instruction but shouldn’t use it for this program,
since this chapter is intended to help you write
programs using shift and rotate instructions.
Z80 users: You have an arithmetic shift left
type of instruction, but you cannot use it here
because it is not part of the 8080/8085 instruction
subset. Use the following procedure for the 8080/
8085.
8080/8085 users: You do not have any shift
instructions; therefore, you should alternately
clear the carry flag and rotate to achieve an effect
similar to that of the arithmetic shift left instruc¬
tion.
All users: There are other ways to multiply.
This simply illustrates one way, and not necessar¬
ily the best or easiest for your particular micro¬
processor.
328 Digital Computer Electronics
Addressing Modes—II
New Concepts _
In this chapter we’ll study some of the more complex
addressing modes. The different microprocessor families
will show more variation at this point than they did in our
earlier chapter on basic addressing modes.
The 6502 has more addressing modes than any other
8-bit microprocessor. Some are used quite often, but several
are used with only a few instructions. Since the 6502 has
no general-purpose registers and only one accumulator, it
must use memory very often and is therefore said to have
a memory-intensive architecture.
The 6800/6808 has a moderate number of different
addressing modes, and students learning about it should
not have difficulty. The 6800/6808 also lacks general-
purpose registers but does have two accumulators. It is also
considered to have a memory-intensive architecture.
The 8080/8085 has the fewest number of addressing
modes of any of the 8-bit microprocessors. Students will
find it easiest to learn in this respect. (The Z80 has more
addressing modes, but those beyond the ones the 8080/
8085 has will not be studied at this time.) The 8080/8085
has six general-purpose registers in addition to an accu¬
mulator and is therefore said to have a register-intensive
architecture.
The 8086/8088, being a successor to and relative of the
8080/8085, has many general-purpose registers. Because it
is a 16-bit microprocessor, it also has many addressing
modes.
To summarize, the 6502 has 56 different instructions
which use one or more of 13 addressing modes. When you
combine the instructions and addressing modes, you produce
152 different op codes.
The 6800/6808 has 107 different instructions which use
one or more of seven addressing modes. The 6800/6808
has 197 different op codes.
The 8080/8085 has 246 different instructions which have
only one addressing mode each. There are five different
addressing modes. This provides a total of 246 different op
codes.
The 8086/8088 has 24 addressing modes (they are
presented in 11 addressing-mode categories in this text) and
approximately 91 different assembly-language instructions.
This is just part of the picture, however.
Each 8086/8088 instruction can have many variations,
the MOVe instruction probably being the best example.
MOV is considered one assembly-language instruction; yet
the 8086/8088 recognizes 28 different assembly-language
forms of the MOV instruction (move to a register, move
immediate, move byte to memory , move word to register ,
and so on). Each of the 28 assembly-language forms can
have many different machine-level instructions which may
be composed of up to 6 bytes (with eight 8-bit registers;
the ability to move any one of them to any other produces
10s of different machine-level instructions just for moving
8-bit registers).
To put it simply, there are hundreds of variations of the
MOV instruction alone. The possible variations of all 91
different assembly-language instructions number some¬
where between 3,000 and 4,000.
How can anyone learn so many combinations? First, if
you are using the 8086 or 8088, you will be concentrating
on learning about the 91 different assembly-language in¬
structions, not every possible variation. Second, once you
learn any one instruction, MOV, for example, most of the
variations will seem very natural. It’s not like rote memo¬
rization.
Which microprocessor is easiest to learn? That’s hard to
say. They each have strengths and weaknesses. And which
feature is a strength and which is a weakness depend on
what you as the programmer want to do.
(Note: Do not try to memorize all of these addressing
modes at this time. Read this chapter and then refer back
to it as you need to in the chapters to come.)
(Additional Note: Reference will be made in this chapter
to concepts and instructions which have not yet been
covered. This is necessary to explain the various advanced
addressing modes. This method of organizing the text has
the great advantage of placing all necessary information
regarding addressing modes in two easy-to-locate chapters.)
21-1 ADVANCED ADDRESSING
MODES
Some addressing modes which will be described in this
chapter use a multistep process to find the address of the
data or the next instruction to be executed. There may be
one or more intermediate addresses, but the final address
at which the data or instruction is to be found will be
referred to as the effective address .
There are three fundamental advanced addressing modes,
although some microprocessors also feature variations of
these three.
Relative Addressing
□□□□
□ 1
NOP
□ □01
□ 1
NOP
□ □□2
2D
BRA $02
□ □□3
□ 2
□ □□4
□ 1
NOP -
□ □□5
□ 1
NOP
□ □□b
□ 1
NOP —
□ □□?
□ 1
NOP
□ □□A
□ 1
NOP
/Vote what is happening here.
The BRanch Always instruction
causes the microprocessor to
branch forward 2 places from the
next instruction in memory!
Thus the next instruction to be
executed is at memory location
0006.
Fig. 21-1 An example of relative branching forward using
the 6800/6808.
The program counter always points to the next memory
location to be accessed. In the case of relative jumps, it
points to the next instruction after the jump instruction.
We start counting from the memory location being pointed
to by the program counter when the jump instruction is
being executed. This memory location is not the location
of the jump instruction itself, and it is not the byte after
the jump instruction, but is the next instruction in memory,
which is usually two memory locations after the jump
instruction.
Relative addressing is a mode in which your destination is
described relative to where you are now. You aren’t directed
to an absolute memory location but rather to an address
higher or lower than where you are now.
This form of addressing is not used to describe where to
find data but rather where the program should find its next
instruction. But let’s back up just a bit.
In an earlier chapter we described the program counter
and its function (the 8086/8088 uses the term instruction
pointer instead of program counter). It keeps track of the
next memory location to be accessed. Normally the locations
are taken in order. The microprocessor gets an instruction,
goes to the next byte in memory to get the next instruction
or data, then to the next, and so forth. Sometimes, however,
we need to “jump” or “branch” to a different area in
memory to get our next instruction, for example, when we
want to repeat a section of the program. (This saves time
compared to writing a portion of a program many times if
it is to be executed many times.)
Relative addressing involves 2 bytes (on 8-bit micropro¬
cessors). The first is the op code for the jump or branch
instruction. The second byte tells how far and in what
direction the microprocessor should jump. The second byte
is a signed binary number—that is, it can be positive or
negative. If it’s positive, the microprocessor jumps forward
in memory (to a higher-numbered address). If it’s negative,
it jumps backward (to a lower-numbered address). There
is a limit, however, to how far you can jump with this
form of addressing. On 8-bit microprocessors the range is
from -128, 0 to + 127 10 bytes. On 16-bit microprocessors
the range is from -32,768 10 to +32,767 10 bytes.
The next task is to determine exactly what point we start
counting from. For example, if we tell the microprocessor
to jump forward 10 memory locations, where do we start
counting from? We must again look at the program counter.
Let’s look at an example. Refer to Fig. 21-1. The 6800/
6808 has an instruction called BRA (BRanch Always),
which uses relative addressing.
The four-digit numbers in the left column are memory
addresses. The two-digit numbers in the next column are
op codes. The third column contains the assembly-language
mnemonics. Memory location 0002 contains the op code
20, which is the op code for the BRA instruction. The next
memory location, 0003, contains the number 02, which is
the same 02 referred to in the BRA $02 instruction.
The NOPs are simply dummy instructions placed there,
in this example, so that we have something to skip over
when the branch is implemented. Again, memory address
0002 contains the op code for BRA, which is 20. Address
0003 contains the number of places we wish to move
relative to where the program counter will be while it’s
executing this instruction! Since the program counter is
always pointing to the next instruction in memory, it will
contain 0004. 0004 16 + 02 16 = 0006 16 . This is the next
instruction to be executed.
Now let’s try branching backward. Figure 21-2 shows
an example.
At this point a review of 2’s-complement negative
numbers may be in order. Remember the odometer? Let’s
look at it again, in decimal first.
□ □□□
□ 1
NOP
□ □□1
□ 1
NOP
□ □□2
□ 1
NOP —
□ □□3
□ 1
NOP
UUUA
2D
BRA $FC
□ □□5
FC
□ 00b
01
NOP -
□ □□?
□ 1
NOP
□ □□A
01
NOP
Fig. 21
-2 An example of
the 6800/6808
This program branches backward
4 places from address 0006. This
is because FC 16 is the 2's-
complement hexadecimal number
for -4-16. The NOP at memory
location 0002 will be the next
instruction to be executed.
relative branching backward using
330 Digital Computer Electronics
Negative 2*s-Complement Numbers
Let’s say you buy a brand-new car and the odometer reads
00,000. Now suppose your odometer rolls forward if the
car drives forward, and rolls backward if the car drives
backward. Let’s drive backward from 00,000.
00,000
99,999
99,998
99,997
99,996
use another technique. A two-digit hexadecimal number is
made up of 8 binary bits, each representing a power of 2.
Find 2 8 and then subtract the number you wish to make
negative. In the case of -4, for instance, take 2? 0 - 4 10
= 252 10 . Now convert 252 10 to hexadecimal; it should be
FC. (To do the same thing with a 16-bit number, use 2 16
instead of 2 8 .)
Or, should no calculator be handy at the time, use the
technique described in Chap. 6, that of taking the 2’s
complement of the number you wish to make negative. In
the case of —4 it looks like this:
We could say that driving backward is like creating negative
numbers: 99,999 is 1 mile less than 00,000. What’s 1 less
than 0? Minus one, of course. 99,998 is 2 miles less than
00,000. What’s 2 less than 0? Minus two is. Let’s look at
some odometer readings from driving backward and their
negative equivalents, along with some odometer readings
from driving forward and their positive equivalents.
00,003 +3
00,002 -F2
00,001 +1
00,000 0
99,999 -1
99,998 -2
99,997 -3
99,996 -4
Now let’s show the same situation with a 1-byte hexa¬
decimal odometer.
03 +3
02 +2
01 +1
00 0
FF -1
FE -2
FD -3
FC -4
Now look at Fig. 21-2 again. Do you see where the FC
came from? It's —4.
What if you had to have a negative number like — 40 10 ?
Counting backward in hexadecimal would require too much
time. There are several options. First, experiment with your
calculator. Most scientific calculators now convert numbers
back and forth between decimal, binary, octal, and hex¬
adecimal. Many even do calculations in all number bases.
Try entering — 4 10 and converting it to hexadecimal. If the
calculator handles negative conversions, you’ll get many
F’s and a C at the end. Simply ignore all the leading F’s
and use just the last two digits, the final FC.
If your calculator does conversions between decimal and
hexadecimal but won’t handle negative numbers, you can
0000 0100
mi ion
+ i
mi lioo
I I
F C
+ 4
1 ’s complement (invert all bits)
add 1
2’s complement for —4
convened to hexadecimal
Indirect Addressing
Indirect addressing is an addressing mode in which the
data does not appear after the op code (as in immediate
addressing), nor does its memory location appear after the
op code (as in direct addressing), but rather a memory
location follows the op code, and in this location is another
address where the data may be found. It’s like finding the
address of an address. {Indirect addressing is indeed a
fitting name.)
There are two basic types of indirect addressing: absolute
indirect addressing and register indirect addressing. The
6502 uses absolute indirect addressing. The 8080/8085/Z80
uses register indirect addressing. The 8086/8088 uses reg¬
ister indirect addressing for data and program indirect
addressing for jumps (which we’ll study later). The 6800/
6808 has no indirect addressing (indirect addressing was
added to the 6809).
Let’s look at an example of this addressing mode and
then develop the topic further in the Specific Microprocessor
Families section of this chapter. The 6502 has an instruction
which looks like this
JMP ($aaaa)
which means JuMP indirect (indicated by the parentheses)
to the address indicated by aaaa. If the address were 1000 16 ,
it would be written as
JMP ($1000)
This tells us that at memory location 1000 and 1001 we
can find the address the microprocessor should jump to.
The address found at these two locations is loaded into the
program counter. (It takes two locations because addresses
in the 6502 are 16 bits wide but memory locations are only
8 bits wide.)
Chapter 21 Addressing Modes—II 331
Indexed Addressing
Indexed addressing involves using a register called an index
register , with a number called an offset , to calculate the
address where the data is located. Let’s look at an example
using the 6800/6808.
One version of the 6800/6808’s load accumulator A
instruction looks like this
LDAA $ff,X
which means
LoaD Accumulator A with the value in the
memory location found by adding the
contents of the X register to the
hexadecimal offset ff.
For example, if the X register contains the number 1000 16
and the instruction is written as
LDAA $22,X
we calculate the address where the data is located in this
way
X + ff = address
1000 16 + 22 ]6 - 1022 16
The microprocessor then goes to address 1022 and places
a copy of its contents in accumulator A.
You might be curious as to why we would want an
addressing mode like this. One reason is its usefulness in
accessing individual pieces of data in a data table. The
index register can be incremented (increased by 1) or
decremented (decreased by 1) easily, allowing the program¬
mer to access each item in the table.
The 6502 microprocessor has two index registers, the X
register and the Y register, and it has six different types of
indexed addressing! The 6800/6808 has only one index
register, the X register, with only one type of indexed
addressing. The 8080/8085 has no index registers at all (the
Z80 has two, X and Y) and has no indexed addressing
mode. The 8086/8088 has two index registers, the source
index and the destination index, and has several types of
indexed addressing.
Specific Microprocessor
Families
Go to the section which discusses your particular micro¬
processor.
21-2 6502 FAMILY
The 6502’s numerous addressing modes make it unusual
among 8-bit microprocessors. It has 13 different addressing
modes. Allow us to offer a few words of encouragement
at this time.
First, don’t expect everything to make sense in the
beginning. It takes time before all these new concepts
become clear and you feel comfortable with them. Inciden¬
tally, the subject of addressing modes is the only difficult
aspect of the 6502. In fact, the 6502 has the fewest different
instructions of any of the 8-bit microprocessors—only 56
(the 6800/6808 has 107; the 8080/8085 has 246).
Relative Addressing
The relative addressing mode occurs in only one category
of 6502 instruction, the Conditional Jump (Branch) cate¬
gory. Look at that section of the Expanded Table of 6502
Instructions Listed by Category. No other category uses
this type of addressing, and this category uses no other
type of addressing.
The subject of branching is coming in a later chapter,
but it is necessary to discuss branching instructions for a
moment to continue our coverage of the relative addressing
mode.
The status register is where the 6502’s flags are located.
They keep track of certain events. If the result of the last
calculation were 0, for instance, the zero flag bit would
contain a L If we wanted to know whether the last result
was a 0, we would check the zero flag. A 1 would mean
yes, and a 0 would mean no. If we wanted the program to
perform one action if the result of the last operation was a
0, and another if the result of the last operation was not a
0, we would write our program so that it would check the
zero flag.
Let’s look at the BEQ instruction. The assembler notation
looks like this
BEQ $rr
which means
Branch rr bytes from where the program
counter is now and do what it says to do
there if the result of the last operation
was EQual to 0.
You’ll notice that the Operation column of the instruction
table has a shorter version of that description.
Let’s look at a program fragment. Refer to Fig. 21-3.
After the BEQ instruction and its operand in locations
0007 and 0008 have been fetched, the program counter will
have already incremented to 0009, which is where we start
counting for the branch (jump).
332 Digital Computer Electronics
0005 EA
□ DDL EA
□□□7 FD
□□□a D3
□ooq ea
□ □□A EA
□ □□B EA
□ □□C EA
□□□D EA
□□□E EA
NOP
NOP
BEQ $03
NOP -
NOP
NOP
NOP —
NOP
NOP
Memory location 0007 contains FO,
the op code for BEQ. The next
location, 0008, contains 03 16 , which
is the distance the program is
going to jump relative to where the
program counter is at the end of
this instruction. Remember:
this jump occurs only if the last
operation set the zero flag (which
we are assuming for this example).
This would load the contents of memory location aaaa
into the low byte of the program counter (PC L ). The contents
of memory location aaaa + 1 would be loaded into the high
byte of the program counter (PC H ). (This reverse low-byte/
high-byte order is normal for the 6502.)
Let’s look at an example. If you refer to Fig. 21-4, you
will see that the instruction
JMP ($0004)
Fig. 21-3 6502 example of relative addressing. Note: The
zero flag is assumed to be set from a previous operation.
Refer back to the New Concepts section of this chapter
to see how a backward branch or jump would work and
how to use 2’s-complement negative numbers.
Indirect Addressing
There is only one 6502 instruction which uses the indirect
addressing mode. That instruction is the JMP instruction,
which is found in the Unconditional Jump Instructions
category in the Expanded Table of 6502 Instructions Listed
by Category.
This particular instruction can be used with two different
addressing modes. In the absolute addressing mode, the
microprocessor simply jumps to the specified address. When
written this way
JMP $aaaa
it means
Jump to address aaaa 16 and continue
program execution from that point.
In the indirect addressing mode, however, it would be
written this way
JMP ($aaaa)
and would mean
JuMP to the address which can be found
at memory location aaaa and aaaa + 1.
0000 tC JMP ($0004)
0001 04
0005 00
□003 EA NOP
0004 IF-*-low byte-
0005 01-high byte
does not mean that address 0004 is where the program is
supposed to jump to, but rather that location 0004 contains
the address it’s supposed to jump to.
Indexed Addressing
Indexed addressing is the subject of the remainder of this
6502 section. There are four basic indexed addressing
modes, and two more which use a mixture of indexed and
indirect addressing.
It should be noted that while the 6502 family has a great
number of addressing modes which use the index registers,
it is the only family which has index registers which are
only 8-bits wide. The 6800/6808, Z80, and 8086/8088 all
have 16-bit index registers. Keep this in mind if you use
the 6502 in addition to one of the other microprocessors.
Zero Page,X and Absolute ,X Addressing
You may remember from the New Concepts section of this
chapter that the 6502 has two index registers, X and Y,
and six different forms of indexed addressing. Here are the
first two of the six forms. The difference between these
two forms is the range of addresses possible.
These first two forms, and the next two, are so similar
to the description in the New Concepts section that you
will probably have little difficulty understanding them. If
you don’t remember how the indexed form of addressing
works, go back and reread the description now.
Look in the Data Transfer Instructions category of the
Expanded Table of 6502 Instructions Listed by Category.
We will use the LDA instruction to illustrate the zero
page,X and absolute,X addressing modes.
This is where the effective address
is being stored. 01 IF is placed in
the program counter.
□ HE next instruction -
This is the location of the next
□ 150
instruction to be executed.
Fig. 21-4 Example of 6502 indirect addressing mode.
Chapter 21 Addressing Modes — II 333
First notice the Assembler Notation column for the zero
page,X and absolute,X forms of the LDA instruction. For
these two the assembler notation is
LDA $ff,X <— zero page,X
LDA $ffff,X absolute,X
In both cases the offset (ff or ffff) is a hexadecimal number
which is going to be added to the value in the X register.
The sum of these two values provides the address of the
data which is to be loaded into the accumulator.
For example, if the X register contained the hexadecimal
number 10, the instruction
LDA $034E,X
would add those two values,
034E 16 + 10 I6 = 035E 16
and place a copy of the contents of memory location 035E 16
in the accumulator.
When zero page,X addressing is used, the offset (the
number being added to the X register) is two hex digits
wide and the X register is also two hex digits wide. Two
hex digits can address memory locations only in page 0
(00 16 to FF 16 ). When this addressing mode is used, it is
assumed that the data is somewhere in page 0. If the sum
of the offset and the X register is greater than FF ]6 then
the most significant digit is truncated and only the first two
digits are used! For example, if the X register contained
FF, the instruction
LDA $04,X
would add the offset to the X register
04 l6 + FF 16 = 103 16 ( The 1 will be dropped.)
so the data will be retrieved from location 03 16 ! Numbers
larger than FF 16 wrap around to the beginning of page 0.
When absolute,X addressing is used, the offset is a four¬
digit hexadecimal number ranging from 0000, 6 to FFFF 16 .
This allows the data to be located anywhere in the entire
6502 address range. If the sum of the offset and the X
register exceeds FFFF 16 , then the microprocessor again
performs a wraparound back to 0000 16 .
Zero Page,Y and Absolute ,Y Addressing
Notice in the Data Transfer Instructions section of the
Expanded Table of 6502 Instructions Listed by Category
that the LDX instruction uses both absolute,Y and zero
page,Y addressing. These work exactly the same as abso¬
lute^ and zero page,X, except that they use the Y register
instead.
The absolute,X, absolute,Y, and zero page,X addressing
modes are used by many 6502 instructions. Zero page,Y
addressing is used by only two instructions, however—
LDX and STX.
Indirect Indexed Addressing
Indirect indexed addressing , as the name implies, is a
mixture of indirect addressing and indexed addressing.
Notice that the word 4 'indirect” is first, and the word
“indexed” is next. In this form of addressing, the indirect
part of the address calculation is accomplished first; then
the indexing is taken into consideration.
Refer to this form of the LDA instruction in the Data
Transfer Instructions section of the Expanded Table of 6502
Instructions Listed by Category. Remember the word or¬
der— indirect , then indexed ; and notice the assembler no¬
tation—LDA ($aa),Y.
To understand the assembler notation for this form of
addressing, it helps to remember one of the rules of algebra.
In algebra, expressions are read from left to right, and when
parentheses are encountered, they are read from the inside
to the outside. Let’s look at an example.
LDA ($aa),Y
The $aa stands for a two-digit hexadecimal address. Because
only two digits are allowed, this address must be between
00 16 and FF 16 . At this address, and the one following it (aa
and aa + 1), is a 16-bit address stored in reverse low-byte/
high-byte order. This address is then added to the Y register
to produce the actual (effective) address where the operand
(data) is stored. Notice that we worked our way from left
to right and from the inside toward the outside as we
analyzed this instruction.
For example, let’s say that
Y register = 10 16
memory location 2D = 00
memory location 2E = CO
If we write the instruction
LDA ($2D),Y
the microprocessor will look in addresses 2D and 2E and
use their contents to form another address, C000. It will
then take the number C000 16 and add it to the Y register:
C000 16 + 10 16 = C010 16
C010, 6 is where the data is actually stored.
334 Digital Computer Electronics
To summarize,
LDA ($aa),Y
means
LoaD the Accumulator with the contents
of an address formed by adding the
contents of memory location aa and aa + 1
(low-byte/high-byte order) to the Y
register.
Indexed Indirect Addressing
This form of addressing is also a mixture of indexed and
indirect addressing, but it is the reverse of the previous
indirect indexed addressing.
It will be helpful here, as in the previous explanation, to
think of how algebraic expressions are written, from left to
right and from the inside to the outside.
We will again use the LDA instruction. Look at the
indexed indirect form of this instruction. In the Assembler
Notation column it appears as
LDA ($ff,X)
In this form of addressing, the microprocessor takes the
two-digit offset (ff 16 ) and then adds it to the value found
in the X register. (If the sum of ff and X is greater than
FF 16 , the sum will be truncated so that only the two least
significant digits remain.) The address formed by the sum
of ff and the X register and the following address contain
the effective address stored in reverse low-byte/high-byte
order.
Let’s try an example. If
X register = 10 16
and we write the instruction
LDA ($11,X)
then the microprocessor will add 11 ]6 to the X register
1 116 + 10l6 = 21 16
creating the address 21 16 . However , this is not where the
operand (data) is stored! At addresses 21 16 and 22 16 the
effective address is stored in reverse low-byte/high-byte
order. So if
memory location 21 = 00
memory location 22 = CO
then the address C000 /6 is created. Memory address C000 16
does contain the operand!
To summarize,
LDA ($ff,X)
means
LoaD the Accumulator with the contents
of the memory location pointed to by the
contents of memory location ff + X and ff
+ X + 1.
21-3 6800/6808 FAMILY
The 6800/6808 microprocessor has only two addressing
modes which must be covered in this chapter—relative
addressing and indexed addressing. (The 6800/6808 has no
form of indirect addressing.)
Relative Addressing
The 6800/6808 uses relative addressing with all of its branch
instructions. These fall into three instruction categories,
Unconditional Jump (Branch) Instructions, Conditional Jump
(Branch) Instructions, and Subroutine Instructions. This
form of addressing works exactly as described in the New
Concepts section of this chapter. (In fact, the 6800/6808
was used as our example in that section.)
Let’s go over this mode again by using the program
fragment in Fig. 21-5.
Since 02 16 is a positive number, we branch forward by
that many spaces starting with the memory location which
will be pointed to by the program counter after the BRA
instruction and its operand have been fetched.
It is important to remember that the BRA operand is a
2’s-complement signed binary number and thus can be
either negative or positive within a range from -F 127 10 to
— 128 I0 . A negative number indicates a backward branch,
and a positive number indicates a forward branch.
Indexed Addressing
The subject of indexed addressing, as discussed in the New
Concepts section, was illustrated by using the 6800/6808.
We present that information again here for your conven¬
ience.
□ □ID
□ □11
2D
□ 2
BRA $(05)
0012
□ 1
NOP-
□ □13
□ 1
NOP
□ □14
□ 1
NOP —
□ DIB
□ 1
NOP
Fig. 21-5 An example of relative addressing.
Chapter 21 Addressing Modes—II 335
One version of the 6800/6808’ s load accumulator A
instruction looks like this
LDAA $ff,X
which means
LoaD Accumulator A with the value in the
memory location found by adding the
contents of the X register to the
hexadecimal offset ff.
For example, if the X register contained the number 1000 16
and the instruction were written as
LDA $22,X
we would calculate the address where the data was located
in this way:
X + ff = address
1000 16 + 22 16 = 1022 16
We would go to address 1022 and place a copy of its
contents in accumulator A.
21-4 8080/8085/Z80 FAMILY
The 8080/8085 microprocessor is easier to learn in some
respects than the other 8-bit microprocessors. One reason
is that the 8080/8085 has the fewest number of addressing
modes. And while the 8080/8085 has the most number of
different instructions (246, in contrast to the 6502 with
only 56 and the 6800/6808 with 107), each instruction
works with only one addressing mode (in contrast to the
6502, which has some instructions which operate in as
many as eight different addressing modes).
As we talk about the 8080/8085/Z80 family, you should
remember that although the Z80 is treated as a part of the
8080/8085 family in this text, it is a significantly enhanced
member of the 8080/8085 family. It has many multibyte
instructions and several addressing modes which the 8080/
8085 does not have. At this time we will cover only those
aspects of the Z80 which it has in common with the 8080/
8085.
Register Indirect Addressing
The only advanced addressing mode which the 8080/8085
has is register indirect addressing. Although indirect ad¬
dressing was covered in the New Concepts section of this
chapter, register indirect addressing was not covered since
it is a variation of indirect addressing which, among the
8-bit microprocessors, is unique to this family.
Register indirect addressing uses the contents of a 16-
bit register pair (most often the HL register pair) as a pointer
for the operand.
For example, refer to the Data Transfer Instructions
section of the Expanded Table of 8085/8080 and Z80 (8080
Subset) Instructions Listed by Category and look at the
MOV A,M [Z80 = LD A,(HL)] instruction. (The MOV
A,M instruction is the eighth instruction in this category.)
The 8085 form is written
MOV A,M
which means
MOVe to the Accumulator the number found
at the Memory location pointed to by the
HL register pair.
The Z80 form is written
LD A,(HL)
which means
LoaD the Accumulator with the number
found at the memory location pointed to
(parens) by the HL register pair.
which says the same thing the 8085 form did but in different
words.
To give an example, if
register pair HL = 1000 16
and you entered MOV A,M [Z80 LD A,(HL)] into your
assembler, the microprocessor would go to memory location
1000 16 and place a copy of its contents in the accumulator.
There are a few occasions when either the BC or the DE
register pair is used instead of the HL pair. You may want
to page through the Expanded Table of 8085/8080 and Z80
(8080 Subset) Instructions Listed by Category to see some
of the instructions that use this addressing mode.
21-5 8086/8088 FAMILY
Because the 8086/8088 is a 16-bit microprocessor, it uses
a greater number of addressing modes than the 8-bit
microprocessors, and the modes are more complex. We
covered the basic 8086/8088 addressing modes in a previous
chapter and will try to give a simple, yet sufficiently
complete description of each of the advanced modes at this
time.
336 Digital Computer Electronics
Register Relative Addressing
Register relative addressing uses two numbers, added
together, to determine the address of the source. This form
of addressing is especially useful in addressing arrays (tables
of data).
Some examples of register relative addressing using the
format used by DEBUG (an MS-DOS utility which helps
to kk debug” programs and includes an assembler and
disassembler) are
MOV AL,[BX + 0100]
MOV AX,[DI + 0200]
MOV [SI+ 0500],CL
MOV [BP + 20],BL
MOV DI,[BX + 0400]
Figure 21-6 illustrates how this form of addressing works.
The instruction
MOV AL,[BX + 0100]
is used as an example. Notice first the brackets surrounding
the BX + 0100. This is required by DEBUG and indicates
that the two numbers added together (the value in register
BX + 0100 ]6 ) will point to the location of the data being
moved to AL.
We can use the number in the source (0100) to indicate
the location of the beginning of the table. The value in the
register indicated in the source operand tells us which item
in the table is the desired data item.
Notice in Fig. 21-6 that 0100 is the beginning of the
table and that 03 (the value in BX) is the data item we
need. We need the fourth item in the table starting at
address 0100. The contents of memory location 0103 (E3)
have been copied to register AL.
It is important to remember that we have added the
displacement (0100) to the value in the indicated register
(BX) to form an address (0103) in the current data segment!
Program Relative Addressing
Program relative addressing is used with JMP and CALL
instructions. This mode specifies where the next program
instruction is located without using absolute addressing.
This allows you to write relocatable assembly-language
programs.
Figure 21-7 shows an 8086/8088 instruction which is not
using program relative addressing. (We’ll show you program
relative addressing in a moment.) This figure is using direct
addressing. We have listed the same line of code three
times.
The first line shows the code as it appeared on our
computer after being disassembled by DEBUG.
The second line shows DEBUG’s disassembly broken
into its major components. The address is the address of
the current memory location. We did not type the address;
DEBUG picked that address for us. The machine code
contains the actual bits which will tell the 8086/8088 what
to do. The assembly language is what we typed in when
using DEBUG.
The third line shows even greater detail. Notice that the
code segment the program is to jump to (8888) and location
within the segment (0100) are actually contained in the
machine code (the bytes are reversed).
Figure 21-8 shows a JMP instruction written using
DEBUG which does use program relative addressing,
instead of direct addressing as in Fig. 21-7.
Line one shows the information as it appeared on our
screen when disassembled by DEBUG.
Line two illustrates the major components of the disas¬
sembly. We typed in the assembly language, and DEBUG
provided us with the machine code.
The third line shows the components in greater detail.
The most interesting fact is that the address we specified
as our target address is not the same as the address DEBUG
generated. Let’s see what DEBUG did.
The JMP op code, EB, is in memory location 0100 as
indicated in the “location within segment’' portion of the
Chapter 21 Addressing Modes—II 337
864E:0111
EA00018888
JMP
8888:0100
|864E:0111
|EA00018888|
| JMP
8888:0100
Address
Machine code
Assembly language (DEBUG)
Location within segment
Fig. 21-7 Direct addressing.
line. That means the next byte , OE, is in address 0101.
(DEBUG does not show the 0101.) Therefore, the next
instruction is at memory location 0102.
How far is it from memory location 0102 to our target
address of 0110? Remember, these are hexadecimal num¬
bers.
0110 16 - 0102 16 = E l6
To reach the target address of 0110, the microprocessor
will have to jump forward a number of spaces from the
point (the instruction) at which the instruction pointer is
pointing when this instruction is executed; the number of
spaces is E 16 . The 0E in Fig. 21-8 was calculated by
DEBUG as the position of our target relative to where the
instruction pointer will be when this instruction is being
executed.
Relative addressing tells the microprocessor how far to
jump forward or backward from the instruction after the
JMP instruction. The next instruction is used because the
instruction pointer always points to the next instruction to
be executed.
Location within segment to jump to
A positive relative address signifies a jump forward; a
negative relative address signifies a jump backward.
Register Indirect Addressing
Register indirect addressing uses a register to point to a
memory location rather than specifying that location di¬
rectly. BX, BP, SI, and DI are used as pointers. All of
them except BP point to locations in the data segment ; BP
points to a location in the stack segment. The registers can
point to either the source or the destination operand.
An assembly-language instruction which uses indirect
addressing is shown in Fig. 21-9.
The format of the instruction line in bold print in Fig.
21-9 is the format that DEBUG uses. (The code segment
on your computer will probably not be the same as the one
shown in Fig. 21-9.)
Most of the different components of the instruction line
in bold have been identified in the figure. [BX] is labeled
as the source. The brackets around BX indicate that the
operand is not the contents of BX; rather the operand will
be found at the address pointed to by BX.
864E:0100
EB0E
JMP
0110
|864E:0100|
| EB0E |
| JMP
0110
Address
Machine code
Assembly language (DEBUG)
Code segment | JMP op code | Address specified
Location within segment Relative address generated by DEBUG
Fig. 21-8 Program relative addressing.
338 Digital Computer Electronics
0100
0101
0102
0103
0104
0105
0106
0107
0108
0109
010A
Memory
8B
07
hh
hh
hh
hh
hh
hh
AA
BB
hh
- Code segment
82CC:0100 8B07
Address- 1 Machine
within segment code
AA replaces hh-
BB replaces hh -
BX-
points I
to memory
location 0108
Source
destination -
MOV AX,|
[BX]
Assembly
language
■ Accumulator AX ■
AH
- hh
AL
hh
Base BX
BH
01
BL
08
Fig. 21-9 Register indirect addressing.
If you look at the contents of BX, you will see the value
0108. That means that the actual operand is in memory
location 0108. In this case we are moving a 16-bit word
rather than an 8-bit byte. Since it takes two memory
locations to hold a whole word, we will find the operand
in locations 0108 and 0109. The 16-bit values in locations
0108 and 0109 are copied into AX, which is the destination.
Figure 21-10 is a screen dump of Fig. 21-9 obtained by
using DEBUG.
In the first line
-d 100 lOf
tells DEBUG to “dump” the contents of memory locations
0100 16 through 010F 16 to the screen so that we can see
them. The hyphen halfway through the memory dump
separates those 16 bytes into two sections to make the
display easier to read. We have shown the contents of
locations 0100 and 0101 in bold because they are the object
code for the
MOV AX,[BX]
instruction. The contents of memory locations 0108 and
0109 are in bold because they are the locations being pointed
to by register BX.
The -r tells DEBUG to display its registers. We have
shown the contents of registers AX and BX in bold in this
illustration because they are the two registers being referred
to in this example.
The -t is the DEBUG trace command. This tells DEBUG
to execute the next instruction and then stop. The next
instruction is
MOV AX,[BX]
Notice the contents of register AX after the trace command.
The contents of memory locations 0108 and 0109 have
been copied to register AX as was illustrated in Fig. 21-9.
Take some time to compare Figs. 21-9 and 21-10. You
may notice that the code segments in the two figures differ.
That’s because we created the figures on two different days,
and the memory arrangement in our computer was not
exactly the same both days. This is normal and something
you should expect to see as you try these figures and
-a mu mt
HDES :AB D7 □□ □□ □□ □□ □□ 00-AA BB □□ □□ DO □□ 0Q □□
-r
AX=DD00 BX=D10A
DS=qDEq es^deh
HDEH:0100 ABD7
CX=00DD DX=DDDD SP—FDbE
ss=qoEq cs^qopq ip=didd
MOV AX,[BX1
BP=D00Q SI=0000 DI=000D
NV UP El PL NZ NA PO NC
DS:010A-BBAA
-t
AX=BBAA BX=D1DA CX^ODOn DX=DDGD SP=FDLE
DS-qnaq ES=qoEs ss=R0Eq cs^hdeh ip=dide
RDEG:010E □□□□ ADD [BX+SI],AL
Fig. 21-10 DEBUG screen dump of Fig. 21-9.
BP=0D00 SI=000D DI=D0DD
NV UP El PL NZ NA PO NC
DS:DIDA=AA
Chapter 21 Addressing Modes—II 339
examples on your computer. Everything will be the same
except the code segment, and that will almost never match
ours.
Again, in the case of register indirect addressing, at least
one of the operands is in a memory location pointed to by
the value in a register (BX, BP, SI, DI).
Program Indirect Addressing
Program indirect addressing is used by CALL and JMP
instructions. It allows the memory location where the
program is to fetch its next instruction to be stored in a
register, in a memory location pointed to by a register, or
in a memory location pointed to by a register with a
displacement.
Normally instructions are stored in memory in sequential
order, with the microprocessor fetching one after another.
When a JMP instruction uses direct addressing, the address
the microprocessor is to jump to is placed immediately after
the jump instruction itself.
A CALL instruction causes the microprocessor to go to
another area of memory where a subroutine is stored,
execute the subroutine, and then return to where it left off
before it began the subroutine. The CALL, like the JMP
instruction, can use direct addressing and place the location
of the subroutine immediately after the CALL instruction.
When either the CALL or the JMP instruction uses one
of the 16-bit registers (AX, BX, CX, DX, SP, BP, SI, or
DI), it means that the destination for the JMP or CALL is
located in that register. For example
JMP AX
instructs the microprocessor to look in register AX and
jump to the location stored in AX. That is, AX “points”
to the correct memory location.
When either the JMP or the CALL instruction uses a
register placed inside brackets ([BX], [BP], [SI], or [DI]),
it means that register contains an address, and that address
contains another address, which is the actual destination
for the JMP or CALL. For example,
JMP [BX]
instructs the microprocessor to look in register BX. Let's
say BX = 0200. Next the microprocessor looks at address
0200 and 0201. There it will find another address which is
its actual destination.
When either the JMP or the CALL instruction uses one
of the registers with brackets ([BX], [BP], [SI], or [DI])
and a displacement, the microprocessor is instructed to add
the displacement to the contents of the register, forming an
address, and then to look at thax address and get another
address, which is the actual destination. For example
JMP [BX + 0100]
instructs the microprocessor to add 0100 16 to the value in
BX. Let’s say that BX contains 0500 J6 .
0500 16 + 0100 16 = 0600 16
The microprocessor now looks in addresses 0600 and 0601
and gets another address. This is the destination address
where the next instruction is to be fetched or the subroutine
begins.
Base plus Index Addressing
Base plus index addressing also uses the concept of cal¬
culating the address where data is located rather than using
direct addressing, which explicitly states where the data is
located.
When base plus index addressing is used, the contents
of one of the base registers (either BX or BP) and the
contents of one of the index registers (either SI or DI) are
added to calculate the address of the operand. For example,
MOV AX,[BX + DI]
instructs the microprocessor to add the value in register BX
to the value in register DI. This sum is the location of the
data which is to be copied into register AX. This is illustrated
in Fig. 21-11.
Base plus index addressing is useful for working with
tables of data. The base register (BX or BP) can point to
the beginning of the data table. The index register (SI or
DI) can then point to the specific piece of data within the
table. The program can then increment or decrement the
index register to point to the next or preceding piece of
data in the table.
Base Relative plus Index Addressing
Base relative plus index addressing combines the features
of base plus index addressing and register relative address¬
ing. Examples of base relative plus index addressing are
MOV DX,[BX + SI+10]
MOV [BX + DI + 20],AX
In the first example, the microprocessor would add the
values in registers BX and SI and the number 10 16 . The
sum is the memory location of the data which is to be
copied into register DX.
In the second example, the microprocessor would copy
the contents of register AX to a memory location whose
address would be calculated by finding the sum of 20 16 ,
the value in register BX, and the value in register DI.
340 Digital Computer Electronics
Fig. 21-11 Base plus index addressing.
1 his addressing mode is useful for working with two- desired data (for example, a field within a record within a
dimensional data tables. The displacement (the number) file, or a specific piece of data in a data table). The program
can point to the beginning of the table, since this is the can then increment or decrement the base register to point
constant value. The base register (BX) can point to the first to the next or previous record in the file and increment or
of the two dimensions (for example, a record in a file or decrement the index register to point to the next or previous
an area in a data table). The index register (SI or Dl) can field in the record,
then point to the specific memory location containing the
Chapter 21 Addressing Modes—II 341
Branching and Loops
In this chapter we’ll study branching and loops. A branch
instruction (or jump instruction) causes the program to
“skip” forward or backward and to execute instructions
from this new memory location.
A loop involves executing a series of microprocessor
instructions and then branching backward to repeat the same
set of instructions. This “loop” is finally broken, or exited
from, when some condition is met.
The previous chapter introduced you to the remainder of
the addressing modes (the more difficult ones) which had
not been covered in the earlier chapter on addressing. From
this point on we will use many of the different types of
addressing modes available to each microprocessor. You
should refer back to either of the chapters on addressing
whenever necessary.
New Concepts
We’ll study unconditional branching (or jumping) first; then
we’ll discuss the slightly more difficult subject of conditional
branching. Later we’ll look at loops and how to control
them through the use of conditions and counters.
22-1 UNCONDITIONAL JUMPS
The simplest type of branch or jump is an unconditional
one. This means that the program will jump to the indicated
memory location every time this part of the program is run.
The jump can be forward or backward.
With unconditional jumps, most of the microprocessors
featured in this text use some form of direct or indirect
addressing to indicate where the next instruction should be
fetched from. The exceptions to this are the 6800/6808,
which can also use relative addressing, and the 8086/8088,
which also uses relative addressing, at least for jumps
within a single memory segment.
To jump forward, you simply indicate the address of the
next instruction to be executed. WeTl look at exactly how
the different addressing modes are used in the Specific
Microprocessor Families section of this chapter.
22-2 CONDITIONAL BRANCHING
Conditional branching, like unconditional branching, causes
program execution to continue with an instruction which is
not the next instruction in memory. We either skip forward
or backward from where we are now. Whether or not
program execution does skip depends on a certain condition.
The microprocessor determines whether a condition is
true or not true by the condition of the flags. To be able to
predict whether or not a condition will be true when the
microprocessor reaches the point at which the conditional
branch occurs, one must know how the preceding instruc¬
tions affect the flags. How each instruction affects each of
the flags is shown in several of the instruction-set tables
for each microprocessor.
When we branch forward, we have the effect of skipping
over a certain number of instructions, if certain conditions
exist, and not skipping over them if those conditions do
not exist. Figure 22-1 shows a generic example of branching
forward.
When we branch backward , the instructions between
where we branched from and where we branched to are
executed again. They could in fact be executed many times.
This creates a loop which will not be exited from until
some condition is met. Figure 22-2 shows a generic example
of branching backward.
In Fig. 22-2, we are not branching backward from address
0009 because of the instruction at that memory location.
Rather, we are branching backward because of the instruc-
□ 000
INSTRUCTION
0001
DATA
□ 000
INSTRUCTION
0003
DATA
0004
INSTRUCTION
0005
INSTRUCTION
□ 000
INSTRUCTION
0007
COND JUMP
□ □□A
□ 0 A0
This area is skipped over if
condition exits. If condition
doesn't exist, this area is not
skipped over.
□ 0 A0
INSTRUCTION
□ 0A1
DATA
□ 0 A0
INSTRUCTION
□ 0 A3
END
Fig. 22-1 Example of generic forward conditional jump.
tion at location 0007 and the address at location 0008. The
arrow is drawn from location 0009 because that will be the
instruction pointed to by the program counter or instruction
pointer when the branch occurs. Remember, the instruction
pointer or program counter points to the next instruction to
be executed, not the one currently being executed.
22-3 COMPARE AND TEST
INSTRUCTIONS
Many (but not all) microprocessor instructions affect the
flags. The flags then tell something about the results of the
instruction. There are instructions, however, compare and
test instructions, which actually do nothing except affect
flags.
For example, the arithmetic instructions actually accom¬
plish some task, such as adding, subtracting, multiplying,
or dividing, and also affect the flags depending on the result
of the operation. Compare and test instructions, however,
compare a register or memory location to another, to zero,
or and two registers, without producing any result or
changing any register or memory location—that is, no
answer is produced. The flags, however, respond just as if
an answer had been produced. A conditional branch instruc¬
tion can then check the flags and determine whether a
certain condition is true or false and then branch or not
branch accordingly.
22-4 INCREMENT AND DECREMENT
INSTRUCTIONS
Sometimes you may want to repeat a section of your
program a certain number of times. A register or memory
location is used to count how many times the section has
been repeated. This register or memory location being used
as a counter can either count up (increment) to a certain
value or count down (decrement) to a certain value. Since
it is easy to test for the occurrence of zero (just check the
zero flag), counters often start at a certain number and
decrement to zero. When the counter reaches zero, we
know how many times that section of the program has
repeated.
This technique produces a loop and uses conditional
branching in a way that is similar to that discussed in the
last section, although the intent is a little different. In the
last section we were talking about situations when you want
to branch if an operation produces a certain result. In this
section we are discussing situations when we simply want
something to be repeated a certain number of times.
22-5 NESTED LOOPS
It’s possible to nest loops one inside the other. Figure
22-3 shows what this looks like.
The operand immediately following the conditional branch
instruction may not be the actual address to branch to but
rather the value needed by some other form of addressing
such as relative addressing.
Remember also that we do not branch from the memory
location containing the conditional branch instruction; nor
do we branch from the next address which determines
where we branch to, but from the instruction after that.
In Fig. 22-3 you can see that an inner loop will be
repeated until the conditions necessary for the program to
“drop through” the bottom of the loop exist, in which case
the program may go back to the beginning of the outer
loop, depending again on the conditions which exist.
0000
INSTRUCTION
□ □□1
DATA
□ □□E
INSTRUCTION
□ □□3
DATA
0004
INSTRUCTION
0005
INSTRUCTION
□ 00b
INSTRUCTION
0007
COND JUMP
00 0 A
□ 000
□ ooq
INSTRUCTION
Fig. 22-2 Example of generic backward conditional jump.
This area is repeated if certain
condition exists. This area is not
repeated if condition does not
exist.
Chapter 22 Branching and Loops
343
□ □□□ INSTRUCTION -
□□01 data
□□□0 INSTRUCTION
□003 data
□ □□4 INSTRUCTION
□□□5 data
□ □□0 INSTRUCTION -
□□□7 data
□□□fl INSTRUCTION
□□□3 data
□ □□A CONDITIONAL BRANCH BACKWARDS
□□□B □□□L
□□□C INSTRUCTION -
□□□D data
□ □□E INSTRUCTION
□□□E data
□□ID CONDITIONAL BRANCH BACKWARDS
□□11 □□□□
□012 INSTRUCTION -
Fig. 22-3 Generic nested loops.
Specific Microprocessor
Families
Let’s look at each of our microprocessors’ instructions to
see how branching and loops are handled.
22-6 6502 FAMILY
The 6502 microprocessor family has a variety of instructions
to handle unconditional jumps, conditional branching, com¬
paring, incrementing, and decrementing. We’ll look at
several tasks and see how the 6502 microprocessor handles
them.
You should enter each program into your computer or
microprocessor trainer and single-step through it, watching
the appropriate registers, memory locations, and flags to
understand how each program works.
Unconditional Jumps
The forward unconditional jump using absolute addressing
is easiest to understand. An example is shown in Fig.
22-4.
The program begins by loading the accumulator with
FF 16 . In a moment we are going to subtract another number
from FF 16 . First, however, we need to jump to the area of
memory where the subtract instruction is. We have placed
the subtract instruction several memory locations forward
from this point to show, in a very simple manner, how the
unconditional jump instruction operates.
The next instruction is our jump instruction. In the source
code column of line 0004 the instruction
JMP MINUS
appears, which might be different from what you were
expecting.
The instruction is saying to jump to a place called
MINUS. To be able to jump to a place with a certain name
is not a native ability of the 6502 microprocessor. Our
assembler is making this possible. Line 0008 has the label
MINUS in the label column. This is the place we want to
jump to. Notice the address at the MINUS label. The
address is 0348. Now look back at line 0004. In the op
code column you see 4C, which is the op code for an
unconditional jump. Then come the numbers 48 03. If you
reverse those two sets of numbers, you have 0348. This is
the memory location of the instruction labeled MINUS. If
you use an assembler, you can use labels and the assembler
will calculate the address for you. If you are hand-assembling
these programs, you must enter the address as shown in
the op code column, in the reverse low-byte/high-byte
order. If you are using an assembler which does not allow
labels, you will need to use the format shown in the 6502
tables. Namely,
JMP $0348
□ □□1
□ 340
. org
$□340
;beginning of code
□□□a
□ 34D
□ □□3
□ 34D
A3
FE
START:
LDA
#$FF
;minuend
□ □□4
□ 343
4 C
4a
□ 3
JMP
MINUS
;forward unconditional jump
□ □□5
□ 345
EA
NOP
□ □□£>
□ 34 L
EA
NOP
;misc. instructions
□ □□?
□ 347
EA
NOP
□ □□a
□ 34a
3a
MINUS:
SEC
jprepare for subtraction
□ □□□
□ 345
E5
EE
SBC
#$EE
;subtrahend
□ □ID
□ 34B
aD
4 F
□ 3
STA
ANSWER
;store difference
□ □11
□ 34E
□□
BRK
; stop
□Die
□ 34F
□ □13
□ 34F
□□
ANSWER
.db
$□□
;memory area for answer
□ □14
□ 35D
; (initialized to □□)
□ □15
□ 3 5 □
. end
Fig. 22-4 Forward unconditional jump with the 6502
microprocessor.
344 Digital Computer Electronics
After the jump instruction are several NOPs which could
be other instructions or just unused memory in a particular
microprocessor system.
Line 0008 is the next instruction to be executed. It sets
the carry flag in preparation for the subtraction instruction.
In line 0009 we subtract EE 16 from FF 16 (in the accumulator).
In line 0010 we store the result of our subtraction in a
memory location called ANSWER. Look at line 0013, labeled
ANSWER. In the op code column are the initials .db. They
stand for define byte. We are telling the assembler to reserve
a memory location, namely, a single byte of memory, with
the name ANSWER. The assembler is initializing the
memory location ANSWER with a value of 0. Our program
can then put any other number we wish in that location.
Notice also that the memory location of ANSWER is
034F 16 . In the op code column of line 0010 we see 8D 4F
03. 8D is the op code for storing the value of the accumulator
in a certain memory location. If you reverse the order of
4F 03, you have 034F, which is the memory location of
ANSWER. Again, the assembler made life simpler by
figuring out where the next available memory location
would be and setting aside that location for the ANSWER.
Finally, in line 0011 the program stops.
You should enter this program and single-step through
it, making sure that everything works as described.
Conditional Branches
Now let’s see an example of conditional branching. Figure
22-5 shows such an example.
In this program we are going to do several things
differently from the way they were done in the last program.
First, we are using a conditional jump or branch rather than
an unconditional one. Second, we are branching backward
rather than forward. Third, we are creating a loop by
branching backward and repeating a section of the program.
Finally, we are using a register as a counter to control how
many times the loop repeats.
In line 0003 we place the number 3 16 in the X register.
This register controls how many times we will branch
backward. In line 0004 we clear the Y register making it
00, 6 so that it can be used to count how many times the
loop repeats.
Line 0005 marks the beginning of the loop; we have
named that location REPEAT. In this line we increment the
Y register since we are beginning to pass through the loop,
in this case for the first time. The Y register is keeping
track of how many times the loop is passed through. Line
0006 represents the fact that there could be many instructions
inside the loop which are going to be repeated.
Line 0007 decrements (reduces by 1) the X register. The
X register keeps track of how many times through the loop
are remaining.
Line 0008 is where we meet our conditional branch
instruction. BNE means Branch if Not Equal. Your first
thought might be, “Not equal to what?” If you check the
Expanded Table for the 6502, you’ll see it is Branch if the
last result is Not Equal to 0.
All the conditional branch instructions are influenced by
the most recent instruction that affected the flag they check.
In this case the zero flag is checked. What was the last
instruction which sets or clears the zero flag? The DEX
(DEcrement X register) instruction. If the X register were
reduced to 0, the zero flag would be set. Has the X register
been reduced to 0? On this first pass through the loop, it
gets reduced from 3 to 2. No, the X register is not equal
to 0.
The branch instruction says, “Branch if the last result is
Not Equal to 0.” Clearly this is true: the last result is not
0, so we branch. Branch to where? We branch to the
memory location known as REPEAT. Notice that the location
called REPEAT, in line 0005, is memory location 0344 16 .
Now look again at line 0008. DO is the op code for the
BNE instruction, and FB is where it is branching to. Is FB
the memory location of REPEAT? No. The BNE instruction
uses relative addressing. FB ]6 is a negative-signed binary
number telling us how many places to move from where
we are now. FB i6 is — 5 10 . We must branch five memory
location backward from memory location 0349 16 .
It will be helpful to enter this program into your computer
or microprocessor trainer and single-step through it. We’ve
gone through the loop only once in our discussion here.
□ □□1
□ 34D
.ORG
$□340
□ □□a
□ 340
□ □□3
□ 34 □
AE
□ 3
START:
LDX
*$□3
;initialize X (repeats)
□ □□4
□34 a
AD
□ □
LDY
#$□□
jinitialize Y
□ □□5
□ 344
CB
REPEAT:
INY
;times loop has repeated
□ □□□
□ 345
EA
NOP
;misc instructions
□ □□?
□ 341
CA
DEX
jdecrement X
□□□a
□ 347
DO
FB
BNE
REPEAT
;if X not equal to □ then
□□□3
□ 343
; branch back to start of
□ □10
□ 343
; loop
□ □ii
□ 343
□ □
BRK
; stop
□ DIE
□ 34 A
□ □13
□ 34 A
.END
Fig. 22-5 A backward conditional jump creating a loop
with the 6502 microprocessor.
Chapter 22 Branching and Loops 345
Pay special attention to the X register, the Y register, and
the zero flag.
Compare Instructions
The compare instructions allow us to compare the values
in two registers and/or memory locations, and to set the
flags accordingly, without changing either of the original
values. The appropriate branch instruction can then cause
program execution to continue at the desired location. The
program in Fig. 22-6 will allow you to observe the compare
instructions.
The program simply loads the value 05 16 into the accu¬
mulator and compares the numbers 04 16 , 06 16 , and 05 16 to
it. If you will refer to the Expanded Table of 6502
Instructions and look in the Operation column, you will
see what we mean by “compare.”
To “compare” means to subtract the number you are
“comparing” from the number being “compared to.” For
example, line 0004 of the program in Fig. 22-6 sets the
flags as though 04 l6 had been subtracted from 05 16 , without
actually changing the value in the accumulator.
Lines 0005 and 0006 likewise subtract 06 16 and 05 16 ,
respectively, from the value in the accumulator without
altering the accumulator.
A point needs to be made at this time about the carry
flag in the 6502 microprocessor. Most microprocessors set
a flag (value of 1) to say, “Yes, this condition exists.”
For example, setting the zero flag (value of I) means,
“Yes, the last value (or current value) is a zero.” When a
flag is reset (value of zero) it means “No, this condition
does not exist.”
The 6502 handles the carry flag in an unusual way. It is
inverted. After addition this flag will appear as expected.
A 1 means that a carry occurred, and a 0 means that a
carry did not occur. After subtraction, however, a 1 means
that a borrow did not occur, and a 0 means that a borrow
did occur. Be careful to remember this exception when
using 6502 compare instructions to prepare for branch
instructions.
This program’s only purpose is to allow you to see how
the flags are affected by each compare instruction. Enter
the program and single-step through it. Watch the flags
after each instruction and make sure that you understand
why they react the way they do.
An Example Program
We’ll now look at an example program which uses a com¬
pare instruction, increment instructions, and a conditional
branch instruction. This program looks at two numbers in
memory, determines which is larger, and then places the
larger value in a third memory location. It also uses a form
of indexed addressing. Refer to Fig. 22-7 at this time.
After entering this program into your computer or trainer,
but before running it, you must place values of your choice
into the two memory locations indicated in the notes at the
beginning of the program.
This program uses the X register to help point to the
next memory location to load a number from or store a
number in. The first instruction in line 0008 initializes the
X register with a value of 00 16 .
Memory location 03A0 16 is the beginning of a series of
memory locations which this program uses. A common
way to address successive memory locations is to use some
form of indexed addressing. Location 03A0 16 is the begin¬
ning of the list, and the X register will point to each
successive number in the list. In line 0009 we load the
accumulator with the first number from the list. The memory
location of this number is formed by adding 03A0 16 to the
value of the X register, which is 00 16 at this moment, to
form the address of the first number in the list, in location
03A0 16 .
In line 0010 we increment the X register to a value of
01 16 so that it points to the next number.
In line 0011 we compare the value held in memory
location 03A1 16 to the value in the accumulator. If the value
in the accumulator is larger, then no borrow will be needed
to perform the comparison (which involves subtraction).
Therefore the carry flag will be set.
We find in line 0012 that, if the carry flag is set, then
we branch forward to line 0014. This will be the case if
the value in the accumulator is the larger value. In line
0014 the X register is incremented so that it points to the
last memory location. In line 0015 we store the value now
in the accumulator in that final memory location.
If during the comparison in line 0011 the value in the
accumulator is smaller, a borrow is required to perform the
comparison (involving subtraction) and the carry flag is
cleared. In line 0012 the carry flag is not set and the branch
does not occur. Therefore, the next instruction in line 0013
is executed. This instruction loads the second number into
□ □Dl
□ 34D
.org $D34□
□ □□5
□ 34D
□ □□3
□ 340
A3
□ 5
START:
LDA
□ □□4
□ 342
C3
□ 4
CMP #$D4
□ □□5
□ 344
C9
□ b
CMP *$Db
□ □□b
□ 34 b
C9
□ 5
CMP #$05
□ 0 □?
□ 34 A
□ □
BRK
OOOfl
□ 34 3
□ □□4
□ 343
. end
Fig. 22-6 Using the compare instruction.
initial value
compare each of these numbers
to A and set flags as though
each had been subtracted from A
346 Digital Computer Electronics
□ 001
□ □□e
□ □03
□ □□4
□ □□5
□ not
□ □□?
□ □□□
□ ODD
□ □□□
□ 000
0000
□ 34D
□ 34D
;place a number in memory location $0340 and another in $D3A1,
, this program will determine which is larger and place
, the larger in location $03AE (Note: Do not use two
; numbers which are equal.)
.org $D34 0
□ □□A
□ 340
AE
□ □
START:
LDX
#$00
□ □□3
□ 34 E
BD
AD
□ 3
LD A
$03A0 , X
□ 010
0345
EA
I NX
□ on
□ 341
DD
AD
□ 3
CMP
$03 A0 , X
□ DIE
□ 34 3
BD
□ 3
BCS
FOUND
□ 013
034B
BD
AD
03
LDA
$03A0, X
□ 014
034E
EA
FOUND:
INX
0015
034F
3D
A0
03
STA
$03A0, X
□ □It
035E
□ □
BRK
0017
□ 353
001A
□ 353
.end
;initialize X register
I load A from mem 03AD + □□ = 03AD
;point to next mem loc
;compare data in mem D3AD +
□1 = D3A1 to A
;if A is larger jump forward to Found;
; otherwise load A from mem 03A0 +
□1 = 03A1
;point to next mem loc
;store A in mem 03A0 + 0E = 03A3
; stop
Fig. 22-7 An example 6502 program.
the accumulator. Obviously, if the first number is not the
larger, the second one must be. After loading the accu¬
mulator with the second number in line 0013, we continue
in lines 0014 and 0015 to store that value in the third
memory location.
This program will give you an idea how to use some of
the new instructions in this chapter and how to use indexed
addressing.
22-7 6800/6808 FAMILY
The 6800/6808 microprocessor family has a variety of
instructions to handle unconditional jumps and branches,
conditional branching, comparing, incrementing, and dec¬
rementing. We’ll look at several tasks and see how the
6800/6808 microprocessor handles them.
You should enter each program into your computer or
microprocessor trainer and single-step through it, watching
the appropriate registers, memory locations, and flags to
understand how each program works.
Unconditional Jumps
The forward unconditional jump using extended addressing
is probably easiest to understand. An example is shown in
Fig. 22-8.
(Technical Note: We have started this program at address
0100 16 rather than our usual 0000 16 . Addresses from 0000 16
to 00FF, 6 form page 0 of memory. Some instructions can
use direct addressing, if the desired location is on page 0,
or extended addressing, if the desired location is on a
memory page other than page 0. Our particular assembler
had trouble handling forward references on page 0. Switch¬
ing to a page other than page 0 provided a simple solution
to this problem.)
The program begins by loading accumulator A with FF 16 .
In a moment we are gong to subtract another number from
this one. First we need to jump to the area of memory
where the subtract instruction is. We have placed the
subtract instruction several memory locations forward from
this point to show, in a very simple manner, how the
unconditional jump instruction operates.
0001
□ !□□
. org
$□!□□
□ DDE
□ 100
□ 003
□ 100
At
FF
START:
LDA A
*$FF
0004
010E
7E
01
□ A
JMP
MINUS
□ □□5
□ 105
□ 1
NOP
□ oot
□ IDt
□ 1
NOP
□ 007
□ 107
□ 1
NOP
□ □□A
□ IDA
A0
EE
MINUS:
SUBA
#$EE
□ □□3
□ 10 A
B7
□ 1
□ E
ST A A
ANSWER
0010
□ 1DD
3E
WAI
□ □11
010E
□ □IE
□ 10E
00
ANSWER
.db
$□□
□ □13
□ IDF
□ □14
□ 10F
. end
Fig. 22-8 Forward unconditional jump with the 6800/6808
microprocessor. (Note that address is $0100 rather than
$0000. This prevents an assembler error caused by a
forward reference to a label on zero page.)
;beginning of code
;minuend
;forward unconditional jump
;misc. instructions
;subtrahend
;store difference
; stop
;memory area for answer
; (initialized to □□)
Chapter 22 Branching and Loops 347
The next instruction is our jump instruction. In the source
code column of line 0004 the instruction
JMP MINUS
appears, which might be different than what you were
expecting.
The instruction is saying to jump to a place called
MINUS. To be able to jump to a place with a certain name
is not a native ability of the 6800/6808 microprocessor.
Our assembler is making this possible. Line 0008 has the
label MINUS in the label column. This is the place we
want to jump to. Notice the address at the MINUS label.
The address is 0108. Now look back at line 0004. In the
op code column you see 7E, which is the op code for an
unconditional jump. Then come the numbers 01 08. This
is the memory location of the instruction labeled MINUS.
If you use an assembler, you can use labels and the
assembler will calculate the address for you. If you are
hand-assembling these programs, you must enter the address
as shown in the op code column. If you are using an
assembler which does not allow labels, you will need to
use the format shown in the 6800/6808 instruction-set
tables. Namely
JMP $0108
After the jump instruction are several NOPs which could
be other instructions or just unused memory in a particular
microprocessor system.
In line 0008 we subtract EE 16 from FF 16 (in accumulator
A). In line 0009 we store the result of our subtraction in a
memory location called ANSWER. Look at line 0012,
labeled ANSWER. In the op code column are the initials
.db. They stand for define byte. We are telling the assembler
to reserve a memory location, namely, a single byte of
memory, with the name ANSWER. The assembler is
initializing the memory location ANSWER with a value of
0. Our program can then put any other number we wish in
that location.
Notice also that the memory location of ANSWER is
010E 16 . In the op code column of line 0009 we see B7 01
0E. The op code for storing the value of the accumulator
in a certain memory location is B7. 010E is the memory
location of ANSWER. Again, the assembler made life
simpler by figuring out where the next available memory
location would be and setting aside that location for the
ANSWER.
Finally, in line 0010 the program stops.
You should enter this program and single-step through
it, making sure everything works as described.
Conditional Branches
Now let’s see an example of conditional branching. Figure
22-9 shows such an example.
In this program we are going to do several things
differently from the way they were done in the last program.
First, we are using a conditional jump or branch rather than
an unconditional one. Second, we are branching backward
rather than forward. Third, we are creating a loop by
branching backward and repeating a section of the program.
Finally, we are using a register as a counter to control how
many times the loop repeats.
In line 0003 we place the number 3 ]6 in the X register.
This register controls how many times we will branch
backward. In line 0004 we clear accumulator B, making it
00 16 so that it can be used to count how many times the
loop repeats.
Line 0005 marks the beginning of the loop, and we have
named that location REPEAT. In this line we increment
accumulator B since we are beginning to pass through the
loop, in this case for the first time. Accumulator B is
keeping track of how many times the loop is passed through.
Line 0006 represents the fact that there could be many
instructions inside this loop which are going to be repeated.
Line 0007 decrements (reduces by 1) the X register. The
X register keeps track of how many times to go through
the loop remain.
Line 0008 is where we meet our conditional branch
instruction. BNE means Branch if Not Equal. Your first
thought might be, “Not equal to what?” If you check the
Expanded Table for the 6800/6808, you’ll see that it is
Branch if Not Equal to 0.
□ □□1
□ ODD
.ORG $□□□□
□ □□5
□ □00
□ 003
□ □□□
CE
□ □ 03
START:
LDX #$DDD3
; initialize X (repeats)
□ 004
□ 003
Ct
□ 0
LDAB *$00
initialize B
0005
□ □□5
5C
REPEAT:
INCB
;times loop has repeated
□ 000
□ □□£>
□ 1
NOP
;misc. instructions
0007
□ □07
□ 3
DEX
;decrement X
□ □□a
□ □□a
E0
FB
BNE REPEAT
;iT X not equal to □ then
□ □□3
□ □□A
; branch back to start of
0010
□ □□A
; loop
□ Oil
□ □□A
3E
WAI
; stop
ooia
□ DOB
□ 013
□ 00B
.END
Fig. 22-9 A backward conditional jump creating a loop
with the 6502 microprocessor.
348 Digital Computer Electronics
All the conditional branch instructions are influenced by
the most recent instruction that affected the flag they check.
In this case the zero flag is checked. What was the last
instruction which sets or clears the zero flag? The DEX
(DEcrement X register) instruction. If the X register was
reduced to 0, the zero flag would be set. Has the X register
been reduced to 0? On this first pass through the loop, it
gets reduced from 3 to 2. No, the X register is not equal
to 0.
The branch instruction says, “Branch if Not Equal to
0.” Clearly this is true: the last result is not 0, so we
branch. Branch to where? We branch to the memory location
known as REPEAT. Notice that the location called RE¬
PEAT, in line 0005, is memory location 0005 16 . Now look
again at line 0008. The op code for the BNE instruction is
26, and FB is where it’s branching to. Is FB the memory
location of REPEAT? No. The BNE instruction uses relative
addressing. FB ]6 is a negative-signed binary number telling
us how many places to move from where we are now. FB 16
is 5 10 . We must branch five memory locations backward
from memory location 000A 16 .
It will be helpful to enter this program into your computer
or microprocessor trainer and single-step through it. Pay
special attention to the X register, accumulator B, and the
zero flag.
Compare Instructions
The compare instructions allow us to compare the values
in two registers and/or memory locations and to set the
flags accordingly without changing either of the original
values. The appropriate branch instruction can then cause
program execution to continue at the desired location. The
program in Fig. 22-10 allows you to observe how the
compare instructions work.
The program simply loads the value 05 16 into accumulator
A and compares the numbers 04, 6 , 06 16 , and 05 16 to it. If
you refer to the Expanded Table of 6800/6808 Instructions
and look in the Operation column, you will see what we
mean by “compare.”
To “compare” means to subtract the number you are
comparing” from the number being “compared to.” For
example, line 0004 of the program in Fig. 22-10 sets the
flags as though 04 16 had been subtracted from 05 16 , in
accumulator A, without actually changing the value in the
accumulator.
□□□1
□ □□□
. org
$□□□□
□ □□2
□ □□□
□ 003
□ □□□
fib
□ 5
START:
LDAA
#$□5
□ □04
□ □□2
A1
□ 4
CMPA
#$04
□ □05
□ □□4
A1
□ t
CMP A
ft $ G b
□ □□□
□ □□t,
A1
□ 5
CMPA
ft$us
□ □□?
□□□a
3E
WAI
□ □□A
□ □□3
□ □05
□ □□5
. end
Fig. 22-10 Using the compare instruction.
Line 0005 and 0006 likewise subtract 06 16 and 05 16 ,
respectively, from the value in accumulator A without
altering the accumulator.
This program’s only purpose is to allow you to see how
the flags are affected by each compare instruction. Enter
the program and single-step through it. Watch the flags
after each step and make sure that you understand why they
react the way they do.
An Example Program
We’ll now look at an example program which uses a
compare instruction, increment instructions, and a condi¬
tional branch instruction. This program looks at two numbers
in memory, determines which is larger, and then places the
larger value in a third memory location. It also uses a form
of indexed addressing. Refer to Fig. 22-11 at this time.
After entering this program into your computer or trainer
but before running it, you must place values of your choice
into the two memory locations indicated in the notes at the
beginning of the program.
This program uses the X register to help point to the
next memory location to load a number from or store a
number in. The first instruction in line 0008 initializes the
X register with a value of 01A0 16 .
Memory location 01A0 16 is the beginning of a series of
memory locations which this program uses. A common
way to address successive memory locations is to use some
form of indexed addressing. Location 01A0 16 is the begin¬
ning of the list, and the X register will point to each
successive number in the list. In line 0009 we load the
accumulator with the first number from the list. The memory
location of this number is formed by adding 00 16 to the
value in the X register, which is 01A0 16 , to form the address
of the first number in the list, at location 01A0 16 .
In line 0010 we increment the X register to a value of
01A1 16 so that it points to the next number.
In line 0011 we compare the value held in memory
location 01A1 16 to the value in accumulator A. If the value
in the accumulator is larger, then no borrow will be needed
to perform the comparison (which involves subtraction).
Therefore the carry flag will be clear.
We find in line 0012 that, if the carry flag is clear, then
we branch forward to line 0014. This will be the case if
the value in the accumulator is the larger value. In line
0014 the X register is incremented, so it points to the last
initial value
compare each of these numbers
to A and set flags as though
each had been subtracted from A
Chapter 22 Branching and Loops 349
□□□1
□□□□
; place
a number in memory location $Q1AD and another in $D1A1;
nan?
□□□□
; this
program will
determine which is larger and place
□ ana
□ □□□
; the
larger in location $D1A? (Note: Do not use two
□ □□4
□□□□
; numbers which are
equal.)
□ nan
□ □□□
□ nan
□ i □ □
.org $□!□□
□ □□?
□ i □ □
□ □□A
□i □ □
CE
□ 1 AD
START:
LDX #$□!AD
;initialize X register
□ nan
□ 1D3
At
□ □
LDAA $□□,X
;load A from mem 01AD + □□ = D1AD
ama
□ 1D5
□ A
INX
;point to next mem loc
ami
□ IQ t
A1
□ □
CMPA $□□/X
;compare data in mem Q1AD + □□ -
□1A1 to A
□ □15
□ IQfl
54
□ 5
BCC FOUND
;if A is larger jump forward to Found
□ □in
□ IGA
At
□ □
LDAA $□□ f X
; otherwise load A from mem D1A1 +
□□ = D1A1
□ Q14
□ 1 DC
□ A
FOUND :
INX
;point to next mem loc
□ □15
□ 1DD
A?
□ □
STAA $□□ ,X
;store A in mem D1A5 + □□ = D1A5
□ nib
□ IDF
3E
WAI
; stop
□ □17
QUO
□aifl
□ 11"
. end
Fig. 22-11 An example 6800/6808 program.
memory location. In line 0015 we store the value now in
accumulator A in that final memory location.
If, during the comparison in line 0011 the value in the
accumulator is smaller, a borrow is required to perform the
comparison (involving subtraction) and the carry flag is set.
In line 0012 the carry flag is not clear and the branch does
not occur. Therefore, the next instruction in line 0013 is
executed. This instruction loads the second number into the
accumulator. Obviously, if the first number is not the larger,
the second one must be. After loading accumulator A with
the second number in line 0013, we continue in lines 0014
and 0015 to store that value in the third memory location.
This program will give you an idea how to use some of
the new instructions in this chapter and how to use indexed
addressing.
22-8 8080/8085/Z80 FAMILY
The 8080/8085/Z80 microprocessor family has a variety of
instructions to handle unconditional jumps, conditional
branching, comparing, incrementing, and decrementing.
We’ll look at several tasks and see how the 8080/8085/Z80
microprocessor handles them.
You should enter each program into your computer or
microprocessor trainer and single-step through it, watching
the appropriate registers, memory locations, and flags to
understand how each program works.
Remember that we will show both 8080/8085 and Z80
programs in the figures and that in the text we will show
8080/8085 mnemonics first with Z80 mnemonics in
brackets.
Unconditional Jumps
The forward unconditional jump using direct addressing is
probably easiest to understand. An example is shown in
Fig. 22-12.
The program begins by loading the accumulator with
FF 16 . In a moment we are going to subtract another number
from this one. First we need to jump to the area of memory
where the subtract instruction is. We have placed the
subtract instruction several memory locations forward from
this point to show, in a very simple manner, how the
unconditional jump instruction operates.
The next instruction is our jump instruction. In the source
code column of line 0004 the instruction
JMP MINUS [JP MINUS]
appears, which might be different than what you were
expecting.
The instruction is saying to jump to a place called
MINUS. To be able to jump to a place with a certain name
is not a native ability of the 8080/8085/Z80 microprocessor.
Our assembler is making this possible. Line 0008 has the
label MINUS in the label column. This is the place we
want to jump to. Notice the address at the MINUS label.
The address is 1808. Now look back at line 0004. In the
op code column you see C3, which is the op code for an
unconditional jump. Then come the numbers 08 18. If you
reverse these two sets of numbers, you have 1808. This is
the memory location of the instruction labeled MINUS. If
you use an assembler, you can use labels and the assembler
will calculate the address for you. If you are hand-assembling
these programs, you must enter the address as shown in
the op code column, in the reverse low-byte/high-byte
order. If you are using an assembler which does not allow
labels, you will need to use the format shown in the 8080/
8085/Z80 instruction-set tables. Namely
JMP aaaa [JP aaaa]
After the jur n instruction are several NOPs which could
be other instructions or just unused memory in a particular
microprocessor system.
350 Digital Computer Electronics
ADAD/ADA5 program
□ □□1
1A 0 □
.org lAOOh
;beginning of code
□ □□a
1A □□
□ □□3
1A □ □
3E
FF
START:
MVI A,DFFh
;minuend
□ □□4
1A0E
C3
□ A
1A
JMP MINUS
;forward unconditional jump
□ □□5
1AD5
□ □
NOP
□ 00b
lAOb
□ □
NOP
;misc. instructions
0007
1A07
□ □
NOP
□ □□A
1 ADA
Db
EE
MINUS:
SUI DEEh
;subtrahend
□ □09
1ADA
3E
0E
1A
STA ANSWER
;store difference
□ 010
1 ADD
7b
HLT
; stop
□ □11
1ADE
□ □IE
1A0E
□ □
ANSWER
.db DDh
;memory area for answer
□ □13
1ADF
; (initialized to 00)
□ □14
1A0F
. end
ZAO ]
program
□ □□1
1A 00
.org lADDh
;beginning of code
0005
1A00
□ □□3
1 ADD
3E
FF
START:
LD A,DFFh
;minuend
□ □□4
1A0E
C3
□ A
1A
JP MINUS
;forward unconditional jump
□ □□5
1AQ5
□ □
NOP
000b
1 A0b
□ □
NOP
;misc. instructions
0007
1AQ7
00
NOP
□ □□A
1AQA
Db
EE
MINUS:
SUB DEEh
; subtrahend
□ □□9
1A0 A
3E
□ E
1A
LD (ANSWER),A
;store difference
0010
1A0D
7b
HALT
; stop
□ □11
1A0E
□ □IE
1A0E
□ □
ANSWER
.db D0h
;memory area for answer
□ □13
1ADF
; (initialized to 00)
□ 014
1AQF
.end
Fig. 22-12 Forward unconditional jump with the 8080/8085/
Z80 microprocessor.
In line 0008 we subtract EE 16 from FF 16 (in the accu¬
mulator). In line 0009 we store the result of our subtraction
in a memory location called ANSWER. Look at line 0012,
labeled ANSWER. In the op code column are the initials
.db. They stand for define byte . We are telling the assembler
to reserve a memory location, namely, a single byte of
memory, with the name ANSWER. The assembler is
initializing the memory location ANSWER with a value of
0. Our program can then put any other number we wish in
that location.
Notice also that the memory location of ANSWER is
180E ]6 . In the op code column of line 0009 we see 32 0E
18. The op code for storing the value, of the accumulator
in a certain memory location is 32. If you reverse 0E 18,
you have 180E, which is the memory location of ANSWER.
Again the assembler made life simpler by figuring out
where the next available memory location would be and
setting aside that location for the ANSWER.
Finally, in line 0010, the program stops.
You should enter this program and single-step through
it, making sure that everything works as described.
Conditional Branches
Now let’s see an example of conditional branching. Figure
22-13 shows such an example.
In this program we are going to do several things
differently from the way they were done in the last program.
First, we are using a conditional jump or branch rather than
an unconditional one. Second, we are branching backward
rather than forward. Third, we are creating a loop by
branching backward and repeating a section of the program.
Finally, we are using a register as a counter to control how
many times the loop repeats.
In line 0003 we place the number 3 16 in register B. This
register controls how many times we will branch backward.
In line 0004 we clear register C making it 00, 6 so that it
can be used to count how many times the loop repeats.
Line 0005 marks the beginning of the loop, and we have
named that location REPEAT. In this line we increment
register C since we are beginning to pass through the loop,
in this case for the first time. Register C is keeping track
of how many times the loop is passed through. Line 0006
represents the fact that there could be many instructions
inside this loop which are going to be repeated.
Line 0007 decrements (reduces by one) register B.
Register B keeps track of how many times we have left to
go through the loop.
Line 0008 is where we meet our conditional branch
instruction. JNZ means Jump if Not Zero. [JP NZ means
JumP if Not Zero.] Your first thought might be, “If what
isn’t zero?”
Chapter 22 Branching and Loops 351
ADAD/ADA5 program
□ □□1
1 ADD
.ORG
lADDh
□ ODE
1A0D
□ □□3
1 ADD
□ b
□ 3
START:
M VI
B, D3h
;initialize B (repeats)
□ □□4
1ADE
□ E
□ □
M VI
C, DDh
;initialize C
□ □□3
1A D4
□ C
REPEAT:
INR
C
;times loop has repeated
□ □□b
1A D 5
□ □
NOP
;misc instructions
□ □□?
1 ADb
□ 5
DCR
B
decrement B
□ □□A
1AD?
CE
□ 4 1A
JNZ
REPEAT
;if B not equal to □ then
□ □□3
1 ADR
; branch back to start of
□ DID
1 ADR
; loop
□ □11
1 ADR
?b
HLT
; stop
□ □IE
1ADB
□ □13
1ADB
.END
ZAD program
0D01
1 ADO
.ORG lAODh
□ DDE
1ADD
□ □□3
1 ADD
0b
D3
START:
LD B/D3h
;initialize B (repeats)
□ 004
1ADE
0E
□ D
LD C/DDh
initialize C
□ □□5
1AD4
DC
REPEAT:
INC C
;times loop has repeated
□ □□b
1AD5
□ D
NOP
;misc instructions
□ □□?
1 AOb
□ 5
DEC B
; decrement B
□ □□A
1A □?
CE
□ 4 1A
JP NZ,REPEAT
;if B not equal to □ then
□ □□3
1 AD A
; branch back to start of
□ □ID
1 AD A
; loop
□ □11
1 ADR
7b
HALT
; stop
□ □IE
1ADB
□ □13
1ADB
.END
Fig. 22-13 A backward conditional jump creating a loop
with the 8080/8085/Z80 microprocessor.
All the conditional branch instructions are influenced by
the most recent instruction that affected the flag they check.
In this case the zero flag is checked. What was the last
instruction which sets or clears the zero flag? The DCR B
(DeCRement B) [DEC B (DECrement B)] instruction. If
register B were reduced to 0, the zero flag would be set.
Has register B been reduced to zero? On this first pass
through the loop, it gets reduced from 3 to 2. No, register
B is not equal to 0.
The jump instruction says, “Jump if not zero.” Clearly
this is true: the last result is not 0, so we do jump. Jump
to where? We jump to the memory location known as
REPEAT. Notice that the location called REPEAT, in line
0005, is memory location 1804 16 . Now look again at line
0008. C2 is the op code for the JNZ [JP NZ] instruction.
If you reverse the two sets of numbers 04 18, you form
1804, which is the memory location of the REPEAT label.
It will be helpful to enter this program into your computer
or microprocessor trainer and single-step through it. Pay
special attention to register B, register C, and the zero flag.
Compare Instructions
The compare instructions allow us to compare the values
in two registers and/or memory locations and to set the
flags accordingly without changing either of the original
values. The appropriate jump instruction can then cause
program execution to continue at the desired location. The
program in Fig. 22-14 allows you to experiment with the
compare instructions.
This program loads the value 05 16 into the accumulator
and compares the numbers 04 16 , 06 16 , and 05 16 to it. If you
will refer to the Expanded Table of 8080/8085/Z80 Instruc¬
tions and look in the Operation column, you will see what
we mean by “compare.”
To “compare” means to subtract the number you are
comparing from the number being “compared to.” For
example, line 0004 of the program in Fig. 22-14 sets the
flags as though 04 16 had been subtracted from 05 16 , without
actually changing the value in the accumulator.
Lines 0005 and 0006 likewise subtract 06 16 and 05 16 ,
respectively, from the value in the accumulator without
altering the accumulator.
This program’s only purpose is to allow you to see how
the flags are affected by each compare instruction. Enter
the program and single-step through it. Watch the flags
after each step and make sure you understand why they
react the way they do.
An Example Program
We’ll now look at an example program which uses a
compare instruction, increment instructions, and a condi-
352 Digital Computer Electronics
ADAD/AOAS program
□ □□1
1A □□
.org lADDh
□ □02
1 ADD
□ □□3
1A 0 □
3E
□ 5
START:
MVI A, 05h
□ □□4
1 ADD
FE
□ 4
CPI 04h
□ □□5
1A D4
FE
□ t
CPI Dbh
□ □□£>
1ADL
FE
□ 5
CPI D5h
□ □□?
1 AD A
7b
HLT
□ □□A
1AD9
□□□q
1A09
.end
ZAO program
□ □□1
1 ADD
.org lAOOh
□ □□2
1 ADD
□ □□3
1 ADD
3E
□ 5
START:
LD A,D5h
□ □□4
1 ADD
FE
□ 4
CP 04h
□ □□5
1A D4
FE
□ b
CP 0bh
□ DDL
1 ADD
FE
□ 5
CP 05h
□ □□7
1 AD A
70
HALT
□ □□A
1A 09
□ 003
1A D9
. end
Fig. 22-14 Using the
compare instruction.
initial value
compare each of these numbers
to A and set flags as though
each had been subtracted from A
initial value
compare each of these numbers
to A and set flags as though
each had been subtracted from A
tional branch instruction. This program looks at two numbers
in memory, determines which is larger, and then places the
larger value in a third memory location. It also uses register
indirect addressing. Refer to Fig. 22-15 at this time.
After entering this program into your computer or trainer,
but before running it, you must place values of your choice
into the two memory locations indicated in the notes at the
beginning of the program.
This program uses the HL register pair to help point to
the next memory location to load a number from or store
a number in. The first instruction in line 0008 initializes
the HL register pair with a value of 18A0 16 .
Memory location 18A0 16 is the beginning of a series of
memory locations which this program uses. A common
way to address successive memory locations is to use some
form of indexed addressing. The 8080/8085 does not actually
have an index register; however, the HL register pair can
be used with register indirect addressing to accomplish
much the same thing. Location 18A0 16 is the beginning of
the list, and the HL register pair will point to each successive
number in the list. In line 0009 we load the accumulator
with the first number from the list. The memory location
of this number is pointed to by the value in the HL register
pair.
In line 0010 we increment the HL register pair to a value
of 18A1 16 so that it points to the next number.
In line 0011 we compare the value held in memory
location 18A1 16 to the value in the accumulator. If the value
in the accumulator is larger, then no borrow will be needed
to perform the comparison (which involves subtraction).
Therefore the carry flag will be clear.
We find in line 0012 that, if the carry flag is clear, then
we branch forward to line 0014. This will be the case if
the value in the accumulator is the larger value. In line
0014 the HL register pair is incremented so that it points
to the last memory location. In line 0015 we store the value
now in the accumulator in that final memory location.
If, during the comparison in line 0011 the value in the
accumulator is smaller, a borrow is required to perform the
comparison (involving subtraction) and the carry flag is set.
In line 0012 the carry flag is not clear and the branch does
not occur. Therefore the next instruction in line 0013 is
executed. This instruction loads the second number into the
accumulator. Obviously, if the first number is not the larger,
the second one must be. After loading the accumulator with
the second number in line 0013, we continue in lines 0014
and 0015 to store that value in the third memory location.
This program will give you an idea how to use some of
the new instructions in this chapter and how to use register
indirect addressing.
22-9 8086/8088 FAMILY
The 8086/8088 microprocessor family has a variety of
instructions to handle unconditional jumps, conditional
branching, comparing, incrementing, and decrementing.
We’ll look at several typical tasks and see how the 8086/
8088 microprocessor handles them.
You should enter each program into your computer or
microprocessor trainer and single-step through it, watching
the appropriate registers, memory locations, and flags to
understand how each program works.
Chapter 22 Branching and Loops 353
ADAD/ADA5 program
□ □□1
□□□□
; place
a number in memory location lAADh and another
in lAAlh
□ DDE
□□□□
; this
program will
determine which is
larger and
place
□ □□3
□ □□□
; the
larger in location lAAEh (Note:
Do not use
two
□ DDZ
□□□□
; numbers which are
equal.)
□ □□5
□ □□□
□ □□b
1 ADD
* org
1A □ □ h
□ □□?
1 ADD
□ □□A
1ADD
El
AD
ia
START:
LXI
H,lAADh
;initialize HL
register
□□□q
1AD3
7E
MOV
A, M
;load A from mem IAAO
□ DID
1ADZ
E3
INX
H
;point to next
mem loc
□ □ii
IADS
BE
CMP
M
;compare data in mem 1AA1
to
A
□ die
1A Db
DE
□ A
1A
JNC
BOUND
;if A is larger
jump forward
to Bound
□ □13
lAoq
7E
MOV
A f M
; otherwise load A from mem
1AA1
□ □1Z
1 ADR
E3
BOUND :
INX
H
;point to next
mem loc
□ □IS
1A DB
77
MOV
M, A
;store A in mem
IA AE
□ nib
1A DC
7b
HLT
; stop
□ □17
1 ADD
□□Ifl
1ADD
.end
ZAD program
□ □□1
□ □□□
;place a number in memory location lAADh and another in lAAlh
□ □□E
□ □□□
; this program will
determine which is larger and place
□ □□3
□ □□□
; the larger in location lAAEh (Note: Do not use two
□ DOZ
□ □□□
; numbers which are
equal.)
□ □□5
□ □□□
□ □□b
1 ADD
.org lAODh
□ □□7
1 ADD
□ □□A
1 ADD
El
AD
IA
START: LD HL,lAADh
;initialize HL register
□ □□3
1A03
7E
LD A,(HL)
;load A from mem 1AAD
□ DID
1 ADZ
E 3
INC HL
;point to next mem loc
□ □11
IADS
BE
CP (HL)
;compare data in mem 1AA1 to A
□ □IE
1A Db
DE
□ A
IA
JP NC,BOUND
;if A is larger jump forward to Bound
□ □13
1A □□
7E
LD A,(HL)
; otherwise load A from mem 1AA1
□ □1Z
1 AD A
E3
FOUND: INC HL
;point to next mem loc
□ □15
1ADB
77
LD (HL),A
;store A in mem 1AAE
□ □lb
1 ADC
7b
HALT
; stop
□ □17
1 ADD
□ □IA
1 ADD
.end
Fig. 22-15 An example 8080/8085/Z80 program.
Using An Assembler
We need to explain a few things about using an assembler
with the 8086/8088 microprocessor. Look at Fig. 22-16 for
a moment. The
page ,132
command tells the assembler to create a list file (Fig. 22-
lb is a list file) that is up to 132 columns wide. This gives
us more room for the comments at the ends of the lines.
The top portion above the program, which reads
CODE SEGMENT
ASSUME CS:CODE, DS:CODE, SS:CODE
ORG lOOh
and the bottom portion, which reads
CODE ENDS
END START
are required by the assembler. This information has to do
with where in memory we want the program to be and how
we want to handle memory segmentation. This model
allows the program to be assembled and linked to form an
.EXE file which can then be converted to a .COM file with
the EXE2B1N DOS utility. A complete discussion of these
concepts is beyond the scope of this text. If you will use
this model, however, you will be able to use DEBUG to
examine the file and use the trace command to single-step
through it.
After you assemble and link the file, use the EXE2BIN
354 Digital Computer Electronics
1
E
3 □□□□
4
5 D1DD
L
? □ i □ n
A D10E
3 0104
ID 01D5
11 0105
IE
13 0103
14 nine
15
it niDE
17
1A
13 D1DF
En
El
BD
FF
EB
D3
3D
3D
3D
EC
EE
AE
D1DE R
CD
ED
DD
page ,
13 E
CODE
SEGMENT
ASSUME CS:CODE,
ORG
lODh
START:
MOV
AL,OFFh
JMP
SHORT MINUS
NOP
NOP
NOP
MINUS:
SUB
AL,DEEh
MOV
ANSWER,AL
INT
EOh
ANSWER
DB
□ Dh
CODE
ENDS
END
STA
DS:CODE, SSrCODE
;minuend
jforward unconditional jump
;misc. instructions
;subtrahend
;store difference
; stop
;memory area for answer
; (initialized to □)
Fig. 22-16 Forward unconditional jump with the 8086/8088
microprocessor (using an assembler).
utility to change it to a .COM file. Then load the file
(filename.ext) by typing
debug filename.ext
at the DOS prompt.
Unconditional Jumps
The forward unconditional jump using direct addressing is
probably the easiest to understand. Look again at Fig.
22-16. The same program entered with DEBUG is shown
in Fig. 22-17.
The program begins by loading AL with FF 16 . In a
moment we are going to subtract another number from this
one. First we need to jump to the area of memory where
the subtract instruction is. We have placed the subtract
instruction several memory locations forward from this
point to show, in a very simple manner, how the uncon¬
ditional jump instruction operates.
ODEBUG
-r
AX=Q000
DS=3F3D
-a
BX-0000 CX-0000 DX—□□□□ SP=FFEE BP=000D SI=0000 DI=00DD
ES=3F3D SS=3F3D CS=3F3D IP D1DD NV UP El PL NZ NA PO NC
3F3D:010E
BDFF
MOV AL,FF
MOV
AL, FF
;minuend
JMP
D107
;forward unconditional jump
NOP
NOP
;misc. instructions
NOP
SUB
AL, EE
;subtrahend
MOV
[□IDE]
/AL ;store difference
INT
ED
; stop
-u lOd
3F3D:010D BDFF
3F3D:010E EBD3
3F3D:DICK 3D
3F3D:0105 3D
3F3D:010b 3D
3F3D:Q1D7 ECEE
3F3D:D1D3 AEDED1
3F3D:D1DC CDED
MOV AL,FF
JMP D1D7
NOP
NOP
NOP
SUB AL,EE
MOV [D1DE]/AL
INT ED
Fig. 22-17 Forward unconditional jump with the 8086/8088
microprocessor (using DEBUG).
Chapter 22 Branching and Loops 355
The next instruction is our jump instruction. In the
source-code column of line 8 in Fig. 22-16 the instruction
JMP SHORT MINUS
appears, which might be different from what you were
expecting.
The instruction is saying to jump to a placed called
MINUS. To be able to jump to a place with a certain name
is not a native ability of the 8086/8088 microprocessor.
Our assembler is making this possible. Line 12 has the
label MINUS in the label column. This is the place we
want to jump to. Notice the address at the MINUS label.
The address is 0107. Now look back at line 8. In the op
code column you see EB, which is the op code for an
unconditional jump. Then comes the number 03. This is
the number of memory locations by which we must move
forward from the instruction after the JMP instruction.
Moving forward 03 places takes us to memory location
0107. This is the memory location of the instruction labeled
MINUS. If you use an assembler, you can use labels and
the assembler will calculate the relative address for you.
The term SHORT tells the assembler that this place called
MINUS is within 127 bytes of our current location.
If you are using DEBUG to assemble these programs,
you must enter the program as shown in Fig. 22-17. Toward
the top of Fig. 22-17 we simply say
JMP 0107
Notice further down in Fig. 22-17 where we disassembled
the program that JMP 0107 disassembles to EB03. Our
assembler and DEBUG produced the same code.
After the jump instruction are several NOPs which could
be other instructions or just unused memory in a particular
microprocessor system.
In line 12 of Fig. 22-16 we subtract EE 16 from FF 16 (in
AL). In line 13 we store the result of our subtraction in a
memory location called ANSWER. Look at line 16, labeled
ANSWER. In the op code column are the initials DB. This
stands for define byte. We are telling the assembler to
reserve a memory location, namely, a single byte of
memory, with the name ANSWER. The assembler is
initializing the memory location ANSWER with a value of
0. Our program can then put any other number we wish in
that location.
Notice also that the memory location of ANSWER is
010E 16 . In the op code column of line 13 we see A2 010E.
A2 is the op code for storing the value of AL in a certain
memory location. Again the assembler made life simpler
by figuring out where the next available memory location
would be and setting aside that location for the ANSWER.
If you used DEBUG as shown in Fig. 22-17, then you
had to specify memory location 010E as shown.
Finally, in line 14 of Fig. 22-16, the program stops.
You should enter this program and single-step through
it, making sure that everything works as described. This is
shown in Fig. 22-18.
-r
AX-DDDD
BX=0000
CX=0Q00
DX=DDD0
SP-FFEE
BP=Q000
SI-DODO
DI=D00D
D S=3F3D
ES=3F3D
SS=3F3D
CS=3F3D
IP-D1DD
NV UP El
PL NZ
NA PO NC
3F3D:0100
B0FF
MOV
AL,
FF
-t
AX=00FF
BX=0000
CX=D000
DX=000D
SP=FFEE
BP = 0000
SI=0D00 DI=0000
DS=3F3D
ES=3F3D
SS=3F3D
CS = 3F3D
IP=0102
NV UP El
PL NZ NA P0 NC
3F3D:0102
EBD3
JMP
DID?
AX=00FF
BX^DDOD
CX^DDDD
DX=0000
SP=FFEE
BP=0000
SI=DDDD DI=0000
DS=3F3D
ES=3F3D
SS=3F3D
CS=3F3D
IP=0107
NV UP El
PL NZ NA PO NC
3F3D:DID?
-t
eCEE
SUB
AL,
- EE
AX=0011
BX=0000
cx=oooo
DX=DDDD
SP^FFEE
BP=0000
SI=0000 DI=0DD0
DS=3F3D
ES=3F3D
SS=3F3D
CS=3F3D
IP=D1D3
NV UP El
PL NZ NA PE NC
3F3D:D1D3
-t
A2DED1
MOV
[010E],AL
DS:010E=S3
AX=0011
BX=00DD
CX=0D00
DX—00DD
SP=FFEE
BP=000D
SI-0000 DI=000D
DS=3F3D
ES=3F3D
SS=3F3D
CS=3F3D
IP=010C
NV UP El
PL NZ NA PE NC
3F3D:010C CD20 INT 2D
-d DIDO 010F
3F3D:010D BO FF EB Q3 3D 3D 3D 2C-EE A2 DE 01 CD 2D 11 3F
Fig. 22-18 Forward unconditional jump with the 8086/8088
microprocessor (single-stepping with the Trace command).
356 Digital Computer Electronics
page ,135
3
□ □□□
CODE
SEGMENT
A
ASSUME CS:CODE ,
5
ta
0RG
IDDh
7
□ 1D0
B1
□ 3
START:
MOV
CL,03h
A
□ 105
B5
□ 0
MOV
CH,00h
9
Q1U4
FE
C5
REPEAT:
INC
CH
ID
□ 10b
SO
NOP
11
□ ID?
FE
CS
DEC
CL
15
□ IDS
75
FS
JNZ
REPEAT
13
1A
15
□ 1DB
CD
50
INT
50h
1L
17
□ 1DD
CODE
ENDS
1A
IS
END
START
Fig. 22-19 A backward
conditional jump creating a loop
with the 8086/8088
microprocessor (using an assembler).
DS:CODE, SS:CODE
;initialize CL (repeats)
;initialize CH
;times loop has repeated
;misc. instructions
;decrement CL
;if CL not equal to □ then
; branch back to start of
; loop
; stop
Conditional Branches
Now let’s see an example of conditional branching. Figure
22-19 shows such an example using an assembler.
Figure 22-20 shows the same program using DEBUG.
In this program we are going to do several things
differently from the way they were done in the last program.
First, we are using a conditional jump or branch rather than
an unconditional one. Second, we are branching backward
rather than forward. Third, we are creating a loop by
branching backward and repeating a section of the program.
Finally, we are using a register as a counter to control how
many times the loop repeats.
In line 7 of Fig. 22-19 we place the number 3 16 in CL.
This register controls how many times we will branch
backward. In line 8 we clear CH, making it 00 16 so that it
can be used to count how many times the loop repeats.
-a 100
77B3:01D0 MOV CL,03
77B3:0105 MOV CH,00
77B3:0104 INC CH
77B3:Q1QL NOP
77B3:0107 DEC CL
77B3:0109 JNZ 0104
77B3:010B
77B3:010B
77B3:010B INT 50
7 7 B3:010D
Line 9 marks the beginning of the loop, and we have
named that location REPEAT. In this line we increment
CH since we are beginning to pass through the loop, in
this case for the first time. Register CH is keeping track of
how many times the loop is passed through. Line 10
represents the fact that there could be many instructions
inside this loop which are going to be repeated.
Line 11 decrements (reduced by 1) register CL. Register
CL keeps track of how many times we have left to go
through the loop.
Line 12 is where we meet our conditional branch instruc¬
tion. JNZ means Jump if Not Zero. Your first thought
might be, “If what isn’t zero?”
All the conditional branch instructions are influenced by
the most recent instruction that affected the flag they check.
In this case the zero flag is checked. What was the last
instruction which sets or clears the zero flag? The DEC CL
;initialize CL (repeats)
;initialize CH
;times loop has repeated
;misc instructions
;decrement CL
;if CL not equal to □ then
; branch back to start of
; loop
; stop
-u 100 IDc
77B3:0100 B1D3
MOV
CL,03
77B3:0105 B500
MOV
CH, DO
77B3:DICK FEC5
INC
CH
77B3:010k 3D
NOP
77B3.-0107 FEC3
DEC
CL
77B3:0103 7SF3
JNZ
Q1UA
77B3:010B CD30
INT
50
Fig. 22-20 A backward conditional jump creating a loop
with the 8086/8088 microprocessor (using DEBUG).
Chapter 22 Branching and Loops 357
(DECrement CL) instruction. If register CL were reduced
to 0, the zero flag would be set. Has CL been reduced to
0? On this first pass through the loop it gets reduced from
3 to 2. No, CL is not equal to 0.
The jump instruction says, “Jump if not zero.” Clearly
this is true: the last result is not 0, so we do jump. Jump
to where? We jump to the memory location known as
REPEAT. Notice that the location called REPEAT, in line
9, is memory location 0104 16 . Now look again at line 12.
The op code for the JNZ instruction is 75. F9 is a negative-
signed binary number telling us how many places to move
backward through memory to reach the place labeled
REPEAT.
If you are using DEBUG to enter this program a shown
in Fig. 22-20, you will actually enter address 0104. DEBUG
then calculates the relative address (F9) for you as shown
in the disassembled area at the bottom of Fig. 22-20.
It will be helpful to enter this program into your computer
and single-step through it. Pay special attention to register
CL, register CH, and the zero flag.
Compare Instructions
The compare instructions allow us to compare the values
in two registers and/or memory locations and to set the
flags accordingly without changing either of the original
values. The appropriate jump instruction can then cause
program execution to continue at the desired location. The
program in Figs. 22-21 and 22-22 allows you to observe
how the compare instructions work.
The program simply loads the value 05 16 into AL and
compares the numbers 04 16 , 06 16 , and 05 16 to it. If you will
refer to the Expanded Table of 8086/8088 Instructions and
read the description, you will see what we mean by
“compare.”
To “compare” means to subtract the number you are
“comparing” from the number being “compared to.” For
example, line 8 of the program in Fig. 22-21 sets the flags
as though 04 16 had been subtracted from 05 16 , without
actually changing the value in AL. Lines 9 and 10 likewise
subtract 06 ]6 and 05 16 , respectively, from the value in AL
without altering AL.
This program’s only purpose is to allow you to see how
the flags are affected by each compare instruction. Enter
the program and single-step through it. Watch the flags
after each step and make sure that you understand why they
react the way they do. This has been done in Fig. 22-22.
An Example Program
We’ll now look at an example program which uses a
compare instruction, increment instructions, and a condi¬
tional branch instruction. This program looks at two numbers
in memory, determines which is larger, and then places the
larger value in a third memory location. It also uses register
indirect addressing. Refer to Figs. 22-23 and 22-24 at this
time.
After entering this program into your computer or trainer
but before running it, you must place values of your choice
into the two memory locations indicated in the note at the
top of Fig. 22-23.
This program uses BX to help point to the next memory
location to load a number from or store a number in. The
first instruction in line 12 of Fig. 22-23 initializes BX with
a value of 00 16 .
Memory location Oil9 16 (referred to as DATA, line 22)
is the beginning of a series of memory locations which this
program uses. A common way to address successive memory
locations is to use register relative addressing. Location
0119 l6 is the beginning of the list, and the BX register will
point to each successive number in the list. In line 13 we
load the accumulator with the first number from the list.
The memory location of this number is pointed to by adding
0119 16 (DATA) to the value in BX.
In line 14 we increment the BX register to a value of
01 16 so that we can point to the next number.
In line 15 we compare the value held in memory location
[DATA + BX] to the value in the accumulator. If the
value in the accumulator is larger, then no borrow will be
needed to perform the comparison (which involves sub-
1
page ,132
3
□ □□□
CODE
SEGMENT
4
ASSUME CS:CODE
5
ninn
0RG lOOh
b
7
010D
BD
D5
START:
MOV AL,D5h
A
□ IDE
3C
□ 4
CMP AL,04 h
q
□ 1D4
3 C
0b
CMP AL,Obh
ID
010b
3 C
□ 5
CMP AL,05h
11
□ IDA
CD
2D
INT 20h
12
13
DID A
CODE
ENDS
14
15
END START
Fig. 22-21 Using the compare instruction (8086/8088 using
an assembler).
DS:CODE, SSrCODE
initial value
compare each of
to AL and set
each had been
these numbers
flags as though
subtracted from AL
358 Digital Computer Electronics
ODEBUG
-r
AX=0000 BX=0000
DS=3F3D ES=3F3D
3F3D:0100 BOOS
CX=0000 DX=0000 SP=FFEE
SS=3F3D CS=3F3D IP=0100
MOV AL,D5
BP=0000 SI=0DGG DI=0000
NV OP El PL NZ NA PO NC
-a
3F3D:0100 MOV AL,05
3F3D: 010E CMP AL,04
3F3D:0104 CMP AL,0t
3F3D: 0100 CMP AL,D5
3F3D:OlOfl INT 30
3F3D:DIDA
initial value
compare each of these numbers
to AL and set flags as though
each had been subtracted from AL
-u 1Q0 IDS
3F3D:0100 BODS
3F3D:0102 3C04
3F3D:0104 3C0G
3F3D:0100 3C0S
3F3D:OIOS CDEO
MOV AL, 05
CMP AL,04
CMP AL/Ot
CMP AL,05
INT 50
-r
AX=0000 BX=0000
DS=3F3D ES=3F3D
3F3D:0100 BOOS
-t
CX=0000 DX=0000 SP=FFEE BP=0000 SI-0D00 DI=0000
SS=3F3D CS=3F3D IP 010D NV UP El PL NZ NA PO NC
MOV AL,0 S
AX=0005 BX=0000 CX=0000 DX=0000 SP=FFEE
DS=3F3D ES=3F3D SS=3F3D CS=3F3D IP=01DE
3F3D:OlOE 3C04 CMP AL,04
-t
BP=0000 SI=0000 DI=0000
NV OP El PL NZ NA PO NC
AX=0005 BX=0000 CX=0000 DX=0000 SP =FFEE
DS=3F3D ES=3F3D SS=3F3D CS=3F3D IP-0104
3F3D:0104 3C0t CMP AL,Ot
-t
BP-0000 SI=0000 DI=0000
NV OP El PL NZ NA PO NC
AX=0005 BX=0000 CX=0000 DX=0000 SP=FFEE
DS=3F3D ES=3F3D SS=3F3D CS=3F3D IP=OlOt
3F3D:OlOt 3C0S CMP AL,05
- t
BP=D0DD SI=0G00 DI=0DDD
NV UP El NG NZ AC PE CY
AX=0D05 BX=0DDD
DS=3F3D ES=3F3D
3F3D:DlDfl CDED
CX=0000 DX=DD00 SP=FFEE BP-DDOD SI^OOOD DI^DDOQ
SS=3F3D CS—3F3D IP---DlDfl NV UP El PL ZR NA PE NC
INT ED
Fig. 22-22 Using the compare instruction (8086/8088 using
DEBUG).
traction), nor will the result of the comparison be 0; there¬
fore both the carry flag and the zero flag will be clear.
We find in line 16 that, if both the carry flag and the
zero flag are clear, then we branch forward to line 18. This
will be the case if the value in AL is the larger value. In
line 18 the BX register is incremented so that it points to
the last memory location. In line 19 we store the value now
in AL in that final memory location.
If during the comparison in line 15 the value in the
accumulator is smaller, a borrow is required to perform the
comparison (involving subtraction) and the carry flag is set.
In line 16 the carry flag is not clear and the jump does not
occur. Therefore the next instruction in line 17 is executed.
This instruction loads the second number into AL. Ob¬
viously, if the first number is not the larger, the second
one must be. After loading the accumulator with the second
number in line 17, we continue in lines 18 and 19 to store
that value in the third memory location.
This program will give you an idea how to use some of
the new instructions in this chapter and how to use register
relative addressing.
Compare the program as shown in Figs. 22-23 and 22-
24. In Fig. 22-24 the program is entered by using DEBUG
and then single-stepping through (using trace). As in all
programs shown in this text, you’ll learn the most if you
enter the program yourself and experiment with it.
Chapter 22 Branching and Loops 359
1
2
3
4
5
b
7
A
□ □□□
3
IQ
□ 1QQ
11
13
□
BB
□ □□□
13
□ 103
AA
A7
□ 113
R
14
□ 107
4 3
15
□ IDA
3 A
A7
□ 113
R
lb
□ 1QC
77
U4
17
□ IDE
AA
A7
□ 113
R
1A
□ 113
43
13
□ 113
AA
A7
□ 113
R
3Q
□ 117
CD
3Q
31
33
□ 113
D5
U4
□ □
S3
34
ss mile
3b
3?
page ,133
;place a number in memory location DATA and another in DATA+1;
; this program will determine which is larger and place
; the larger in location DATA+3 (Note: Do not use two
; numbers which are equal.)
CODE
SEGMENT
ASSUME CS:CODE,
DS :
CODE, SS:CODE
ORG
□inoh
START:
MOV
BX,□□h
;initialize BX register
MOV
AL,[DATA
+
BX]
;move byte to AL from mem loc
DATA
INC
BX
;point to next mem loc
(DATA
+ 1)
CMP
AL,[DATA
+
BX]
;compare byte in mem DATA + 1
to
AL
JA FOUND
;if AL is larger jump forward
to
Found
MOV
AL,[DATA
+
BX]
; otherwise move byte
DATA + 1
to AL
from
mem
FOUND:
INC
BX
;point to next mem loc
(DATA
+ 2)
MOV
[DATA +
BX]
, AL
;move byte in AL to mem
DATA
+ 3
INT
3Dh
; stop
DATA
DB
□5h,D4h,
□ □h
;you can use different
values
for
the
; first two numbers
CODE
ENDS
END
START
Fig. 22-23 An example 8086/8088 program (using an
assembler).
ODEBUG
—
AX=DDDD BX=DDDD
CX=QQ0D DX=
□□□□ SP FFEE BP=DDDD SI=DDDD DI=DDDD
DS=3F3D ES=3F3D
SS=3F3D CS=
3F3D IP=D1DD NV UP El PL NZ NA P0 NC
3F3D : □!□□
BBDDDD
MOV
BX,□□□□
-a
3F3D : □!□□
MOV
BX , □□□□
; initialize BX register
3F3D:D1D3
MOV
AL,[BX+D113]
;move byte to AL from mem loc 0113 + □
3F3D: D1D7
INC
BX
;point to next mem loc D113 + 1
3F3D:DlDfl
CMP
AL,[BX+Q113]
;compare byte in mem 0113 + 1 to AL
3F3D: D1DC
JA
□ 113
;if AL is larger jump forward to D113,
3F3D: D1DE
MOV
AL,[BX+0113 ]
| ; otherwise move byte to AL from D113
3F3D : □!13
INC
BX
;point to next mem loc D113 + 3
3F3D : 0113
MOV
[BX+D113],AL ;move byte in AL to mem D113 + 3
3F3D : 0117
INT
3D
; stop
3F3D : 0113
-u □!□□ Ollfl
3F3D :□!□□
BBDQDD
MOV
BX, □□□□
3F3D : 0103
fl AA713D1
MOV
AL,[BX+D113]
3F3D : 0107
43
INC
BX
3F3D : DlDfl
3 Afi713□!
CMP
AL, [ BX+D113 ]
3F3D : D1DC
71U4
JA
□ 113
3F3D : D1DE
fiA6713D1
MOV
AL,[BX+D113]
3F3D:D113
43
INC
BX
3F3D:D113
fiflfi713Dl
MOV
[BX+D113],AL
3F3D:0117
CD3D
INT
3D
Fig. 22-24 An example 8086/8088 program (using DEBUG).
360 Digital Computer Electronics
-e 0113
3F3D : 0113 5E.05 Ft.. DA 6B.00 07.□□
-d 0110 Ollf
3F3D:0110 13 01 A3 66 67 13 01 CD-50 05 UA □□ □□ 63 AL EE ..C
AX=D000
BX=0000
CX=0000
DX=000D
SP=FFEE
DS=3F3D
ES=3F3D
SS=3F3D
CS=3F3D
IP=0100
3F3D:DIDO
-t
1 BBDD0D
MOV
BX,
0000
AX=DDDD
BX=0000
CX=0DDD
DX=Q0Q0
SP=FFEE
DS=3F3D
ES=3F3D
SS=3F3D
CS=3F3D
IP=01D3
3F3D:0103
-t
6A6713I
□ 1 MOV
AL /
[BX+0113
AX=DDD5
BX=0D0D
CX=0000
DX-0000
SP=FFEE
DS=3F3D
ES=3F3D
SS=3F3D
CS=3F3D
IP=0107
3F3D:DID?
-t
A 3
INC
BX
AX^DDDS
BX=0D01
CX=0000
DX=QQ00
SP=FFEE
DS=3F3D
E S=3F3D
SS=3F3D
CS=3F3D
IP=0106
3F3D:0106
-t
3A671301 CMP
AL,
[BX+0113
AX=DD05
BX=D001
CX=00D0
DX=00 00
SP=FFEE
DS=3F3D
ES=3F3D
SS=3 F3D
CS=3F3D
IP=D10C
3F3D:D1DC
-t
??UA
JA
□ 113
AX=0n05
BX=0001
cx=oooo
DX=0000
SP FFEE
DS=3F3D
ES-3F3D
SS=3F3D
CS=3F3D
IP=D113
3F3D : DUE
-t
A 3
INC
BX
AX=0005
BX=0003
CX-0000
DX=000D
SP=FFEE
DS=3F3D
ES=3F3D
SS=3F3D
CS=3F3D
IP—0113
3F3D:0113
-t
mov
[ BX+0113]/A]
AX=DDD5
BX=0003
CX=0000
DX=0000
SP=FFEE
D S—3F3D
ES = 3F3D
SS=3F3D
CS=3F3D
IP=0117
3F3D:Dll?
CD30
INT
30
-d DUO 011 f
3 F3D:0110
13 01
A 3 flfl 67 13 01 CD-
30 05 UA
BP^DOOO SI=DOOD DI=0000
NV UP El PL NZ NA PO NC
BP=0000 SI=0000 DI=0000
NV UP El PL NZ NA PO NC
DS:0113=05
BP=DOOO SI=0000 DI=0000
NV UP El PL NZ NA PO NC
BP=0000 SI=0000 DI=0000
NV UP El PL NZ NA PO NC
DS:DllA=04
bp=oooo si=oooo di=odod
NV UP El PL NZ NA PO NC
bp=oooo si=oooo di=odoo
NV UP El PL NZ NA PO NC
BP-oooo si=aaoo di-oooo
NV UP El PL NZ NA PO NC
DS:011B=00
BP=0000 SI=0000 DI=0000
NV UP El PL NZ NA PO NC
05 00 63 AL EE ..C
F .
Fig. 22-24 (cont.)
GLOSSARY
decrement To decrease. Most microprocessors decrement
registers or memory locations by 1.
increment To increase. Most microprocessors increment
registers or memory locations by 1.
loop A group of instructions which can be executed more
than once. The program “falls through” the loop when
some condition exists or when the loop has been executed
a predetermined number of times.
nest To fit one inside another. Loops can be nested by
having one small loop executing within a larger loop.
Chapter 22 Branching and Loops 361
SELF-TESTING REVIEW
Read each of the following and provide the missing words.
Answers appear at the beginning of the next question.
1. Branches or jumps can be made to execute all the
time or only when certain conditions exist. That is,
branches and loops can be_or
2. (conditional, unconditional) When a program
branches backward and repeats a group of instruc¬
tions, it is called a_
3. (loop) Compare instructions generally (though not
always) set and clear the microprocessor’s flags as
though_had occurred.
(subtraction)
PROBLEMS
Solve the following problems by using the microprocessor
of your choice.
You may have some difficulty with the following two
problems; therefore only two are given. As you begin each
problem, do not immediately think of which microprocessor
instructions to use. Instead, think about the problem itself
and visualize what the memory locations will contain. Think
of how to move the data between registers and memory
locations to solve the problem, and then think about what
instructions can be used to accomplish the moves.
22-1. Write a program which will use the first number
in a list of unsigned binary numbers as a refer¬
ence, will compare that number to each of the
following numbers in the list, and will then stop
when it finds the first number in the list which is
smaller than or equal to the reference number.
Finally, the program should store that first number
which was smaller or equal to the reference num¬
ber in a memory location called ANSWER.
(Important: The numbers in the list must be considered
unsigned binary numbers. At least one number in the list
must be smaller than or equal to the reference number.
All the numbers may be smaller or equal to the reference.
The program will be most interesting if more than one,
but not all, the numbers are smaller than or equal to the
reference.)
(Note: You will need to enter the list of numbers
before running the program. The list must have a mini¬
mum of two numbers and can have as many additional
numbers as you wish. We have started the list of numbers
at memory location $03AO for the 6502, $01 AO for the
6800/6808, and at 18A0h for the 8080/8085/Z80, and at a
location labeled LIST for the 8086/8088.)
22-2. Write a program which will look at a list of
numbers which you will store in memory. The
end of this list will be indicated by the number
00. The number 00 cannot be used anywhere in
the list except to mark its end. Write the program
so that it will add each pair of consecutive num¬
bers. That is, if the list contained the numbers
06 16 , 2E 16 , 36 16 , 42 16 , and 00 16 , it would perform
the following additions:
06 16 + 2E 16 = 34 16
2E 16 + 36 16 — 64 16
36j 6 + 42 16 = 78 16
The program should not add the 00 16 to the preceding
number since 00 16 is not one of the numbers in the list
but indicates the end of the list.
When the program adds the first two numbers, it
should place their sum in a memory location called
LRGST (largest). As it adds each of the following pairs,
it should compare their sum with the number in LRGST.
If the new sum is larger than the number in LRGST, then
the new largest number should be placed in LRGST.
Thus, after the program has added all the pairs together,
LRGST will contain the largest sum that was created. All
numbers should be considered unsigned binary numbers.
(Note: The list must contain at least one number, with
the number 00 following it to indicate the end of the list.
In this case no sum should appear in LRGST because
there can be no sum with a list of only one number. The
list can contain any number of numbers beyond one.)
(Note: We have used the numbers 2E 16 , 3C 16 , 1B 16 , 46 16 ,
and 00 16 to end the list, in that order, in the answer key.
You should try altering your list to make sure it works
under various circumstances.)
362 Digital Computer Electronics
Subroutine and Stack Instructions
At this point we have covered most of the instruction set
of each of the microprocessors featured in this text. Two
final topics, however, the stack and subroutines, may be
the most important ones. Without subroutines, programs
written for these microprocessors would be unmanageable.
Subroutines are used when there are tasks which must be
executed or used many times. The subroutine provides a
way to write a program segment which can handle a specific
task and be reused.
The stack is important because it supports subroutines
by storing information the microprocessor needs when it
tries to return from a subroutine.
New Concepts
This chapter deals with subroutines and with the stack,
especially as the stack relates to subroutines. The use of
the stack in passing parameters between subroutines or in
mixed-language programs is beyond the scope of this text
and is not discussed.
We discussed the stack in Chap. 15. We’ll review a
portion of that chapter here.
Memory
0000
A
0001
0002
Top-of-stack
d
d
r
0003
Data item #6
— Stack pointer—
0004
Data item #5
0002
e
s
s
0005
Data item #4
e
0006
Data item #3
s
0007
Data item #2
0008
Data item #1
Fig. 23-1 Typical stack and stack pointer.
23-1 STACK AND STACK POINTER
The stack, in the case of the microprocessors used in this
text, is located in RAM. Refer to Fig. 23-1.
The structure of the stack is a first-in-last-out (F1LO)
type of structure. Unlike main memory, where you can
access any data item in any order, the stack is designed so
that you can access only the top of the stack. If you want
to place data in the stack, it must go on top, and if you
wish to remove data from the stack, it must be on top
before it can be removed.
Let’s see how the situation in Fig. 23-1 has come to be.
To do that, refer to Fig. 23-2. Data item #1 is the first
item we wish to place on the stack.
At this time the stack pointer is '‘pointing” to memory
location 0008; therefore, data item #1 will be placed in
the stack at that memory location. Putting a piece of data
in the stack is called pushing data onto the stack. It is as
though the data is being pushed in from the top. Now look
at Fig. 23-3.
We have pushed data item #1 onto the stack, and the
stack pointer has been decremented or decreased by 1,
Memory
0000
A
0001
d
0002
d
r
0003
— Stack pointer —
0004
0008
e
s
s
0005
e
0006
s
0007
0008
Top-of-stack
r
Fig. 23-2 Typical stack and stack pointer.
Memory
0000
A
0001
d
0002
d
r
0003
— Stack pointer—
0004
0007
e
s
s
0005
e
0006
s
0007
Top-of-stack
0008
Data item #1
Fig. 23-3 Typical stack and stack pointer.
which means that it is now pointing to memory location
0007. Now 0007 is the top-of-the-stack. Now let’s push
data item #2 onto the stack. The stack will appear as it
does in Fig. 23-4.
When data item #2 was pushed onto the stack, it went
into the location which was being pointed to by the stack
pointer, which was 0007. The stack pointer was then
decremented to 0006. This process will be repeated until
the stack appears as it did in Fig. 23-1.
At some point we will need this data in the stack, so we
will remove it from the top-of-the-stack. This is called
popping or pulling the data from the stack. We simply
reverse the whole process. As each data item is removed,
the stack pointer will drop, which in this case means that
it will increment or point to the next-greater memory address.
23-2 BRANCHING VERSUS
SUBROUTINES
another section of the program. This may be an unconditional
jump or a conditional jump. In either case the instructions
immediately following the jump instruction may not be
executed. If we branch to another section of the program,
it is because we don’t want to execute the instructions
immediately following the branch instructions.
Subroutines also allow us to jump to another section of
the program to execute instructions there. Subroutines differ
from jumps or branches, however, in that the instructions
which immediately follow the subroutine instruction are
executed later. (The act of starting to execute a subroutine
is referred to as jumping to a subroutine if you are using a
6502 or 6800/6808 microprocessor. It is referred to as
calling a subroutine if you are using an 8080/8085/Z80 or
8086/8088 microprocessor.)
After the microprocessor jumps to a subroutine or calls
a subroutine, the instructions in the subroutine begin to
execute. At the end of the subroutine is an instruction called
the return instruction. The return instruction is usually the
last instruction in the subroutine; it tells the microprocessor
to go back to the place in the program where it was when
the subroutine was called and to pick up where it left off.
This is shown in Fig. 23-5.
It is also possible for a subroutine to call another
subroutine. These nested subroutines then sort of “unwind”
and return in the reverse order relative to that in which they
were called. This is illustrated in Fig. 23-6.
23-3 HOW DO SUBROUTINES
RETURN?
The ability of a subroutine to return to the exact location
it came from, especially when nested several layers deep,
raises the question of how it knows where to return to.
In Chap. 22, where branching was discussed, we saw that
branching causes program execution to jump or branch to
Memory
0000
A
0001
d
0002
d
r
0003
— Stack pointer —
0004
0006
e
s
s
0005
0006
Top-of-stack
e
s
0007
Data item #2
0008
Data item #1
Fig. 23-4 Typical stack and stack pointer.
A
d
d
r
e
s
s
e
s
Main program Subroutine
Memory Memory
0000
hh
hh
0001
hh
hh
0002
hh
hh
0003
hh
hh
0004
Call sub
hh
0005
Address
hh
0006
Next inst
hh
0007
hh
hh
0008
hh
hh
0009
hh
Return
Fig. 23-5 “Calling’’ or “jumping” to a subroutine.
364 Digital Computer Electronics
Second Subroutine
A
d
d
r
e
s
s
e
s
Main program First Subroutine
Memory
Memory
Memory
0000
hh
hh
hh
0001
hh
hh
hh
0002
hh
Jump sub
hh
0003
hh
Address
hh
0004
Jump sub
Next inst
hh
0005
Address
hh
hh
0006
Next inst
hh
hh
0007
hh
hh
hh
0008
hh
hh
hh
0009
hh
Return
Return
Fig. 23-6 Nested subroutines.
That is, how does it know where it came from? The answer
lies in what happens just before the microprocessor leaves
the main program, or current subroutine, to go to the
subroutine being called.
The microprocessor must know two things before a
subroutine can be called or jumped to. First, it must know
where it’s going, and second, it must know how to get
back.
The instruction jump to subroutine or call subroutine
contains the address of the desired subroutine. This may
be in the form of an absolute address or an offset of some
sort. This is the destination.
The program counter (8086/8088 instruction pointer)
contains the address of the next instruction to be executed.
This is the point to which the microprocessor needs to
return. Refer to Fig. 23-7.
When the subroutine is called, the contents of the program
counter are pushed onto the stack. This requires more than
one push, since in the case of the 8-bit microprocessors the
stack is only 8 bits wide but the program counter is 16 bits
wide. (The 8088 stores not only the instruction pointer but
may also store the code segment, depending on the type of
call —near or far.)
After the program counter (instruction pointer) is pushed
onto the stack, the address of the subroutine which is being
called or jumped to is placed in the program counter
(instruction pointer), and program execution begins at this
new address.
Execution now continues in the subroutine until a return
instruction is encountered. Refer to Fig. 23-8.
At this point, the address of the next instruction which
was to be executed after the subroutine jump or call, which
A
d
d
r
e
s
s
e
s
Main program
Memory
0000
hh
0001
hh
0002
hh
0003
hh
0004
Jump sub
0005
Addr F000
0006
Next inst
0007
hh
0008
hh
0009
hh
Program counter
Addr next inst
Stack
Ret addr
hh
hh
hh
hh
hh
Fig. 23-7 Calling a subroutine.
Subroutine
Memory
F000
hh
F001
hh
F002
hh
F003
hh
F004
hh
F005
hh
F006
hh
F007
hh
F008
hh
F009
Return
Chapter 23 Subroutine and Stack Instructions
365
Subroutine
Main program
Memory
0000
hh
A
0001
hh
d
0002
hh
d
r
0003
hh
e
0004
Jump sub
s
s
0005
Addr F000
e
0006
Next inst
s
0007
hh
0008
hh
0009
hh
Fig. 23-8 Returning from a subroutine.
Program counter
A
d
d
r
e
s
s
e
s
Memory
F000
hh
F001
hh
F002
hh
F003
hh
F004
hh
F005
hh
F006
hh
F007
hh
F008
hh
F009
Return
has been stored on the stack, is pulled or popped from the
stack and placed in the program counter (instruction pointer).
Execution then proceeds from that point forward in the
main program.
To summarize:
1. The call or jump to subroutine instruction is encoun¬
tered.
2. The program counter (instruction pointer) is already
pointing to the next instruction to be executed (in this
section of the program code).
3. The contents of the program counter (instruction pointer)
are pushed onto the stack.
4. The address of the subroutine is placed in the program
counter (instruction pointer).
5. Program execution now begins in the subroutine.
6. When a return instruction is encountered, the return
address, which has been previously stored in the stack,
is pulled from the stack and placed in the program
counter (instruction pointer).
7. Program execution continues from where it left off
before the subroutine was called or jumped to.
23-4 PUSHING AND POPPING
REGISTERS
When a subroutine is called or jumped to, the use and
operation of the stack are automatic. You don’t have to tell
the microprocessor to store the return address on the stack.
It is done automatically.
In addition to the automatic use of the stack in subroutine
calls, the stack can be used directly by the programmer for
other purposes. Although each microprocessor is different,
in general, you can push onto the stack, and pull from the
stack, the contents of some or most of the microprocessor’s
registers. This is often used to pass values from the main
program to subroutines and back, or from subroutine to
subroutine. These values are sometimes referred to as
parameters. The use of the stack in parameter passing,
however, is beyond the scope of this text.
Specific Microprocessor
Families
Let’s look at each of our featured microprocessors. We will
not go into great detail about what each microprocessor
does automatically before and after a subroutine is called.
Rather, we will give examples which show how to call a
subroutine and how to nest subroutines.
23-5 6502 FAMILY
The 6502 microprocessor works as described in the New
Concepts section of this chapter. There is one point worth
noting, however.
The stack pointer of the 6502 is a little different from
that of the other microprocessors featured in this text. The
changeable portion of the stack pointer is only 8 bits wide
(all the others are 16 bits wide) and a 9th bit is always set
to 1. This means that the location of the stack must lie in
the range from address 0100 to 01FF. This is shown in
Fig. 23-9.
Setting the Stack Pointer
Our first example program illustrates how to set the stack
pointer to a desired address and then call a subroutine. It
366 Digital Computer Electronics
Memory
is important to note that, with the simple programs we have
used throughout this text, setting the stack pointer is
normally not required. The microprocessor trainer or com¬
puter you are working with will have an operating system
that will set the stack pointer to a logical address based on
available memory.
Figure 23-10 contains our example program. It sets the
stack pointer to a desired address and then calls a subroutine.
The subroutine does not actually do anything. It gives you
a chance to single-step through a program and watch the
stack pointer and program counter.
Calling More than One Subroutine (Not Nested)
Our next example program is shown in Fig. 23-11.
The two subroutines shown here occur one after the
other. They are not nested. You should single-step through
this program and watch the stack pointer and program
counter. This is important because the next program will
also contain two subroutines, but they will be nested. We
want you to see the difference between the two.
Again, these first programs do not do anything. Just
observe the behavior of the program counter and the stack
pointer.
Nesting Subroutines
The program shown in Fig. 23-12 also has two subroutines.
They are nested, however.
Single-step through this program and watch the stack
pointer and the program counter carefully. Notice how they
act differently from the way they did in the last program.
When you are inside the second subroutine, the stack is
holding the return addresses for both subroutines. That’s
why it decrements further.
Pushing Registers
The example program shown in Fig. 23-13 shows how to
use the stack to move information from one register to
another.
The program pushes the flags onto the stack and then
pulls them from off the stack into the accumulator. The
□ □□1
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3 A
TXS
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EA
NOP
□ □□fa
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ED
4A 03
JSR SUBRTN
□ □□7
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□ □
BRK
□ □□A
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EA
SUBRTN:
NOP
□ □□3
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to
RTS
□ □ID
□ 34 A
7
□ □11
□ 34 A
.END
;load number for stack pointer
;load stack pointer
;misc instructions
;jump to subroutine (watch stack pointer)
; stop
;misc instructions
;return from subroutine
Fig. 23-10 6502 program
subroutine.
loading stack pointer and
calling a
□ □□1
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□ 340
□ □□3
□ 34 □
EA
START:
NOP
□ □□4
□ 341
3D 43
□ 3
JSR RTNE_1
□ □□5
□ 344
EA
NOP
□ □□fa
□ 345
3D 4B
□ 3
JSR RTNE_3
□ □07
□ 34 A
□ □
BRK
□ □□a
□ 343
EA
RTNE_1 :
NOP
□ □□3
□ 34 A
faD
RTS
□ □ID
□ 34B
EA
RTNE_3:
NOP
□ □11
□ 34C
faD
RTS
□ □13
□ 34D
□ □13
□ 3 4D
.END
Fig. 23-11 6502
program
with two subroutines not nested.
Watch the stack pointer as
each subroutine is
"called" or "jumped to,"
and as execution returns
from each back to the main
program. These subroutines
are not nested.
Chapter 23 Subroutine and Stack Instructions 367
□ □01
□ 34 0
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□ 34 □
□ □□3
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EA
START:
NOP
□ □□4
□ 341
00
45
□ 3
JSR RTNE_1
□ □□5
□ 344
□ □
BRK
□ 00b
□ 345
EA
RTNE_1:
NOP
□ □□?
□ 34b
00
4 A
□ 3
JSR RTNE_0
□ □□A
□ 3 4 3
GO
RTS
□ □□3
□ 34 A
EA
RTNE_0:
NOP
□ □10
□ 34B
b0
RTS
□ □11
□ 34C
□ 010
□ 34C
.END
Fig. 23-12 6502
program with two nested subroutines.
Again, watch the stack
pointer as each subroutine
is “called" or "jumped to,"
and as execution returns
from each subroutine. These
subroutines are nested.
□ □□1
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□ □□0
034 □
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□ □□5
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0343
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PLA
BRK
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:push flags then decrement stack pointer
;pull then increment stack pointer
; stop
Fig. 23-13 6502 program which pushes a register.
bits of the accumulator, which represent the status of the
flags, can now be examined by the program or stored in
memory.
A Useful Program Containing a Subroutine
Let’s take a look at the program shown in Fig. 23-14.
This program’s purpose is as follows:
it is positive or 0, it will do nothing with the num¬
ber. If the number is negative, a subroutine will be
entered. This subroutine will find the absolute value
of the number (that is, it will make the negative num¬
ber positive). It will then write this positive number
into memory in place of the original negative number.
(We used the decimal numbers 3, —4, —2, 0, and 5.)
(Note: If the microprocessor being used here has a
negate instruction, that instruction will not be used.)
This program will read a list of five signed binary
numbers. As it reads each number, it will determine
whether that number is positive or 0 or negative. If
Enter this program into your microprocessor trainer or
computer and single-step through it. Study the program and
make sure that you understand its operation.
□ □□1
034 □
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$0340
□ □00
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□ □03
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A0
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START:
LDX
#$□□
0004
□ 340
AD
□ b
LDY
$ $ □ b
□ □□5
□ 344
A A
GETNUM :
DEY
□ 00b
□ 345
F0
13
BEQ
DONE
□ □□?
□ 347
BD
bl
□ 3
LDA
SLIST, X
□ □□A
034 A
C3
□ □
CMP
*$□□
□ □□3
’□34 C
10
05
BPL
NEXT
□ □ID
034E
F0
□ 3
BEQ
NEXT
□ Oil
0350
00
57
□ 3
JSR
NEGNUM
0010
□ 353
EA
NEXT:
INX
□ □13
□ 354
4C
44
□ 3
JMP
GETNUM
□ □14
□ 357
43
FF
NEGNUM:
EOR
* IFF
□ □15
□ 353
1A
CLC
□ □lb
□ 35 A
b3
01
ADC
#$□1
0017
035C
3D
bl
□ 3
STA
SLIST, X
□ D1A
□ 35E
bO
RTS
□ 013
□ 3 b 0
□ 0
DONE :
BRK
□ □00
□ 3bl
□ □01
03bl
□3FCFEDDD5
LIST:
.db
3,
□ □00
□ 3bb
□ □03
□ 3bb
. end
Fig. 23-14 A useful 6502 program which contains a
subroutine.
;address of beginning of list
;counter
;decrement counter
; if no items left end program
;load number from list
;is it positive/zero or negative?
;if positive get next number now
;if zero get next number now
;if negative call subroutine
;point to next number in list
;branch back to beginning
jinvert all bits of negative number
;prepare for addition
;add 1 to inverted bits
;write absolute value over
old negative value
; return*
; stop
-2, □, 5 ;list of 5 numbers
368 Digital Computer Electronics
□□□1
0100
.ORG
$0100
□ DDE
□ 100
;
□ 003
□ 100
flE
□ 1
FF
START:
LDS
*$01FF
□ 0D4
0103
01
NOP
□ 005
0104
BD
01
□ A
JSR
SUBRTN
0000
□ ID?
3E
WAI
0007
OlOfl
□ 1
SUBRTN :
NOP
OOOfi
□ 103
33
RTS
0003
□ 10 A
0010
□ IDA
.END
Fig. 23-15 6800/6808 program loading stack pointer and
calling a subroutine.
; load stack pointer
;misc instructions
;jump to subroutine (watch stack pointer)
; stop
;misc instructions
; return from subroutine
23-6 6800/6808 FAMILY
The 6800/6808 microprocessor works as described in the
New Concepts section of this chapter. We’ll look at several
sample programs which you can enter into your micropro¬
cessor trainer or computer and examine.
Setting the Stack Pointer
Our first example program illustrates how to set the stack
pointer to a desired address and then call a subroutine. It
is important to note that, with the simple programs we have
used throughout this text, setting the stack pointer is
normally not required. The microprocessor trainer or com¬
puter you are working with will have an operating system
that will set the stack pointer to a logical address based on
available memory.
Figure 23-15 contains our example program. It sets the
stack pointer to a desired address and then calls a subroutine.
The subroutine does not
actually do anything. It
gives you
0001
□ 1D0
.ORG $0100
0003
□ 100
0003
010D
□ 1
START:
NOP
□ 004
0101
BD
01 03
JSR RTNE_1
0005
□ 1D4
□ 1
NOP
□ 000
□ 105
BD
01 DA
JSR RTNE_3
0007
OlOfl
3E
WAI
OOOfi
0103
01
RTNE_1:
NOP
□ ooq
□ 10 A
33
RTS
□ □10
010B
□ 1
RTNE_3:
NOP
□ Oil
□ 10C
33
RTS
□ 013
010D
0013
□ 1DD
.END
Fig. 23-16 6800/6808 program with two subroutines not nested.
□ 001
0100
.ORG $0100
0003
0100
0003
0100
□ 1
START:
NOP
0004
01D1
BD
01 05
JSR RTNE_1
0005
□ 104
3E
WAI
□ 000
0105
□ 1
RTNE_1:
NOP
0007
0100
BD
□ 1 0A
JSR RTNE_3
OOOfi
0103
33
RTS
0003
010A
01
RTNE_3:
NOP
□ 010
□ 10B
33
RTS
□ Oil
010C
0013
□ 1DC
.END
Fig. 23-17 6800/6808 program with two nested subroutines.
a chance to single-step through a program and watch the
stack pointer and program counter.
Calling More than One Subroutine (Not Nested)
Our next example program is shown in Fig. 23-16.
The two subroutines shown here occur one after the
other. They are not nested. You should single-step through
this program and watch the stack pointer and program
counter. This is important because the next program will
also contain two subroutines, but they will be nested. We
want you to see the difference between the two.
Again, these first programs do not do anything. Just
observe the behavior of the program counter and the stack
pointer.
Nesting Subroutines
The program shown in Fig. 23-17 also has two subroutines.
They are nested, however.
Watch the stack pointer as
each subroutine is
"called" or "jumped to,"
and as execution returns
from each back to the main
program. These subroutines
are not nested.
3
3
Again, watch the stack
pointer as each subroutine
is "called" or "jumped to,"
and as execution returns
from each subroutine. These
subroutines are nested.
Chapter 23 Subroutine and Stack Instructions 369
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then
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PSHB
; push
then
decrement
stack
pointer
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PULA
; puli
then
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stack
pointer
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□ ID?
33
PULB
; puli
then
increment
stack
pointer
□ □□3
□ IDA
3E
WAI
; stop
□ □ID
□ IDS
□ □11
□ 1D3
.END
again
again
Fig. 23-18 6800/6808 program which pushes a register.
Single-step through this program and watch the stack
pointer and the program counter carefully. Notice how they
act differently from the way they did in the last program.
When you are inside the second subroutine, the stack is
holding the return addresses for both subroutines. That's
why it decrements further.
Pushing Registers
The example program shown in Fig. 23-18 shows how to
use the stack to move information from one register to
another.
The program loads accumulators A and B with a value,
pushes A and B onto the stack, and then pulls them from
the stack in reverse order. This places the data that was in
A in B and the data that was in B in A.
A Useful Program Containing a Subroutine
Let’s take a look at the program shown in Fig. 23-19.
This program’s purpose is as follows:
This program will read a list of five signed binary
numbers. As it reads each number, it will determine
whether that number is positive or 0 or negative. If
it is positive or 0, it will do nothing with the num¬
ber. If the number is negative, a subroutine will be
entered. This subroutine will find the absolute value
of the number (that is, it will make the negative num¬
ber positive). It will then write this positive number
into memory in place of the original negative number.
(We used the decimal numbers 3, — 4, —2, 0, and 5.)
(Note: If the microprocessor being used here has a
negate instruction, that instruction will not be used.)
Enter this program into your microprocessor trainer or
computer and single-step through it. Study the program and
make sure that you understand its operation.
23-7 8080/8085/Z80 FAMILY
The 8080/8085/Z80 microprocessor works as described in
the New Concepts section of this chapter. We’ll look at
several sample programs which you can enter into your
microprocessor trainer or computer and examine.
The 8080/8085/Z80 microprocessors do have two features
□ □□1
□ !□□
. org
$□!□□
□ DDE
□ !□□
□ □□3
□ !□□
CE
□ 1
IB
START:
LDX
*$LIST
□ □□4
0103
Ct
□ t
LDAB
# $ □ t
□ □□5
□ IDS
5 A
GETNUM:
DECB
□ □□□
□ 1DL
E7
IE
BEQ
DONE
□ □□?
□ IDA
At
□ □
LD AA
$□□ , X
□□□a
□ IDA
A1
□ □
CMP A
#$□□
□ □□3
01 DC
EC
□ 3
BGE
NEXT
□ □ID
□ IDE
BD
□ 1
14
JSR
NEGNUM
□ □11
□ 111
□ a
NEXT:
I NX
□ □IE
□ HE
ED
FI
BRA
GETNUM
□ □13
□ 114
43
NEGNUM :
COMA
□ □ 14
□ 115
QB
□ 1
ADDA
#$□1
□ □IB
□ 117
A7
□ □
STAA
$□□, X
□ □It
□ 113
33
RTS
□ □17
□ HA
3E
DONE:
WAI
□ □Ifl
□ 1 IB
□ □13
0HB
□3FCFEDDD5
LIST:
.db
3 ,
□ □ED
DIED
□ □El
DIED
. end
;address of beginning of list
;counter
; decrement counter
; if no items left end program
;load number from list
;is it positive/zero or negative?
;if positive get next number now
;if negative call subroutine
;point to next number in list
;branch back to beginning
;invert all bits of negative number
;add 1 to inverted bits
;write absolute value over
old negative value
;return
; stop
-4/ -E, □, 5 ; list of 5 numbers
Fig. 23-19 A useful 6800/6808 program which contains a
subroutine.
370 Digital Computer Electronics
that the other microprocessors featured in this text don’t
have: They have the ability to perform conditional subrou¬
tine calls and to perform conditional returns from subrou¬
tines. All the other microprocessors featured in this text
have only unconditional calls and unconditional returns.
Setting the Stack Pointer
Our first example program illustrates how to set the stack
pointer to a desired address and then call a subroutine. It
is important to note that, with the simple programs we have
used throughout this text, setting the stack pointer is
normally not required. The microprocessor trainer or com¬
puter you are working with will have an operating system
that will set the stack pointer to a logical address based on
available memory.
Figure 23-20 contains our example program. It sets the
stack pointer to a desired address and then calls a subroutine.
The subroutine does not actually do anything. It gives you
a chance to single-step through a program and watch the
stack pointer and program counter.
Calling More than One Subroutine (Not Nested)
Our next example program is shown in Fig. 23-21.
The two subroutines shown here occur one after the
other. They are not nested. You should single-step through
this program and watch the stack pointer and program
counter. This is important because the next program will
also contain two subroutines, but they will be nested. We
want you to see the difference between the two.
ADAD/ADA5 program
□ □□1
1AD0
.ORG lADOh
□ □02
1 ADD
□ □□3
1 ADD
31
DE
IF
START:
LXI SP, IFDEh
□ □□4
1AD3
DO
NOP
□ 005
1AD4
CD
□ A
1A
CALL SUBRTN
□ □□b
1 AD?
7b
HLT
□ □□7
1 AD A
□ □
SUBRTN :
NOP
□ □□A
1 ADD
CD
RET
□ □□3
1A DR
y
□ □ID
1ADA
.END
ZAD
program
□ DD1
1 ADO
.ORG
lADDh
□ □□2
1 ADD
;
□ □□3
1 ADD
31
DE
IF
START:
LD SP
, IFDEh
□ □□4
1AD3
□ □
NOP
□ DD5
1AD4
CD
□ A
1A
CALL
SUBRTN
□ DDL
1 AD?
7b
HALT
□ DD7
1ADA
□ □
SUBRTN:
NOP
□ □□A
1 ADD
CD
RET
□ ODD
1A 0 A
□ DID
1 AD A
.END
Fig. 23-20 8080/8085/Z80 program loading stack pointer and
calling a subroutine.
Again, these first programs do not do anything. Just
observe the behavior of the program counter and the stack
pointer.
Nesting Subroutines
The program shown in Fig. 23-22 also has two subroutines.
They are nested, however.
Single-step through this program and watch the stack
pointer and the program counter carefully. Notice how they
act differently from the way they did in the last program.
When you are inside the second subroutine, the stack is
holding the return addresses for both subroutines. That’s
why it decrements further.
Pushing Registers
The example program shown in Fig. 23-23 shows how to
use the stack to move information from one register to
another.
The program loads register pairs BC and DE with a
value, pushes BC and DE onto the stack, and then pulls
them from the stack in reverse order. This places the data
that was in BC in DE, and the data that was in DE in BC.
A Useful Program Containing a Subroutine
Let’s take a look at the program shown in Fig. 23-24.
This program’s purpose is as follows:
This program will read a list of five signed binary
numbers. As it reads each number, it will determine
;load stack pointer
;misc instructions
;call subroutine (watch stack pointer)
; stop
;misc instructions
;return from subroutine
;load stack pointer
;misc instructions
;call subroutine (watch stack pointer)
; stop
;misc instructions
;return from subroutine
Chapter 23 Subroutine and Stack Instructions 371
AD AD/AD A 5 program
□□□1
1 ADD
.ORG
1800h
odde
1 ADO
□ □□3
1A DO
□ □
START:
NOP
□ DDZ
1AD1
CD
DD
1A
CALL
RTNE_1
□ DDD
1A DZ
□ □
NOP
□ □□b
1 ADD
CD
□ B
1A
CALL
RTNE_5
□ □□?
1 AD A
7b
HLT
□ □□A
1 ADD
□ D
RTNE_1:
NOP
□ □□3
1 AD A
CD
RET
□ □ID
1A OB
□ □
RTNE__E:
NOP
□ Oil
1A DC
CD
RET
□ 012
1 ADD
□ □13
1 ADD
.END
ZAD ]
program
0001
1A □□
.ORG
lADDh
□□□a
1ADD
□ □□3
1 ADD
DD
START:
NOP
□ DDZ
1 ADI
CD
□ D
1A
CALL
RTNE_1
□ □□5
1A0Z
□ □
NOP
□ DDL
1 ADD
CD
DB
1A
CALL
RTNE_E
□ □□?
1 ADA
7b
HLT
□ □□A
1A 0 D
□ □
RTNE_1:
NOP
□ DDD
1A 0 A
CD
RET
□ DID
1A0B
00
RTNE_E:
NOP
□ Dll
1A DC
CD
RET
□ DIE
1 ADD
□ 013
1A DD
.END
Fig. 23-21 8080/8085/Z80 program with two subroutines not
nested.
ADAD/ADA5 program
Watch the stack pointer as
each subroutine is
"called" or "jumped to,"
and as execution returns
from each back to the main
program. These subroutines
are not nested.
Watch the stack pointer as
each subroutine is
"called" or "jumped to,"
and as execution returns
from each back to the main
program. These subroutines
are not nested.
□ □□1
1ADD
.ORG
lADDh
DDOE
1 ADD
□ □□3
1 ADO
□ □
START:
NOP
□ DDZ
1A01
CD
05
1A
CALL
RTNE_1
□ DDD
1A0Z
7b
HLT
^_
□ DDb
1AD5
□ □
RTNE_1:
NOP
00D7
1 ADh
CD
□ A
1A
CALL
RTNE_E
DDD A
1 ADD
CD
RET
—
□ DDD
1 AD A
□ D
RTNE_E:
NOP
□ DID
1ADB
CD
RET
□ Dll
1AOC
□ DIE
1 ADC
.END
ZAD
urogram
□ Q01
1ADD
.ORG
lADDh
□ DDE
1 ADO
□ □□3
1A0D
DD
START:
NOP
□ □□4
1AQ1
CD
□ D
1A
CALL
RTNE_1
□ □□5
1 ADZ
7b
HALT
□ DDb
1 ADD
DD
RTNE_1:
NOP
^ —
□ DD7
1 ADb
CD
DA
1A
CALL
RTNE_2
□ □□A
1ADD
CD
RET
i
0 0 0 D
1A D A
DD
RTNE_E:
NOP
DD1D
1ADB
CD
RET
DO 11
1A DC
□ DIE
1 AOC
.END
Fig. 23-22 8080/8085/Z80 program with two nested
subroutines.
Again, watch the stack
pointer as each subroutine is
"called" or "jumped to,"
and as execution returns
from each subroutine. These
subroutines are nested.
Again, watch the stack
pointer as each subroutine is
"called" or "jumped to,"
and as execution returns
from each subroutine. These
subroutines are nested.
372 Digital Computer Electronics
A0A0/A0A5 program
□ □□1
IflOO
.ORG lAOOh
□ doe
iaoo
0003
IflOO
□ 1
34
IE START:
LXI B,1E34 h
□ □□4
1603
11
7 A
50
LXI D/507Ah
0003
1600
C5
PUSH B
0000
1A07
D5
PUSH D
0007
IfiOfl
Cl
POP B
0DDA
laoq
D1
POP D
0003
1A0A
70
HLT
0010
1A 0B
□ 011
1A 0B
.END
ZAO
program
0001
1A 0 0
.ORG lAOOh
□ 00E
1A 0 0
0003
1A 00
01
34
15 START:
LD BC/lE34h
0004
1A03
11
? A
5 b
LD DE, 507 Ah
0005
1A 0 0
C5
PUSH BC
□ 000
1A07
D5
PUSH DE
0007
1A 0 A
Cl
POP BC
000 A
1603
D1
POP DE
0 0 03
1A 0 A
70
HALT
0010
1A 0B
0011
1A 0B
.END
Fig. 23-23 8080/8085/Z80 program which pushes a register.
whether that number is positive or 0 or negative. If
it is positive or 0, it will do nothing with the num¬
ber. If the number is negative, a subroutine will be
entered. This subroutine will find the absolute value
of the number (that is, it will make the negative num¬
ber positive). It will then write this positive number
into memory in place of the original negative number.
(We used the decimal numbers 3, —4, —2, 0, and 5.)
{Note: If the microprocessor being used here has a
negate instruction, that instruction will not be used.)
Enter this program into your microprocessor trainer or
computer and single-step through it. Study the program and
make sure that you understand its operation.
23-8 8086/8088 FAMILY
The 8086/8088 microprocessor works as described in the
New Concepts section of this chapter. The 8086/8088 can
have a very large stack, up to 64K (65,536 bytes). The
location of the top-of-the-stack is calculated by using both
the stack pointer and the stack segment.
We’ll look at several sample programs which you can
enter into your microprocessor trainer or computer and
examine.
Setting the Stack Pointer
Our first example program illustrates how to set the stack
pointer to a desired address and then call a subroutine. It
;load values into
; registers
;push then decrement stack pointer
;push then decrement stack pointer again
;pull then increment stack pointer
;pull then increment stack pointer again
; stop
;load values into
; registers
;push then decrement stack pointer
;push then decrement stack pointer again
;pull then increment stack pointer
;pull then increment stack pointer again
; stop
is important to note that, with the simple programs we have
used throughout this text, setting the stack pointer is
normally not required. The microprocessor trainer or com¬
puter you are working with will have an operating system
that will set the stack pointer to a logical address based on
available memory.
Figure 23-25 contains our example program. It sets the
stack pointer to a desired address and then calls a subroutine.
The subroutine does not actually do anything. It gives you
a chance to single-step through a program and watch the
stack pointer and program counter.
Calling More than One Subroutine (Not Nested)
Our next example program is shown in Fig. 23-26.
The two subroutines shown here occur one after the
other. They are not nested. You should single-step through
this program and watch the stack pointer and program
counter. This is important because the next program will
also contain two subroutines, but they will be nested. We
want you to see the difference between the two.
Again, these first programs do not do anything. Just
observe the behavior of the program counter and the stack
pointer.
Nesting Subroutines
The program shown in Fig. 23-27 also has two subroutines.
They are nested, however.
Chapter 23 Subroutine and Stack Instructions 373
A06D/ADA5 program
□□□1
1 AO □
• or 9
lADOh
□ □□2
1 ADD
□ □□3
1AQQ
21
1C
1A
START:
LXI
H,LIST
UUUA
1AQ3
□ b
□ b
MVI
B, Dbh
□ □□5
1A □ 5
□ 5
GETNUM:
DCR
B
□ □□b
1A □ b
CA
IB
1A
JZ DONE
□ □□?
iAoq
7E
MOV
A , M
ODD A
1 ADA
FE
□ □
CPI
□ □h
□ □□3
1 ADC
F2
12
1A
JP NEXT
□ □ID
1ADF
CD
lb
1A
CALL
NEGNUM
□ □11
1A12
23
NEXT:
INX
H
□ □12
1A13
C3
□ 5
1A
JMP
GETNUM
□ □13
1A1 b
2F
NEGNUM :
CM A
unit
1A1?
Cb
□ 1
ADI
□ Ih
□ □15
1A13
77
MOV
M, A
□ □lb
1A1A
C3
RET
□ □1?
1A IB
7b
DONE :
HLT
□ □1A
1A 1C
□ □13
1A 1C
□3FCFEDDD5
LIST:
. db
3,
□ □2D
1A21
□ □21
1A21
.end
ZAO program
□ □□1
1 ADD
.org lAODh
□ □□2
1 ADO
□ □□3
1ADD
21
1C
1A
START:
LD HL,LIST
UUUA
1603
□ b
□ b
LD B/Dbh
□ □□5
1A □ 5
□ 5
GETNUM:
DEC B
□ □□b
1A Db
CA
IB
1A
JP Z,DONE
0007
1A 03
7E
LD A,(HL)
□ □□A
1 AD A
FE
□ □
CP DDh
□ □□3
1A DC
F2
12
1A
JP P,NEXT
□ □ID
1ADF
CD
lb
1A
CALL NEGNUM
□ □11
1612
23
NEXT:
INC HL
□ □12
1613
C3
□ 5
1A
JP GETNUM
□ □13
1 Alb
2F
NEGNUM:
CPL
unit
1A17
Cb
01
ADD A,01h
□ □15
1613
77
LD (HL),A
□ □lb
1A1A
C3
RET
□ □17
1A IB
7b
DONE :
HALT
□ D1A
1A1C
□ □13
1A1C
□3ECFEDDD5
LIST:
.db 3,
□ □2D
1A21
□ □21
1A21
. end
Fig. 23-24 A useful 8080/8085/Z80 program which contains
a subroutine.
Single-step through this program and watch the stack
pointer and the program counter carefully. Notice how they
act differently from the way they did in the last program.
When you are inside the second subroutine, the stack is
holding the return addresses for both subroutines. That’s
why it decrements further.
Pushing Registers
The example program shown in Fig. 23-28 shows how to
use the stack to move information from one register to
another.
address of beginning of list
counter
decrement counter
if no items left end program
load number from list
is it positive/zero or negative?
if positive get next number now
if negative call subroutine
point to next number in list
branch back to beginning
invert all bits of negative number
add 1 to inverted bits
write absolute value over old negative value
return
stop
-2, □, 5 ;list of 5 numbers
address of beginning of list
counter
decrement counter
if no items left end program
load number from list
is it positive/zero or negative?
if positive get next number now
if negative call subroutine
point to next number in list
branch back to beginning
invert all bits of negative number
add 1 to inverted bits
write absolute value over old negative value
return
stop
-2, □ , 5 ;list of 5 numbers
The program loads registers AX and BX with a value,
pushes AX and BX onto the stack, then pulls them from
the stack in reverse order. This places the data that was in
AX in BX, and the data that was in BX in AX.
A Useful Program Containing a Subroutine
Let’s take a look at the program shown in Fig. 23-29.
This program’s purpose is as follows:
This program will read a list of five signed binary
numbers. As it reads each number, it will determine
374 Digital Computer Electronics
ADAb/ADAA program (with assembler)
1
page ,
13 E
E
3
□ □□□
CODE
SEGMENT
4
ASSUME CS:CODE , D
5
□ 1DD
ORG DlDOh
b
7
□ 1DD
BC
EEF3
START:
MOV SP/0FFF3h
A
0103
3D
NOP
3
0104
EA
□ 1D3 R
CALL SHORT SUBRTN
ID
□ ID?
CD
ED
INT EOh
11
□ 103
3D
SUBRTN
: NOP
IE
□ IDA
C3
RET
13
14
□ 1QB
CODE
ENDS
15
It END START
ADAb/ADAA program (with DEBUG)
MOV
SP,FFF3
; load
stack pointer
NOP
; misc
instructions
CALL
D1D3
; call
subroutine (watch
INT
ED
; stop
NOP
; misc
instructions
RET
;return from subroutine
Fig. 23-25 8086/8088 program loading stack pointer and
calling a subroutine.
S:CODE, SS:CODE
;load stack pointer
;misc instructions
;call subroutine (watch stack pointer)
;stop
;misc instructions
;return from subroutine
tack pointer)
ADAb/ADAA program (with assembler)
1
page ,
13 E
E
3
□ ODD
CODE
SEGMENT
4
ASSUME CS:CODE ,
5
□ 1DD
ORG DlDOh
b
7
D1DD
3D
START:
NOP
A
D1D1
EA
□ IDA
R
CALL SHORT RTNE.
3
01D4
3D
NOP
ID
□ 1D5
EA
D1DC
R
CALL SHORT RTNE.
11
□ IDA
CD
ED
INT EOh
IE
□ IDA
3D
RTNE_1
: NOP
13
D1DB
C3
RET
14
D1DC
3D
RTNE_E
: NOP
15
□ 1DD
C3
RET
lb
17
01DE
CODE
ENDS
1A
13
END START
DS:CODE, SS:CODE
Watch the stack pointer as
each subroutine is
"called" or "jumped to,"
and as execution returns
from each back to the main
program. These subroutines
are not nested.
A □ A b./A □ A A program (with DEBUG)
NOP
CALL
DID A
NOP
CALL
01DC
INT
ED
NOP
RET
NOP
RET
Watch the stack pointer as
each subroutine is
"called" or "jumped to,"
and as execution returns
from each back to the main
program. These subroutines
are not nested.
Fig. 23-26 8086/8088 program with two subroutines not
nested.
Chapter 23 Subroutine and Stack Instructions 375
ADAb/ADAA
program
(with assembler)
1
page
, i3a
a
3 □□□□
CODE
SEGMENT
4
ASSUME CS:CODE,
5 DIDO
ORG niODh
b
7 0100
qo
START: NOP
A
EA
□ 10L
R
CALL SHORT RTNE_
3 U1UA
CD
ao
INT aOh
10 010L
3D
RTNE_
.1: NOP
11 DID?
EA
010B
R
CALL SHORT RTNE_
ia DIDA
C3
RET
13 □10B
qo
RTNE_
.a: NOP
IA EDI DC
C3
RET
15
10 010D
CODE
ENDS
17
IA
END START
ADAb/ADAA
program
(with DEBUG)
NOP
CALL 010 L
—
int ao
^_
Again, watch the stack
NOP
pointer as each subroutine is
CALL DiDB
"called" or "jumped to,"
and as execution returns
RET
**
from each subroutine. These
NOP
—*
subroutines are nested.
RET
—
SS:CODE
Again, watch the stack
pointer as each subroutine is
"called" or "jumped to,"
and as execution returns
from each subroutine. These
subroutines are nested.
Fig. 23-27 8086/8088 program with two nested subroutines.
ADAb/ADAA program (with
assembler)
1 page ,132
a
3
0000
CODE
SEGMENT
A
ASSUME CS:CODE,
DS:CODE, SS:CODE
5
r
□ 100
ORG OlODh
b
7
0100
BA
133A
START:
MOV AX,ia34h
;load values into
A
0103
BB
5L7 A
MOV BX,5L7 Ah
; registers
q
OlDta
5D
PUSH AX
;push then decrement stack pointer
10
□ 107
53
PUSH BX
;push then decrement stack pointer aga
11
□ IDA
5 A
POP AX
;pop then increment stack pointer
ia
oioq
5B
POP BX
;pop then increment stack pointer agai
13
□ IDA
CD
ao
INT ODh
; stop
1 A
15
□ 10C
CODE
ENDS
1L
17
END START
ADA L/A □ A A program
MOV
AX,ia34
MOV
BX,5L7 A
PUSH
AX
PUSH
BX
POP
AX
POP
BX
INT
ao
(with DEBUG)
;load values into
; registers
;push then decreme
;push then decreme
;pop then incremen
;pop then incremen
; stop
nt stack pointer
nt stack pointer again
t stack pointer
t stack pointer again
Fig. 23-28 8086/8088 program which pushes a register.
376 Digital Computer Electronics
AOAk/AOAA program (with assembler)
1 page ,132
2
3 □□□□ CODE SEGMENT
ASSUME CS:CODE, DS:CODE, SS:CODE
;address of beginning of list
;counter
;decrement counter
;if no items left end program
;load number from list
;is it positive/zero or negative?
;if positive get next number now
;if negative call subroutine
;point to next number in list
;branch back to beginning
jinvert all bits of negative number
;add 1 to inverted bits
;write absolute value over old
negative value
; return
; stop
; list of 5 numbers
A 0 A k/A 0 A A program (with DEBUG)
jaddress of beginning of list
;counter
;decrement counter
;if no items left end program
;load number from list
;is it positive/zero or negative?
;if positive get next number now
;if negative call subroutine
;point to next number in list
;branch back to beginning
jinvert all bits of negative number
;add 1 to inverted bits
;write absolute value over old negative value
;return
; stop
e 0125 03 FC FE □□ 05
Fig. 23-29 A useful 8086/8088 program which contains a
subroutine.
whether that number is positive or 0 or negative. If
it is positive or 0, it will do nothing with the num¬
ber. If the number is negative, a subroutine will be
entered. This subroutine will find the absolute value
of the number (that is, it will make the negative num¬
ber positive). It will then write this positive number
into memory in place of the original negative number
Chapter 23 Subroutine and Stack Instructions 377
(We used the decimal numbers 3, -4, -2, 0, and 5.)
(Note: If the microprocessor being used here has a
negate instruction, that instruction will not be used.)
Enter this program into your microprocessor trainer or
computer and single-step through it. Study the program and
make sure that you understand its operation.
a D100
MOV BX,□□□□
MOV CL,0k
DEC CL
JZ 0120
MOV AL,[BX+0122]
CMP AL,00
JGE DllA
CALL 0117
INC BX
JMP 0105
NOT AL
ADD AL, 01
MOV [BX+0122],AL
RET
INT 20
SELF TESTING REVIEW
Read each of the following and provide the missing words.
Answers appear at the beginning of the next question.
1. _are used when there are common tasks
which must be executed or used many times.
2. ( Subroutines) The structure of the stack is a
_type of structure.
3. (FILO) The act of putting a piece of data on the top
of the stack is called_the data onto the
stack.
4 . (pushing) The act of removing a piece of data from
the top of the stack is called-or
_the data from the stack.
5. ( pulling , popping) The instruction that is usually the
last instruction in a subroutine, and that tells the
microprocessor to go back to the place where it was
before the subroutine was called, is the-
instruction.
6. (return) In general, the programmer can push onto
and pull from the stack one or more of the micropro¬
cessor’s _
(registers)
PROBLEMS
Solve the following problem using the microprocessor of
your choice. This will be the longest program you have
written thus far. Therefore, this chapter has only this one
program for you to write. The program can be considered
correct only if it causes the correct values to be placed in
the counter variables and alters the original list correctly.
23 - 1 .
A 1 -byte unsigned number can range from 00 to
FF. Each number in this range has a correspond¬
ing ASCII value. The primary categories within
the ASCII table are shown below. (The characters
from 80-FF are not actually official ASCII char¬
acters but are used to form the extended IBM
character set.)
00-IF
various control characters
20-2F
punctuation marks
30-39
numbers
o
I
<
CO
punctuation marks
41 -5A
uppercase letters
5B-60
punctuation marks
61 -7A
lowercase letters
7B-7F
punctuation marks
80-FF
foreign letters, boxes,
math symbols, miscellaneous
Write a program
in which the main part of the
program examines consecutive bytes from a list
which ends with the number FF. This main pro¬
gram section then determines which category each
value in the list is from. Different subroutines will
then be called, depending on which category a
value belongs to.
If the value represents a lowercase letter, a
subroutine called LOWER will increment a mem¬
ory location called NUM_LW, which indicates
the number of lowercase letters found.
If the value represents an uppercase letter, a
subroutine called UPPER will increment a mem¬
ory location called NUM_UP, which indicates the
number of uppercase letters found.
If the value represents a number, a subroutine
called NUM will change the number to its corre¬
sponding binary value. (The ASCII value for a
number and the binary value for that number are
not the same.) The subroutine will then store the
binary value in the list in place of the original
ASCII value and then increment a memory loca¬
tion called NUM_N, which indicates the number
of numbers found.
If the number represents a control character, the
program will do nothing.
If the value represents a punctuation mark, a
subroutine called PUNCT will increment a mem¬
ory location called NUM_P, which indicates the
number of punctuation marks found.
If the value represents one of the special char¬
acters in the range from 80 to FF, a subroutine
called SPECL will change the uppermost bit of
the number from a 1 to a 0. This change will
cause the value to fit into one of the previously
mentioned categories. The subroutine SPECL will
then return to the main program, which is to be
arranged in such a way that this converted value
will be evaluated a second time to determine its
new category and have the appropriate subroutine
called.
Place the following hexadecimal values in the
list: 00, IF, 20, 2F, 30, 39, 3A, 40, 41, 5A, SB,
60, 61, 7A, 7B, 7F, 80, and FF. (FF is not
actually a value to be evaluated but marks the end
of the list.)
378 Digital Computer Electronics
PART 4
MICROPROCESSOR INSTRUCTION SF.T TARIFS
0F 8085,8080 AND 280 (8080 subset) instructions listed
Micro Mnemonic Operation 8085>sz-a-p^ T # Address Op Boolean/Arith.
Z80 > sz-H-PNC Mode Operation
CPU Control Instruction.*}
8085
NOP
No Operation
xx-x-x-x
1 Implied 00 nothing
Can be used to create time
Z80
NOP
No Operation
4
xx-x-xxx
delays or leave extra spaces for
instructions to be inserted at a
later time.
8085
HLT
HALT
xx-x-x-x 5
1 Implied 76 stop processing
(8080 = 7 states)
Z80
HALT
HALT
xx-x-xxx 4
Data Transfer Instructions
8085
MOV AA
MOVe data to A from A
xx-x-x-x
1 Register
(8080 = 5 T states)
Z80
LD AyA
LoaD data into A
from A
xx-x-xxx
4
7F
A A
8085
MOV A,B
MOVe data to A from B
xx-x-x-x
1 Register
(8080 = 5 T states)
Z80
LD A,B
LoaD data into A
from B
xx-x-xxx
4
78
A<-B
8085
MOV A.C
MOVe data to A from C
xx-x-x-x
1 Register
(8080 = 5 T states)
Z80
LD A,C
LoaD data into A
from C
xx-x-xxx
4
79
A C
8085
MOV A,D
MOVe data to A from D
xx-x-x-x
1 Register
(8080 = 5 T states)
Z80
LD A,D
LoaD data into A
xx-x-xxx
4
7A
A <- D
from D
8085
MOV A,E
MOVe data to A from E xx-x-x-x
Z80
LD A,E
4
1 Register 7B A <- E
LoaD data into A xx-x-xxx
from E
(8080 = 5 T states)
381
EXPANDED TABLE OF 8085/8080 AND Z80 (8080 SUBSET) INSTRUCTIONS LISTED
BY CATEGORY ( Continued)
Micro Mnemonic Operation 8085>s2>a-p-c T # Address Op Boolean/Arith. Notes
Z80>sZtH-pnc Mode Operation
8085 MOV A,H MOVe data to A from H xx-x-x-x
4 1 Register 7C A «- H
Z80 LD A,H LoaD data into A xx-x-xxx
from H
(8080 = 5 T states)
8085 MOV A,L MOVe data to A from L xx-x-x-x
4 1 Register 7D A «- L
Z80 LD A,L LoaD data into A xx-x-xxx
from L
(8080 = 5 T states)
8085 MOV A,M MOVe data to A from M xx-x-x-x
7 1
Z80 LD A,(HL) LoaD data into A xx-x-xxx
from (HL)
The data byte found at the
Reg Ind 7E A «- M HL memory location pointed to by
the HL register pair is copied
into the accumulator.
8085 MOV B,A MOVe data to B from A xx-x-x-x
4 1 Register 47 B «- A
Z80 LD BA LoaD data into B xx-x-xxx
from A
(8080 = 5 T states)
8085 MOV B,B MOVe data to B from B xx-x-x-x
4 1 Register 40 B «- B
Z80 LD B,B LoaD data into B xx-x-xxx
from B
(8080 = 5 T states)
8085 MOV B,C MOVe data to B from C xx-x-x-x
4 1 Register 41 B «- C
Z80 LD B,C LoaD data into B xx-x-xxx
from C
(8080 = 5 T states)
8085 MOV B,D MOVe data to B from D xx-x-x-x
4 1 Register 42 B <- D
Z80 LD B,D LoaD data into B xx-x-xxx
from D
8085 MOV B,E MOVe data to B from E xx-x-x-x
4 1 Register 43 B *■ E
Z80 LD B,E LoaD data into B xx-x-xxx
from E
(8080 = 5 T states)
(8080 = 5 T states)
8085 MOV B,H MOVe data to B from H xx-x-x-x
4 1 Register 44 B «- H
Z80 LD B,H LoaD data into B xx-x-xxx
from H
(8080 = 5 T states)
382 Microprocessor Instruction Set Tables
Micro Mnemonic Operation
Notes
8085>sz-a-P-c T # Address Op Boolean/Arith.
Z80>sZtH-pnc Mode Operation
8085
MOV B,L
MOVe data to B from L xx-x-x-x
Z80
LD B,L
LoaD data into B xx-x-xxx
from L
Register 45 B «- L
(8080 = 5 T states)
8085 MOV B,M MOVe data to B from xx-x-x-x
m hl
Z80 LD B,(HL) LoaD data into B xx-x-xxx
from (HL)
1 Reg Ind 46 B «- M.
HL
The data byte found at the
memory location pointed to by
the HL register pair is copied
into register B.
8085
Z80
MOV CA
LD CA
MOVe data to C from A
xx-x-x-x
4
1
Register
4F
C «- A
(8080 = 5 T states)
LoaD data into C
from A
xx-x-xxx
8085
Z80
MOV C,B
LD C,B
MOVe data to C from B
xx-x-x-x
4
1
Register
48
C <- B
(8080 = 5 T states)
LoaD data into C
from B
xx-x-xxx
8085
Z80
MOV C,C
LD C,C
MOVe data to C from C
xx-x-x-x
4
1
Register
49
C«-C
(8080 = 5 T states)
LoaD data into C
from C
xx-x-xxx
8085
MOV C,D
MOVe data to C from D xx-x-x-x
Z80
LD C,D
LoaD data into C xx-x-xxx
from D
Register 4A C «- D
(8080 = 5 T states)
8085 MOV C,E
MOVe data to C from E xx-x-x-x
(8080 = 5 T states)
Z80 LD C,E
4
1 Register 4B C«- E
LoaD data into C xx-x-xxx
from E
8085 MOV C,H
Z80 LD C,H
8085
MOV C,L
MOVe data to C from L xx-x-x-x
(8080 = 5 T states)
Z80
LD C,L
4
1 Register 4D C«- L
LoaD data into C xx-x-xxx
from L
MOVe data to C from H xx-x-x-x
LoaD data into C xx-x-xxx
from H
4 1 Register 4C C«- H
- 5 T states)
Microprocessor Instruction Set Tables 383
EXPANDED TABLE OF 8085/8080 AND Z80 (8080 SUBSET) INSTRUCTIONS LISTED
BY CATEGORY ( Continued)
Micro Mnemonic Operation 8085 > sz-a-p-c T # Address Op Boolean/Arith. Notes
Z80 > sz-H-PNC Mode Operation
8085
MOV C,M
MOVe data to C from xx-x-x-x
M„ l
LoaD data into C xx-x-xxx
7
1
Reg Ind
4E
c-m hl
The data byte found at the
memory location pointed to by
Z80
LD C,(HL)
the HL register pair is copied
from (HL)
into register C
8085
MOV DA
MOVe data to D from A xx-x-x-x
4
1
Register
57
D ♦* A
(8080 = 5 T states)
Z80
LD DA
LoaD data into D xx-x-xxx
from A
8085
MOV D,B
MOVe data to D from B xx-x-x-x
4
1
Register
50
D <- B
(8080 = 5 T states)
Z80
LD D,B
LoaD data into D xx-x-xxx
from B
8085
MOV D,C
MOVe data to D from C xx-x-x-x
4
1
Register
51
D <- C
(8080 = 5 T states)
Z80
LD D,C
LoaD data into D xx-x-xxx
from C
8085
MOV D,D
MOVe data to D from D xx-x-x-x
4
1
Register
52
D <- D
(8080 = 5 T states)
Z80
LD D,D
LoaD data into D xx-x-xxx
from D
8085
MOV D,E
MOVe data to D from E xx-x-x-x
4
1
Register
53
D «- E
(8080 = 5 T states)
Z80
LD D,E
LoaD data into D xx-x-xxx
from E
8085
MOV D,H
MOVe data to D from H xx-x-x-x
4
1
Register
54
D <- H
(8080 = 5 T states)
Z80
LD D,H
LoaD data into D xx-x-xxx
from H
8085
MOV D,L
MOVe data to D from L xx-x-x-x
4
1
Register
55
D <- L
(8080 = 5 T states)
Z80
LD D,L
LoaD data into D xx-x-xxx
from L
8085
MOV D,M
MOVe data to D from xx-x-x-x
The data byte found at the
m hl
7
1
Reg Ind
56
d<-m hl
memoiy location pointed to by
Z80
LD D,(HL)
LoaD data into D xx-x-xxx
the HL register pair is copied
from (HL)
into register D.
384 Microprocessor Instruction Set Tables
Micro Mnemonic Operation
Notes
8085 > S2>A-P-c T # Address Op Boolean/Arith.
Z80 > sz-H-PNc Mode Operation
8085
MOV EA
MOVe data to E from A xx-x-x-x
Z80
LD EA
4
1 Register 5F E «* A
LoaD data into E xx-x-xxx
from A
(8080 = 5 T states)
8085
MOV E,B
MOVe data to E from B xx-x-x-x
Z80
LD E,B
LoaD data into E xx-x-xxx
from B
Register 58 E B
(8080 = 5 T states)
8085
MOV E,C
MOVe data to E from C xx-x-x-x
Z80
LD E,C
4
LoaD data into E xx-x-xxx
1 Register 59 E «- C
from C
8085 MOV E,D
MOVe data to E from D xx-x-x-x
Z80 LD E,D
4
1 Register 5A E«- D
LoaD data into E xx-x-xxx
from D
8085
MOV E,E
MOVe data to E from E xx-x-x-x
Z80
LD E,E
4
LoaD data into E xx-x-xxx
from E
1 Register
5B
E«- E
8085
MOV E,H
MOVe data to E from H xx-x-x-x
Z80
LD E,H
4
LoaD data into E xx-x-xxx
from H
1 Register
5C
E«- H
(8080 = 5 T states)
(8080 = 5 T states)
(8080 = 5 T states)
(8080 = 5 T states)
8085
MOV E,L
MOVe data to E from L xx-x-x-x
Z80
LD E,L
4
LoaD data into E xx-x-xxx
1 Register 5D E«- L
from L
(8080 - 5 T states)
8085 MOV E,M MOVe data to E from xx-x-x-x
M hl
Z80 LD E t (HL) LoaD data into E
from (HL)
1 Reglnd 5E E«- M,
xx-x-xxx
HL
The data byte found at the
memory location pointed to by
the HL register pair is copied
into register E.
8085 MOV HA MOVe data to H from A xx-x-x-x
4
Z80 LD HA LoaD data into H xx-x-xxx
from A
Register 67 H * A
(8080 = 5 T states)
Microprocessor Instruction Set Tables 385
EXPANDED TABLE OF 8085/8080 AND Z80 (8080 SUBSET) INSTRUCTIONS LISTED
BY CATEGORY ( Continued )
Micro Mnemonic Operation 8085>sz-A-p.c T # Address Op Boolean/Arith. Notes
Z80>sz-h-pnc Mode Operation
8085
MOV H,B
MOVe data to H from B
xx-x-x-x
4
1
Register
60
H «- B
(8080 = 5 T states)
Z80
LD H,B
LoaD data into H
from B
xx-x-xxx
8085
MOV H,C
MOVe data to H from C
xx-x-x-x
4
1
Register
61
H «- C
(8080 = 5 T states)
Z80
LD H,C
LoaD data into H
from C
xx-x-xxx
8085
MOV H,D
MOVe data to H from D
xx-x-x-x
4
1
Register
62
H «• D
(8080 = 5 T states)
Z80
LD H,D
LoaD data into H
from D
xx-x-xxx
8085
MOV H,E
MOVe data to H from E
xx-x-x-x
4
1
Register
63
H <- E
(8080 = 5 T states)
Z80
LD H,E
LoaD data into H
from E
xx-x-xxx
8085
MOV H,H
MOVe data to H from H
xx-x-x-x
4
1
Register
64
H<-H
(8080 a 5 T states)
Z80
LD H,H
LoaD data into H
from H
xx-x-xxx
8085
MOV H,L
MOVe data to H from L
xx-x-x-x
4
1
Register
65
H L
(8080 = 5 T states)
Z80
LD H,L
LoaD data into H
from L
xx-x-xxx
8085
MOV H,M
MOVe data to H from
m hl
LoaD data into H
xx-x-x-x
7
1
Reg Ind
66
H*M hl
The data byte found at the
memory location pointed to by
Z80
LD H,(HL)
xx-x-xxx
the HL register pair is copied
from (HL)
into register H.
8085
MOV LA
MOVe data to L from A
xx-x-x-x
4
1
Register
6F
L<- A
(8080 = 5 T states)
Z80
LD LA
LoaD data into L
from A
xx-x-xxx
8085
MOV L,B
MOVe data to L from B
xx-x-x-x
4
1
Register
68
L«~B
(8080 = 5 T states)
Z80
LD L,B
LoaD data into L
from B
xx-x-xxx
386 Microprocessor Instruction Set Tables
Micro Mnemonic Operation
Notes
8085>sZtA-p-c T # Address Op Boolean/Arith.
Z80>sz-h-pnc Mode Operation
8085
MOV L,C
MOVe data to L from C xx-x-x-x
Z80
LD L,C
LoaD data into L xx-x-xxx
from C
Register 69 L <- C
(8080 = 5 T states)
8085
MOV L,D
MOVe data to L from D xx-x-x-x
Z80
LD L,D
LoaD data into L xx-x-xxx
from D
Register 6A L <- D
8085
MOV L,E
MOVe data to L from E xx-x-x-x
Z80
LD L,E
LoaD data into L xx-x-xxx
from E
8085
MOV L,H
MOVe data to L from H
xx-x-x-x
Z80
LD L,H
LoaD data into L
from H
xx-x-xxx
8085
MOV L,L
MOVe data to L from L
xx-x-x-x
Z80
LD L,L
LoaD data into L
from L
xx-x-xxx
1 Register 6B L «- E
1 Register 6C L «- H
1 Register 6D L«- L
(8080 = 5 T states)
(8080 = 5T states)
(8080 * 5 T states)
(8080 = 5 T states)
8085 MOV L,M
Z80 LD L,(HL)
MOVe data to L from xx-x-x-x
M hl
LoaD data into L xx-x-xxx
from (HL)
Reg Ind 6E L «- M HL
The data byte found at the
memory location pointed to by
the HL register pair is copied
into register L.
8085 MOV M^A MOVe data to M HL
from A
Z80 LD (HL),A LoaD data into (HL)
from A
1 Reg Ind 77 M HL «■ A
The data in the accumulator is
copied into the memory
location pointed to by the HL
register pair.
8085
MOV M,B
MOVe data to M HL
xx-x-x-x
from B
7 1
Z80
LD (HL),B
LoaD data into (HL)
xx-x-xxx
from B
The data in register B is copied
Reg Ind 70 M HL «- B into the memory location
pointed to by the HL register
pair.
8085
MOV M,C
MOVe data to M HL
xx-x-x-x
from C
7 1
Z80
LD (HL),C
LoaD data into (HL)
xx-x-xxx
from C
The data in register C is copied
Reg Ind 71 M HL <- C into the memory location
pointed to by the HL register
pair.
Microprocessor Instruction Set Tables 387
EXPANDED TABLE OF 8085/8080 AND Z80 (8080 SUBSET) INSTRUCTIONS LISTED
BY CATEGORY ( Continued )
Micro
Mnemonic
Operation
8085 > sz-a-p-c
Z80>sm-pnc
T
#
Address
Mode
Op
Boolean/Arith.
Operation
Notes
8085
Z80
MOV M,D
LD (HL),D
MOVe data to M HL
from D
LoaD data into (HL)
from D
xx-x-x-x
xx-x-xxx
7
1
Reg Ind
72
Mhl* d
The data in register D is copied
into the memory location
pointed to by the HL register
pair.
8085
Z80
MOV M,E
LD (HL),E
MOVe data to M HL
from E
LoaD data into (HL)
from E
xx-x-x-x
xx-x-xxx
7
1
Reg Ind
73
The data in register E is copied
into the memory location
pointed to by the HL register
pair.
8085
Z80
MOV M,H
LD (HL),H
MOVe data to M HL
from H
LoaD data into (HL)
from H
xx-x-x-x
xx-x-xxx
7
1
Reg Ind
74
m hl *h
The data in register H is copied
into the memory location
pointed to by the HL register
pair.
8085
Z80
MOV M,L
LD (HL),L
MOVe data to M HL
from L
LoaD data into (HL)
from L
xx-x-x-x
7
xx-x-xxx
1 Reg Ind
75
Mhl 4- L
The data in register L is copied
into the memory location
pointed to by the HL register
pair.
8085
MVI A.dd
MoVe Immediate dd
xx-x-x-x
The data byte immediately
to A
7
2 Immed
3E
A «- dd
following the op code is copied
Z80
LD A,dd
LoaD dd into A
xx-x-xxx
into the accumulator.
8085
MVI B,dd
MoVe Immediate dd
to B
xx-x-x-x
7
2
Immed
06
B <- dd
The data byte immediately
following the op code is copied
Z80
LD B,dd
LoaD dd into B
xx-x-xxx
into register B.
8085
MVI C,dd
MoVe Immediate dd
to C
xx-x-x-x
7
2
Immed
0E
C <- dd
The data byte immediately
following the op code is copied
Z80
LD C,dd
LoaD dd into C
xx-x-xxx
into register C.
8085
MVI D,dd
MoVe Immediate dd
to D
xx-x-x-x
7
2
Immed
16
D ♦* dd
The data byte immediately
following the op code is copied
Z80
LD D,dd
LoaD dd into D
xx-x-xxx
into register D.
8085
MVI E,dd
MoVe Immediate dd
to E
xx-x-x-x
7
2
Immed
IE
E <- dd
The data byte immediately
following the op code is copied
Z80
LD E,dd
LoaD dd into E
xx-x-xxx
into register E.
8085
MVI H,dd
MoVe Immediate dd
to H
xx-x-x-x
7
2 Immed 26 H «- dd
The data byte immediately
following the op code is copied
Z80
LD H,dd
LoaD dd into H
xx-x-xxx
into register H.
388 Microprocessor Instruction Set Tables
Micro Mnemonic Operation
Notes
8085>sz^a-p-c T # Address Op Boolean/Arith.
Z80 > sz-h-pnc Mode Operation
8085
MVI L,dd
MoVe Immediate dd
xx-x-x-x
to L
7
Z80
LD L.dd
LoaD dd into L
xx-x-xxx
8085
MVI M,dd
MoVe Immediate dd
xx-x-x-x
t° m hl
10
Z80
LD (HL),dd
LoaD dd into (HL)
xx-x-xxx
2 Immed
2E
The data byte immediately
following the op code is copied
into register L.
2 Immed/ 36 M HL <- dd
Reg Ind
The data byte immediately
following the op code is copied
into the memory location
pointed to by the HL register
pair.
8085 LXI B,dddd Load extended Im¬
mediate dddd into
register pair BC
Z80 LD BC,dddd LoaD dddd into
register pair BC
xx-x-x-x
10 3 Immed 01 BC«- dddd
xx-x-xxx
Copy bytes 3 and 2 of the
instruction into registers B and
C respectively.
8085 LXI D,dddd Load extended Im¬
mediate dddd into
register pair DE
Z80 LD DE,dddd LoaD dddd into
register pair DE
xx-x-x-x
10 3 Immed II DE *- dddd
xx-x-xxx
Copy bytes 3 and 2 of the
instruction into registers D and
E respectively.
8085 LXI H,dddd Load extended Im¬
mediate dddd into
register pair HL
Z80 LD HL,dddd LoaD dddd into
register pair HL
10 3 Immed 21 HL«- dddd
Copy bytes 3 and 2 of the
instruction into registers H and
L respectively.
8085 LDAX B LoaD Accumulator xx-x-x-x
extended with data
from mem loc BC 7
Z80 LD A,(BC) LoaD Accumulator with xx-x-xxx
data from mem loc (BC)
1 Reg Ind 0A A«-
Copy the data byte found at
the memory location pointed to
by the BC register pair into the
accumulator.
8085 LDAX D LoaD Accumulator xx-x-x-x
extended with data
from mem loc DE 7
Z80 LD A,(DE) LoaD Accumulator with xx-x-xxx
data from mem loc (DE)
Reg Ind 1A A *• M DE
Copy the data byte found at
the memory location pointed to
by the DE register pair into the
accumulator.
8085 LHLD aaaa
Z80 LD HL,(aaaa)
Load HL Direct with
data starting at aaaa
LoaD HL with data
starting at (aaaa)
xx-x-x-x
xx-x-xxx
Copy the data byte found at
16 3 Direct 2A L«- memory location aaaa into the
H * M aaaa +1 L register and the data byte
found at the next memory
location (aaaa + 1) into the H
register.
Microprocessor Instruction Set Tables 389
EXPANDED TABLE OF 8085/8080 AND Z80 (8080 SUBSET) INSTRUCTIONS LISTED
BY CATEGORY ( Continued)
Micro Mnemonic
Operation
8085 > sz-a-p-c T
# Address Op
Boolean/Arith.
Notes
Z80>sz-h-pnc
Mode
Operation
8085
LDA aaaa
LoaD Accumulator with
xx-x-x-x
Copy the contents of memory
data from mem loc aaaa
13
3
Direct
3A
A *• M aaM
location aaaa into the
Z80
LD A,(aaaa)
LoaD Accumulator with
data from mem loc
(aaaa)
xx-x-xxx
Accumulator.
8085
STA aaaa
STore Accumulator in
xx-x-x-x
Copy the contents of the
mem loc aaaa
13
3
Direct
32
M^A
accumulator into memory
Z80
LD (aaaa)A
LoaD mem loc (aaaa)
with the contents of
xx-x-xxx
location aaaa.
the Accumulator
8085
STAX B
STore Accumulator
xx-x-x-x
Copy the contents of the
extended at mem
accumulator into the memory
loc BC
7
1
Reg Ind
02
^BC * A
location pointed to by the BC
Z80
LD (BC)A
LoaD mem loc (BC)
with the contents of
the Accumulator
xx-x-xxx
register pair.
8085
STAX D
STore Accumulator
xx-x-x-x
Copy the contents of the
extended at mem
accumulator into the memory
loc DE
7
1
Reg Ind
12
^DE * A
location pointed to by the DE
Z80
LD (DE )A
LoaD mem loc (DE)
with the contents of
the Accumulator
xx-x-xxx
register pair.
8085
Z80
SHLD aaaa
LD (aaaa),HL
Store HL Direct at
mem loc aaaa
LoaD mem loc starting
at (aaaa) with con¬
tents of HL)
XX-X-X-X
xx-x-xxx
16 3 Direct
22
M^L
M^, ♦ H
Copy the contents of register L
into memory location aaaa and
the contents of register H into
the next (aaaa + 1) memory
location.
8085
XCHG
eXCHanGe DE with HL
xx-x-x-x
Exchange the contents of the
4 1 Register
EB
DE~HL
DE and HL register pairs.
Z80
EX DE,HL
Exchange DE with HL
xx-x-xxx
Flag Instructions
8085 STC
SeT Carry flag
xx-x-x-1
The carry flag is normally
4
1 Implied 37 C <* 1
designated as "CY* for the
Z80 SCF
Set Carry Flag
xx-x-xxl
8080/8085.
390 Microprocessor Instruction Set Tables
Micro Mnemonic Operation
Notes
8085 > sz-a-p-c T # Address Op Boolean/Arith.
Z80 > sz-h-pnc Mode Operation
8085 CMC
CoMpIement Carry flag xx-x-x-C
The carry flag is normally
Z80 CCF
4 1 Implied 3F C«- C
Complement Carry Flag xx-x-xxC
designated as "CY" for the
8080/8085.
Arithmetic Instructions
8085
ADD A
ADD A to A
SZ-A-P-C
Z80
ADD AA
ADD A to A
4
SZrH-POC
1
Register
87
A «- A + A
8085
ADD B
ADD B to A
SZ-A-P-C
Z80
ADD A,B
ADD B to A
4
SZ-H-P0C
1
Register
80
A <- A + B
8085
ADD C
ADD C to A
SZ-A-P-C
Z80
ADD A,C
ADD C to A
4
SZ-H-P0C
1
Register
81
A <- A + C
8085
ADD D
ADD D to A
SZ-A-P-C
Z80
ADD A,D
ADD D to A
4
SZ-H-P0C
1
Register
82
A «- A + D
8085
ADD E
ADD E to A
SZ-A-P-C
Z80
ADD A,E
ADD E to A
4
SZ-H-P0C
1
Register
83
A «- A + E
8085
ADD H
ADD H to A
SZ-A-P-C
Z80
ADD A,H
ADD H to A
4
SZ-H-P0C
1
Register
84
A <- A + H
8085
ADD L
ADD L to A
SZ-A-P-C
Z80
ADD A,L
ADD L to A
4
SZ-H-P0C
1
Register
85
A «- A + L
8085
ADD M
ADD M hl to A
SZ-A-P-C
Add the data byte whose
Z80
ADD A,(HL)
ADD (HL) to A
7
SZ-H-P0C
1
Reg Ind
86
A «- A + M hl memory location is pointed to
by the HL register pair to the
accumulator and store the
results in the accumulator.
8085
Z80
ADC A
ADC A,A
AdD with Carry A to A
AdD with Carry A to A
SZ-A-P-C
4
SZH-P0C
1
Register
8F
The carry flag is usually
A <- A + A + C designated by "CY” for the
8080/8085.
Microprocessor Instruction Set Tables 301
EXPANDED TABLE OF 8085/8080 AND Z80 (8080 SUBSET) INSTRUCTIONS LISTED
BY CATEGORY ( Continued)
Micro Mnemonic
Operation
8085>s2^ap-c T
# Address Op
Boolean/Arith.
Notes
Z80 > SZ-H-PNC
Mode
Operation
8085
ADC B
AdD with Carry B to A
SZ-A-P-C
4
1
Register
88
A «- A + B + C
The carry flag is usually
designated by "CY" for the
Z80
ADC A,B
AdD with Carry B to A
SZ-H-P0C
8080/8085.
8085
ADC C
AdD with Carry C to A
SZ-A-P-C
4
1
Register
89
A «- A + C + C
The carry flag is usually
designated by "CY* for the
Z80
ADC A,C
AdD with Carry C to A
SZ-H-P0C
8080/8085.
8085
ADC D
AdD with Carry D to A
SZ-A-P-C
4
1
Register
8A
A <- A + D + C
The carry flag is usually
designated by "CY" for the
Z80
ADC A,D
AdD with Carry D to A
SZ-H-P0C
8080/8085.
8085
ADC E
AdD with Carry E to A
SZ-A-P-C
4
1
Register
8B
A «- A + E + C
The carry flag is usually
designated by "CY" for the
Z80
ADC A,E
AdD with Carry E to A
SZ-H-P0C
8080/8085.
8085
ADC H
AdD with Carry H to A
SZ-A-P-C
4
1
Register
8C
A *■ A + H + C
The carry flag is usually
designated by "CY* for the
Z80
ADC A,H
AdD with Carry H to A
SZ-H-P0C
8080/8085.
8085
ADC L
AdD with Carry L to A
SZ-A-P-C
4
1
Register
8D
A «- A + L + C
The carry flag is usually
designated by "CY" for the
Z80
ADC A,L
AdD with Carry L to A
SZ-H-P0C
8080/8085.
8085
ADC M
AdD with Carry M HL
SZ-A-P-C
Add to the accumulator both
to A
7
1
Reg Ind
8E
A «- A + M hl + C
the contents of the memory
Z80
ADC A,(HL)
AdD with Carry (HL)
SZ^H-POC
location pointed to by the HL
to A
register pair, and the carry flag,
and then place this result in the
accumulator.
8085
SUB A
SUBtract A from A
SZ-A-P-C
4 1 Register 97 A«- A - A
Z80
SUB A
SUBtract A from A
SZ-H-P1C
8085
Z80
SUB B
SUB B
SUBtract B from A
SUBtract B from A
SZ-A-P-C
4
SZ-H-P1C
1
Register
90
A* A-B
8085
SUB C
SUBtract C from A
SZ-A-P-C
4
1
Register
91
A <- A - C
Z80
SUB C
SUBtract C from A
SZ-H-P1C
392 Microprocessor Instruction Set Tables
Micro Mnemonic Operation
Notes
8085 > sz-a-p-c T # Address Op Boolean/Arith.
Z80>sz-h-pnc Mode Operation
8085
SUB D
SUBtract D from A
SZ-A-P-C
Z80
SUB D
SUBtract D from A
4
SZ-H-P1C
1
Register
92
A <- A - D
8085
SUB E
SUBtract E from A
SZ-A-P-C
Z80
SUB E
SUBtract E from A
4
SZ-H-P1C
1
Register
93
A «■ A - E
8085
SUB H
SUBtract H from A
SZ-A-P-C
Z80
SUB H
SUBtract H from A
4
SZ-H-P1C
1
Register
94
A «- A - H
8085
SUB L
SUBtract L from A
SZ-A-P-C
Z80
SUB L
4
1
Register
95
A <- A - L
SUBtract L from A
SZ-H-P1C
8085
SUB M
SUBtract M HL from A
SZ-A-P-C
Subtract the contents of the
Z80
SUB (HL)
SUBtract (HL) from A
7
SZ-H-P1C
1
Reg Ind
96
a*a-m hl
memoiy location pointed to by
the HL register pair from the
contents of the accumulator.
8085
SBB A
SuBtract with Borrow
SZ-A-P-C
Z80
SBC AA
A from A
4
1
Register
9F
A «- A - A - C
SuBtract with Carry
A from A
SZ-H-P1C
8085
SBB B
SuBtract with Borrow
SZ-A-P-C
Z80
SBC A,B
B from A
4
1
Register
98
A A - B - C
SuBtract with Cany
B from A
SZ-H-P1C
8085
SBB C
SuBtract with Borrow
SZ-A-P-C
Z80
SBC A,C
C from A
4
1
Register
99
A «- A - C - C
SuBtract with Cany
C from A
SZ-H-P1C
8085
SBB D
SuBtract with Borrow
SZ-A-P-C
Z80
SBC A,D
D from A
4
1
Register
9A
A «- A - D - C
SuBtract with Carry
D from A
SZ-H-P1C
8085
SBB E
SuBtract with Borrow
SZ-A-P-C
Z80
SBC A,E
E from A
4
1
Register
9B
A«- A-E-C
SuBtract with Carry
E from A
SZ-H-P1C
Microprocessor Instruction Set Tables 393
EXPANDED TABLE OF 8085/8080 AND Z80 (8080 SUBSET) INSTRUCTIONS LISTED
BY CATEGORY ( Continued)
Micro
Mnemonic
Operation 8085 > sz-a-p-C
T
#
Address
Op
Boolean/Arith.
Notes
Z80 > SZ-H-PNC
Mode
Operation
8085
SBB H
SuBtract with Borrow
H from A
SZ-A-P-C
4
1
Register
9C
A A - H - C
Z80
SBC A,H
SuBtract with Carry
H from A
SZ-H-P1C
8085
SBB L
SuBtract with Borrow
L from A
SZ-A-P-C
4
1
Register
9D
A «- A - L- C
Z80
SBC A,L
SuBtract with Carry
L from A
SM-PIC
8085
SBB M
SuBtract with Borrow
SZrA-P-C
Subtract from the contents of
M ut from A
7
1
Reg Ind
9E
A «■ A - M hl - C
the accumulator both the carry
Z80
SBC A,(HL)
nt
SuBtract with Carry
(HL) from A
SM-P1C
flag and the contents of the
memory location pointed to by
the HL register pair.
8085
DAD B
Double AdD BC to HL
xx-x-x-C
10
1
Register
09
HL <- HL + BC
Z80
ADD HL,BC
ADD BC to HL
xx-x-xOC
11
8085
DAD D
Double AdD DE to HL
xx-x-x-C
10
1
Register
19
HL <- HL + DE
Z80
ADD HL,DE
ADD DE to HL
xx-x-xOC
11
8085
DAD H
Double AdD HL to HL
xx-x-x-C
10
1
Register
29
HL <- HL + HL
Z80
ADD HL,HL
ADD HL to HL
xx-x-xOC
11
8085
ADI dd
AdD Immediate dd to A
SZ-A-P-C
7
2
Immed
C6
A «- A + dd
Z80
ADD A,dd
ADD dd to A
SZ-H-P0C
8085
ACI dd
AdD with Carry Im¬
mediate dd to A
SZ-A-P-C
7
2
Immed
CE
A «• A + dd + C
Z80
ADC A,dd
AdD with Carry dd
to A
SZ-H-P0C
8085
SUI dd
Subtract Immediate
dd from A
SZ-A-P-C
7
2
Immed
D6
A «- A - dd
Z80
SUB dd
SUBtract dd from A
SZ-H-P1C
394 Microprocessor Instruction Set Tables
Micro Mnemonic Operation
8085 > sz^A-P-c T # Address Op Boolean/Arith.
Z80 > sZrH-PNC Mode Operation
Notes
8085
Z80
SBI dd
SBC A.dd
Subtract with Borrow
Immediate dd from A
SuBtract with Carry
dd from A
SZrA-P-C
7
SZ-H-P1C
2 Immed
DE A «- A - dd - C
8085
DAA
Decimal Adjust A
SZ-A-P-C
The 8-bit contents of the
4
1 Implied
27 A «- BCD (A)
accumulator are adjusted to
Z80
DAA
Decimal Adjust A
SZ-H-PxC
form two 4-bit binary-coded-
decimal (BCD) digits.
Logical Instructions
8085
ANA A
ANd A with A
SZ-A-P-0
(8085) A flag = l
Z80
AND A
AND A with A
SZ-1-P00
4
1
Register
A7
A «- A AND A
(8080) A = ORing of bit 3
of the operands
8085
ANA B
ANd A with B
SZ-A-P-0
(8085) A flag = l
Z80
AND B
AND B with A
SZ-1-P00
4
1
Register
A0
A «- A AND B
(8080) A flag-ORing of bit 3
of the operands
8085
ANA C
ANd A with C
SZ-A-P-0
(8085) A flag =1
Z80
AND C
AND C with A
SZ.1-P00
4
1
Register
A1
A <- A AND C
(8080) A flag-ORing of bit 3
of the operands
8085
ANA D
ANd A with D
SZ-A-P-0
(8085) A flag =1
Z80
AND D
AND D with A
SZ-1-P00
4
1
Register
A2
A «- A AND D
(8080) A flag = ORing of bit 3
of the operands
8085
ANA E
ANd A with E
SZ-A-P-0
(8085) A flag=1
Z80
AND E
AND E with A
SZ-1-P00
4
1
Register
A3
A «- A AND E
(8080) A flag-ORing of bit 3
of the operands
8085
ANA H
ANd A with H
SZ-A-P-0
(8085) A flag=1
Z80
AND H
AND H with A
SZ-1-P00
4
1
Register
A4
A <- A AND H
(8080) A flag-ORing of bit 3
of the operands
8085
ANA L
ANd A with L
SZ-A-P-0
(8085) A flag=1
Z80
AND L
AND L with A
SZ-1-P0O
4
1
Register
A5
A «* A AND L
(8080) A flag-ORing of bit 3
of the operands
8085
ANA M
ANd A with M HL
SZ-A-P-0
(8085) A flag-1
Z80
AND (HL)
AND (HL) with A
SZ-1-P00
7
1
Reg Ind
A6
A * A AND M hl
(8080) A flag-ORing of bit 3
of the operands
Microprocessor Instruction Set Tables 395
EXPANDED TABLE OF 8085/8080 AND Z80 (8080 SUBSET) INSTRUCTIONS LISTED
BY CATEGORY ( Continued)
Micro
Mnemonic
Operation
8085 > sz-a-p-c
T
#
Address
Op
Boolean/Arith. Notes
Z80>sz>h-pnc
Mode
Operation
8085
XRA A
exclusively OR A
with A
SZ-O-P-O
4
1
Register
AF
A «- A XOR A
Z80
XOR A
exclusively OR A
with A
SZ-O-POO
8085
XRA B
exclusively OR A
with B
SZ-O-P-O
4
1
Register
A8
A <- A XOR B
Z80
XOR B
exclusively ORA
with B
SZ-0-P00
8085
XRA C
exclusively OR A
with C
SZ-O-P-O
4
1
Register
A9
A <- A XOR C
Z80
XOR C
exclusively OR A
with C
SZ-0-P00
8085
XRA D
exclusively ORA
with D
SZ-O-P-O
4
1
Register
AA
A «- A XOR D
Z80
XOR D
exclusively OR A
with D
SZ4J-P00
8085
XRA E
exclusively OR A
with E
SZ-O-P-O
4
1
Register
AB
A «- A XOR E
Z80
XOR E
exclusively ORA
with E
SZ-O-POO
8085
XRA H
exclusively OR A
with H
SZ-O-P-O
4
1
Register
AC
A <- A XOR H
Z80
XOR H
exclusively OR A
with H
SZ-0-P00
8085
XRA L
exclusively OR A
with L
SZ-O-P-O
4
1
Register
AD
A <- A XOR L
Z80
XOR L
exclusively OR A
with L
SZ4-P00
8085
XRA M
exclusively OR A
SZ-O-P-O
Exclusively or the contents of
with M hl
7
1
Reg Ind
AE
A «- A XOR M HL the accumulator with the
Z80
XOR (HL)
exclusively OR A
SZ4)-P00
contents of the memory
with (HL)
location pointed to by the HL
register pair.
8085
ORA A
OR A with A
SZ-O-P-O
4
1
Register
B7
A «- A OR A
Z80
ORA
OR A with A
SZ-O-POO
396 Microprocessor Instruction Set Tables
Micro
Mnemonic
Operation
8085 > sz-a-p-c
Z80>sz-h-pnc
T
#
Address
Mode
Op
Boolean/Arith.
Operation
Notes
8085
ORA B
OR A with B
SZ-O-P-O
Z80
ORB
OR A with B
SZ-0-P00
4
1
Register
B0
A*A ORB
8085
ORA C
OR A with C
SZ-O-P-O
Z80
OR C
OR A with C
SZ-0-P00
4
1
Register
B1
A <- A OR C
8085
ORAD
OR A with D
SZ-O-P-O
Z80
OR D
OR A with D
SZ-0-P00
4
1
Register
B2
A <- A OR D
8085
ORA E
OR A with E
SZ-O-P-O
Z80
OR E
OR A with E
SZ-0-P00
4
1
Register
B3
A «- A OR E
8085
ORA H
OR A with H
SZO-P-O
Z80
OR H
OR A with H
SZ-0-P00
4
1
Register
B4
A A OR H
8085
ORA L
OR A with L
SZ-O-P-O
Z80
OR L
OR A with L
SZ-0-P00
4
1
Register
B5
A «- A OR L
8085
Z80
ORA M
OR (HL)
OR A with M hl
OR A with (HL)
SZ-O-P-O
SZ-0-P00
7
1
Reg Ind
B6
A <- A OR M hl
or the contents of the
accumulator with the contents
of the memory location pointed
to by the HL register pair.
8085
Z80
ANI dd
AND dd
ANd Immediate dd
with A
AND dd with A
SZA-P-0
SZ1-P00
7
2
Immed
E6
A <- A AND dd
(8085) A flag = 1
(8080) A flag = ORing of bit
3 of operands
8085
XR] dd
exclusively OR Im-
SZ-O-P-O
mediate dd with A
7
2
Immed
EE
A «- A XOR dd
Z80
XOR dd
exclusively OR dd
SZ-O-P00
with A
8085
ORJ dd
OR Immediate dd
SZO-P-O
with A
7
2
Immed
F6
A «- A OR dd
Z80
OR dd
OR dd with A
SZ0-P00
8085
CMA
CoMplement A
xx-x-x-x
Invert every bit in the
4
1
Implied
2F
A «- A
accumulator. Form the Vs
Z80
CPL
ComPLement A
xx-l-xlx
complement.
Microprocessor Instruction Set Tables 397
EXPANDED TABLE OF 8085/8080 AND Z80 (8080 SUBSET) INSTRUCTIONS LISTED
BY CATEGORY ( Continued)
Micro Mnemonic Operation 8085 > sz-a-p-c T # Address Op Boolean/Arith. Notes
Z80>sz-h-pnc Mode Operation
Rotate and Shift Instructions
8085 RLC
Rotate Left with
xx-x-x-C
Carry
4 1 Implied 07 C^-i-A 7 ..
xx-0-x0C 1
• • A 0 -*—|
Z80 RLCA
Rotate Left with
Carry A
8085
Z80
RRC
RRCA
Rotate Right with
with Carry
Rotate Right with
Carry A
xx-x-x-C
4
xx-0-x0C
1 Implied OF |—... Aq— p* C
8085
RAL
Rotate A Left
xx-x-x-C
4
1 Implied 17 r— C^—A 7 ... Ao^i
Z80
RLA
Rotate Left A
xx-0-xOC
L . _ I
8085 RAR
Rotate A Right
xx-x-x-C
4
1 Implied IF
1
>
>
0
1
O
J
Z80 RRA
Rotate Right A
xx-O-xOC
___1
Increment and Decrement Instructions
8085
INR A
INcRement A
SZ-A-P-x
4
1
Register
3C
A <- A +
1
(8080 = 5 states)
Z80
INC A
INCrement A
SZ-H-POx
8085
INR B
INcRement B
SZ-A-P-x
4
1
Register
04
B «- B +
1
(8080 = 5 states)
Z80
INC B
INCrement B
SZ-H-POx
8085
INR C
INcRement C
SZ-A-P-x
4
1
Register
oc
C<- C +
1
(8080 = 5 states)
Z80
INC C
INCrement C
SZ-H-POx
8085
INR D
INcRement D
SZ-A-P-x
4
1
Register
14
D «-D +
1
(8080 = 5 states)
Z80
INC D
INCrement D
SZrH-P0x
8085
INR E
INcRement E
SZ-A-P-x
4
1
Register
1C
E «* E +
1
(8080 = 5 states)
Z80
INC E
INCrement E
SZ-H-POx
398 Microprocessor Instruction Set Tables
Micro
Mnemonic
Operation 8085 > sz-a-p-c
Z80>sz-h-pnc
T
#
Address
Mode
Op
Boolean/Arith.
Operation
Notes
8085
INR H
INcRement H
SZ-A-P-x
(8080 = 5 states)
4
1
Register
24
H «- H + 1
Z80
INC H
INCrement H
SZ-H-POx
8085
INR L
INcRement L
SZ-A-P-x
(8080 » 5 states)
4
1
Register
2C
L «* L + 1
Z80
INC L
INCrement L
SZ-H-PGx
8085
INR M
INcRement M HL
SZ-A-P-x
10
Z80
INC (HL)
INCrement (HL)
SZ-H-POx
11
1
Reg Ind
34
m hl m hl + 1
8085
I NX B
INcrement extended B
xx-x-x-x
(8080 = 5 states)
6
1
Register
03
BC «- BC + 1
Z80
INC BC
INCrement reg pair BC
xx-x-xxx
8085
I NX D
INcrement extended D
xx-x-x-x
(8080 = 5 states)
6
1
Register
13
DE «• DE + 1
Z80
INC DE
INCrement reg pair DE
xx-x-xxx
8085
I NX H
INcrement extended H
xx-x-x-x
(8080 = 5 states)
6
1
Register
23
HL «* HL + 1
Z80
INC HL
INCrement reg pair HL
xx-x-xxx
8085 DCR A DeCRement register A SZ-A-P-x
Z80 DEC A DECrement register A SZ-H-Plx
4 1 Register 3D A «- A - 1
(8080 = 5 states)
8085
Z80
DCR B
DeCRement register B
SZ-A-P-x
4
1
Register
05
B B - 1
(8080 as 5 states)
DEC B
DECrement register B
SZ-H-Plx
8085
DCR C
DeCRement register C
SZ-A-P-x
4
1
Register
0D
C«- C- 1
(8080 = 5 states)
Z80
DEC C
DECrement register C
SZ-H-Plx
8085
Z80
DCR D
DeCRement register D
SZ-A-P-x
4
1
Register
15
D «- D - 1
(8080 = 5 states)
DEC D
DECrement register D
SZ-H-Plx
8085
DCR E
DeCRement register E
SZ-A-P-x
4
1
Register
ID
E E - 1
(8080 = 5 states)
Z80
DEC E
DECrement register E
SZ-H-Plx
Microprocessor Instruction Set Tables 399
EXPANDED TABLE OF 8085/8080 AND Z80 (8080 SUBSET) INSTRUCTIONS LISTED
BY CATEGORY ( Continued )
Micro
Mnemonic
Operation 8085 > sz-a-p-c
T
#
Address
Op
Boolean/Arith.
Notes
Z80>sZtH-pnc
Mode
Operation
8085
DCRH
DeCRement register H
SZ-A-P-x
4
1
Register
25
H<~H-1
(8080 = 5 states)
Z80
DECH
DECrement register H
SZ-H-Plx
8085
DCRL
DeCRement register L
SZ-A-P-x
4
1
Register
2D
L «- L - 1
(8080 = 5 states)
Z80
DEC L
DECrement register L
SZ-H-Plx
8085
DCRM
DeCRement M HL
SZ-A-P-x
10
1
Reg Ind
35
m hl * m hl ' 1
Z80
DEC (HL)
DECrement (HL)
SZ-H-Plx
8085
DCX B
Decrement extended
register pair BC
xx-x-x-x
6
1
Register
0B
BC «- BC - 1
(8080 = 5 states)
Z80
DEC BC
DECrement register
pair BC
xx-x-xxx
8085
DCX D
Decrement extended
register pair DE
xx-x-x-x
6
1
Register
IB
DE «- DE - 1
(8080 = 5 states)
Z80
DEC DE
DECrement register
pair DE
xx-x-xxx
8085
DCX H
Decrement extended
register pair HL
xx-x-x-x
6
1
Register
2B
HL ^ HL - 1
(8080 = 5 states)
Z80
DEC HL
DECrement register
pair HL
xx-x-xxx
Unconditional Jump Instructions
8085
JMP aaaa
JuMP to mem loc aaaa
xx-x-x-x
10
3
Direct
C3
PC «- aaaa
Z80
JP aaaa
JumP to mem loc aaaa
xx-x-xxx
8085
PCHL
transfer to the Pro-
xx-x-x-x
6
(8080 = 5 states)
gram Counter HL
1
Register
E9
PC«^H
Transfer the contents of
Z80
JP (HL)
JumP to (HL)
xx-x-xxx
4
PCx.<-L
register H to the high-order
byte of the program counter
and the contents of register L
to the low-order byte of the
program counter.
400 Microprocessor Instruction Set Tables
Micro Mnemonic Operation
8085 > sz^a-p-c T # Address Op Boolean/Arith.
Z80 > sz-H-PNc Mode Operation
Notes
Test ('Compare') Instructions
8085
CMP A
CoMPare A to A
SZ-A-P-C
If A = A then the Z flag = 1.
Z80
4
1
Register
BF
A - A
If A < A then the C flag = 1.
CPA
ComPare A to A
SZ-H-P1C
8085
CMP B
CoMPare B to A
SZ-A-P-C
If A = B then the Z flag = 1.
Z80
4
1
Register
B8
A - B
If A < B then the C flag = 1.
CP B
ComPare B to A
SZ-H-P1C
8085
CMP C
CoMPare C to A
SZ-A-P-C
If A = C then the Z flag = 1.
Z80
4
1
Register
B9
A- C
If A < C then the C flag = 1.
CP C
ComPare C to A
SZ-H-P1C
8085
CMP D
CoMPare D to A
SZ-A-P-C
If A = D then the Z flag = 1.
Z80
4
1
Register
BA
A - D
If A < D then the C flag = 1.
CP D
ComPare D to A
SZ-H-P1C
8085
CMP E
CoMPare E to A
SZ-A-P-C
If A = E then the Z flag = 1.
Z80
4
1
Register
BB
A-E
If A < E then the C flag = 1.
CP E
ComPare E to A
SZ-H-P1C
8085
CMP H
CoMPare H to A
SZ-A-P-C
If A = H then the Z flag = 1.
Z80
4
1
Register
BC
A-H
If A < H then the C flag = 1.
CP H
ComPare H to A
SZ-H-P1C
8085
CMP L
CoMPare L to A
SZ-A-P-C
If A = L then the Z flag = 1.
Z80
4
1
Register
BD
A - L
If A < L then the C flag = 1.
CP L
Compare L to A
SZ-H-P1C
8085
CMP M
CoMPare M HL to A
SZ-A-P-C
If A = M hl then the Z flag »
7
1
Reg Ind
BE
a-m hl
1.
Z80
CP (HL)
Compare (HL) to A
SZ-H-P1C
If A < M hl then the C flag =
1.
8085
CPI dd
ComPare Immediate
SZ-A-P-C
If A = dd then the Z flag * 1.
dd to A
7
2
Immed
FE
A-dd
If A < dd then the C flag = 1.
Z80
CP dd
ComPare dd to A
SZ-H-P1C
Microprocessor Instruction Set Tables
401
EXPANDED TABLE OF 8085/8080 AND Z80 (8080 SUBSET) INSTRUCTIONS LISTED
BY CATEGORY ( Continued)
Micro Mnemonic
Operation
8085 > sz-a-p-C T
# Address Op
Boolean/Arith.
Notes
Z80>sZtH-pnc
Mode
Operation
Conditional Jumo (Branch"! Instructions
8085 JNZ aaaa Jump if Not Zero
xx-x-x-x
7/10
(8080 = 10 states)
to aaaa
3 Direct
C2 PC «- aaaa
PCl <- byte 2
Z80 JP NZ,aaaa Jump if Not Zero
xx-x-xxx
10
if Z = 0
PCjj <- byte 3
to aaaa
8085
JZ aaaa
Jump if Zero to aaaa
xx-x-x-x
7/10
3 Direct
CA PC «• aaaa
(8080 = 10 states)
PC^ <* byte 2
Z80
JP Z,aaaa
JumP if Zero to aaaa
xx-x-xxx
10
if Z = 1
PCjj «* byte 3
8085
Z80
JNC aaaa
JP NC,aaaa
Jump if No Carry
to aaaa
JumP if No Carry
to aaaa
xx-x-x-x
xx-x-xxx
7/10
3
10
Direct
D2
PC «- aaaa
if C = 0
(8080 * 10 states)
PCl *■ byte 2
PCj^ *- byte 3
8085
JC aaaa
Jump if Carry to aaaa
xx-x-x-x
7/10
(8080 = 10 states)
3
Direct
DA
PC «- aaaa
PCl «- byte 2
Z80
JP C.aaaa
JumP if Carry to aaaa
xx-x-xxx
10
if C = 1
PCjj «■ byte 3
8085
Z80
JPO aaaa
JP PO.aaaa
Jump if Parity Odd
to aaaa
JumP if Parity Odd
to aaaa
xx-x-x-x
xx-x-xxx
7/10
3
10
Direct
E2
PC «- aaaa
if P * 0
(8080 = 10 states)
PC^ <- byte 2
PCh «- byte 3
8085
JPE aaaa
Jump if Parity Even
xx-x-x-x
7/10
(8080 = 10 states)
to aaaa
3
Direct
EA
PC «* aaaa
PCl <- byte 2
Z80
JP PE,aaaa
JumP if Parity Even
xx-x-xxx
10
if P = 1
PC^ «- byte 3
to aaaa
8085
JP aaaa
Jump if Plus to aaaa
xx-x-x-x
7/10
(8080 = 10 states)
3
Direct
F2
PC «- aaaa
PCl «- byte 2
Z80
JP P,aaaa
JumP if Plus to aaaa
xx-x-xxx
10
if S = 0
PC^ «- byte 3
8085
JM aaaa
Jump if Minus to aaaa xx-x-x-x
7/10
3 Direct
FA PC «* aaaa
(8080 = 10 states)
PCl «■ byte 2
Z80
JP M,aaaa
JumP if Minus to aaaa xx-x-xxx
10
if S = 1
PCj^ *■ byte 3
Subroutine Instructions
8085
CALL aaaa
CALL subroutine
at aaaa
xx-x-x-x
18
3 Direct/
CD S «- PC^
(8080 = 17 states)
The stack pointer is
Z80
CALL aaaa
CALL subroutine
at aaaa
xx-x-xxx
17
Reg Ind
S^Pq
PC «- aaaa
decremented as each new byte
is pushed onto the stack.
PCjj <- byte 3
PCl «* byte 2
402 Microprocessor Instruction Set Tables
Micro Mnemonic Operation
Notes
8085>S2tA*p-c T # Address Op Boolean/Arith.
Z80>sz-h-pnc Mode Operation
8085 CNZ aaaa Call if Not Zero
subroutine at aaaa
Z80 CALL NZ,aaaa CALL if Not Zero
subroutine at aaaa
xx-x-x-x 9/18
if Z = 0
3
Direct/ C4
S-PC H
xx-x-xxx 10/17
Reg Ind
S *■ PCl
PC *■ aaaa
(8080 = 11/17 states)
The stack pointer is
decremented as each new byte
is pushed onto the stack.
PCn «* byte 3
PCl <- byte 2
8085 CZ aaaa Call if Zero
subroutine at aaaa
Z80 CALL Z,aaaa CALL if Zero
subroutine at aaaa
xx-x-x-x 9/18
if Z = 1
(8080 = 11/17 states)
3
Direct/ CC
S-PCh
The stack pointer is
xx-x-xxx 10/17
Reg Ind
S< - PC L
decremented as each new byte
PC «- aaaa
is pushed onto the stack.
PC H * byte 3
PCl «- byte 2
8085
CNC aaaa Call if No Carry
xx-x-x-x 9/18
if C = 0
Z80
subroutine at aaaa
3
Direct/ D4
S*PCh
s <- PC,^
PC «- aaaa
CALL NC.aaaa CALL if No Cany
subroutine at aaaa
xx-x-xxx 10/17
Reg Ind
(8080 = 11/17 states)
The stack pointer is
decremented as each new byte
is pushed onto the stack.
PCjj «- byte 3
PCl <- byte 2
8085
CC aaaa
Z80
CALL C,aaaa
Call if Carry
subroutine at aaaa
CALL if Cany
subroutine at aaaa
9/18 if C = 1
3 Direct/ DC S <- PC„
10/17 Reg Ind S «- PC^
PC «- aaaa
(8080 = 11/17 states)
The stack pointer is
decremented as each new byte
is pushed onto the stack.
PC^ ♦- byte 3
PCl <- byte 2
8085 CPO aaaa Call if Parity Odd
subroutine at aaaa
Z80 CALL PO,aaaa CALL if Parity Odd
subroutine at aaaa
xx-x-x-x
9/18
if P = 0
3
Direct/ E4
S^PCh
xx-x-xxx
10/17
Reg Ind
S^PCl
PC <- aaaa
(8080 = 11/17 states)
The stack pointer is
decremented as each new byte
is pushed onto the stack.
PCjj «• byte 3
PCl *■ byte 2
8085
CPE aaaa
Z80
CALL PE,aaaa
Call if Parity Even
subroutine at aaaa
CALL if Parity Even
subroutine at aaaa
xx-x-x-x 9/18
if P = 1
(8080 = 11/17 states)
3
Direct/ EC
S*PC„
The stack pointer is
xx-x-xxx 10/17
Reg Ind
s-r^
decremented as each new byte
PC «- aaaa
is pushed onto the stack.
PCjj «• byte 3
PCl <- byte 2
8085
CP aaaa
Z80
CALL P,aaaa
Call if Plus
subroutine at aaaa
CALL if Plus
subroutine at aaaa
9/18
3 Direct/ F4
10/17 Reg Ind
if S = 0 (8080 = 11/17 states)
s * p Cn The stack pointer is
S PCl decremented as each new byte
PC ♦* aaaa is pushed onto the stack.
PCn «- byte 3
PC^ «- byte 2
Microprocessor Instruction Set Tables 403
EXPANDED TABLE OF 8085/8080 AND Z80 (8080 SUBSET) INSTRUCTIONS LISTED
BY CATEGORY ( Continued )
Micro Mnemonic Operation 8085>sz-a-p-c T # Address Op Boolean/Arith. Notes
Z80>sz^h-pnc
Mode
Operation
8085 CM aaaa
Z80 CALL M,aaaa
Call if Minus
subroutine at aaaa
CALL if Minus
subroutine at aaaa
xx-x-x-x
xx-x-xxx
9/18
3
10/17
Direct/ FC
Reg Ind
if S = 1
s «- PCh
S<-PCl
PC <- aaaa
(8080 = 11/17 states)
The stack pointer is
decremented as each new byte
is pushed onto the stack.
PCjj <- byte 3
PCY <- byte 2
8085
RET
RET urn
xx-x-x-x
The stack pointer
is
10 1
Reg Ind
C9
PCj, *■ s
incremented as each byte
is
Z80
RET
RETum
xx-x-xxx
PCh^S
popped from the stack.
8085
RNZ
Return if Not Zero
xx-x-x-x
6/12
if Z = 0
(8080 = 5/11 states)
1
Reg Ind
CO
PCl + S
The stack pointer
is
Z80
RET NZ
RETum if Not Zero
xx-x-xxx
5/10
PCh^-S
incremented as each byte
popped from the stack.
is
8085 RZ
Return if Zero
xx-x-x-x 6/12
if Z = 1
(8080 = 5/11 states)
1 Reg Ind C8
PCl<-S
The stack pointer is
Z80 RET Z
RETum if Zero
xx-x-xxx 5/10
PCh-S
incremented as each byte is
popped from the stack.
8085 RNC
Return if No Carry
xx-x-x-x 6/12
if C = 0
(8080 = 5/11 states)
1
Reg Ind DO PC^ «- S
The stack pointer
is
Z80 RET NC
RETum if No Carry
xx-x-xxx 5/10
PC^VS
incremented as each byte
popped from the stack.
is
8085 RC
Return if Carry
xx-x-x-x 6/12
1
if C = 1
Reg Ind D8 PC^ *■ S
(8080 = 5/11 states)
The stack pointer is
Z80 RET C
RETum if Carry
xx-x-xxx 5/10
PCh * S
incremented as each byte is
popped from the stack.
8085 RPO
Return if Parity Odd xx-x-x-x
6/12
1 Reg Ind E0
if P = 0
PC^ *■ S
(8080 - 5/11 states)
The stack pointer is
Z80 RET PO
RETum if Parity Odd xx-x-xxx
5/10
PC^S
incremented as each byte is
popped from the stack.
8085 RPE
Return if Parity Even xx-x-x-x
6/12
if P = 1
(8080 = 5/11 states)
1 Reg Ind E8
PCl *" S
The stack pointer is
Z80 RET PE
RETum if Parity Even xx-x-xxx
5/10
PCh^S
incremented as each byte is
popped from the stack.
404 Microprocessor Instruction Set Tables
Micro Mnemonic
Operation
8085 > sz-a-p-c
T #
Address
Op
Boolean/Arith.
Notes
Z80>sz-h-pnc
Mode
Operation
8085
RP
Return if Plus
xx-x-x-x
6/12
if S = 0
(8080 = 5/11 states)
Z80
RET P
RETurn if Plus
xx-x-xxx
1
5/10
Reg Ind
F0
PC^S
PC„ * S
The stack pointer is
incremented as each byte is
popped from the stack.
8085
RM
Return if Minus
xx-x-x-x
6/12
if S = 1
(8080 = 5/11 states)
Z80
RET M
RETurn if Minus
xx-x-xxx
1
5/10
Reg Ind
F8
PC^S
PCh*S
The stack pointer is
incremented as each byte is
popped from the stack.
8085
RSTO
ReStarT 0
xx-x-x-x
12
S * PC„
(8080 = 11 states)
Z80
RST00H
ReStarT 00H
xx-x-xxx
1
11
Reg Ind
C7
S *" PCl
PC *• OOOOH
The stack pointer is
decremented as each new byte
is pushed onto the stack.
8085
RST 1
ReStaiT 1
xx-x-x-x
12
S.PCh
(8080 = 11 states)
Z80
RST08H
ReStaiT 08H
xx-x-xxx
1
11
Reg Ind
CF
S^PCl
PC «- 0008H
The stack pointer is
decremented as each new byte
is pushed onto the stack.
8085
RST 2
ReStaiT 2
xx-x-x-x
12
s^ PCh
(8080 = 11 states)
Z80
RST 10H
1
Reg Ind
D7
S«-PCl
The stack pointer is
decremented as each new byte
ReStarT 10H
xx-x-xxx
11
PC <- 0010H
is pushed onto the stack.
8085
RST 3
ReStarT 3
xx-x-x-x
12
S-PCn
(8080 = 11 states)
Z80
RST 18H
ReStarT 18H
xx-x-xxx
1
11
Reg Ind
DF
s PCl
PC «■ 0018H
The stack pointer is
decremented as each new byte
is pushed onto the stack.
8085
RST 4
ReStaiT 4
xx-x-x-x
12
s-P^
(8080 = 11 states)
Z80
RST20H
ReStaiT 20H
xx-x-xxx
1
11
Reg Ind
E7
S <- PCl
PC <- 0020H
The stack pointer is
decremented as each new byte
is pushed onto the stack.
8085
RST 5
ReStaiT 5
xx-x-x-x
12
s^PC„
(8080 = 11 states)
Z80
RST28H
1
Reg Ind
EF
S *■ PCl
The stack pointer is
ReStaiT 28H
xx-x-xxx
11
PC «■ 0028H
decremented as each new byte
is pushed onto the stack.
8085
RST 6
ReStaiT 6
xx-x-x-x
12
S«- PCh
(8080 = 11 states)
Z80
RST30H
1
Reg Ind
F7
PCl
The stack pointer is
ReStaiT 30H
xx-x-xxx
11
PC «- 0030H
decremented as each new byte
is pushed onto the stack.
Microprocessor Instruction Set Tables 405
EXPANDED TABLE OF 8085/8080 AND Z80 (8080 SUBSET) INSTRUCTIONS LISTED
BY CATEGORY (Continued)
Micro
Mnemonic
Operation 8085 > sz-a-p-c
T
#
Address
Op
Boolean/Arith.
Notes
Z80>sZtH-pnc
Mode
Operation
8085
RST 7
ReStarT 7
xx-x-x-x
12
S'PCh
(8080 = 11 states)
1
Reg Ind
FF
S«-PCl
The stack pointer is
Z80
RST 38H
ReStaiT 38H
xx-x-xxx
11
PC <- 0038H
decremented as each new byte
is pushed onto the stack-
Stack Instructions
8085
LXI SP,dddd
Load extended Im-
xx-x-x-x
Copy bytes 3 and 2 of the
mediate dddd into
instruction into the stack
the Stack Pointer
10
3
Immed
31
SP <- dddd
pointer.
Z80
LD SP,dddd
LoaD dddd into
the Stack Pointer
xx-x-xxx
8085
DAD SP
Double AdD SP to HL
xx-x-x-C
10
1
Register
39
HL «- HL + SP
Z80
ADD HL,SP
ADD SP to HL
xx-x-xOC
11
8085
INX SP
INcrement extended
Stack Pointer
xx-x-x-x
6
1
Register
33
SP «• SP + 1
(8080 = 5 states)
Z80
INC SP
INCrement Stack
Pointer
xx-x-xxx
8085
DCX SP
Decrement extended
Stack Pointer
xx-x-x-x
6
1
Register
3B
SP «- SP - 1
(8080 = 5 states)
Z80
DEC SP
DECrement Stack
Pointer
xx-x-xxx
8085
PUSH B
PUSH reg pair BC
xx-x-x-x
12
1
Reg Ind
C5
S «- B
(8080 = 11 states)
The stack pointer is
Z80
PUSH BC
PUSH reg pair BC
xx-x-xxx
11
s«-c
decremented as each new byte
is pushed onto the stack.
8085
PUSH D
PUSH reg pair DE
xx-x-x-x
12
1
Reg Ind
D5
S «- D
(8080 = 11 states)
The stack pointer is
Z80
PUSH DE
PUSH reg pair DE
xx-x-xxx
11
S<-E
decremented as each new byte
is pushed onto the stack.
8085
PUSH H
PUSH reg pair HL
xx-x-x-x
12
1
Reg Ind
E5
S ♦* H
(8080 = 11 states)
The stack pointer is
Z80
PUSH HL
PUSH reg pair HL
xx-x-xxx
11
S <- L
decremented as each new byte
is pushed onto the stack.
406 Microprocessor Instruction Set Tables
Micro Mnemonic Operation
Notes
8085 > sz-A-P-c T # Address Op Boolean/Arith.
Z80>sz>h-pnc Mode Operation
8085
PUSH PSW
PUSH Processor
Status Word
XX-X-X-X
12
Z80
PUSH AF
PUSH Accumulator
and Flags
XX-X-XXX
11
(8080 = 11 states)
Reg Ind F5 S <- A The stack pointer is
S «- flags decremented as each new byte
is pushed onto the stack. The
"flags" byte is assembled in the
normal order of the flags
(8080/8085 = SZ-A-P-C and
Z80 = SZ-H-PNC) for that
microprocessor.
8085 POP B POP reg pair BC
Z80 POP BC POP reg pair BC
xx-x-x-x
10 1 Reg Ind Cl C <-S
xx-x-xxx B «- S
The stack pointer is
incremented as each byte is
popped from the stack.
8085 POP D POP reg pair DE
Z80 POP DE POP reg pair DE
xx-x-x-x
10 1 Reg Ind D1 E <- S
xx-x-xxx D <- S
The stack pointer is
incremented as each byte is
popped from the stack.
8085 POP H POP reg pair HL
Z80 POP HL POP reg pair HL
xx-x-x-x
10 1 Reg Ind El L «■ S
xx-x-xxx H «* S
The stack pointer is
incremented as each byte is
popped from the stack.
8085
POP PSW
POP Processor
SZ-A-P-C
Status Word
10 1
Z80
POP AF
POP Accumulator
SZ-H-PNC
and Flag
The stack pointer is
Reg Ind FI flags «- S incremented as each byte is
A + S popped from the stack.
8085 XTHL eXchange top of xx-x-x-x 16
sTack with reg pair HL
Z80 EX (SP),HL Exchange M (Sp) with xx-x-xxx 19
reg pair HL
Reg Ind E3
L *♦ S
HwS o~o
(8080 = 18 states)
Stack pointer does not change
8085 SPHL move into SP the con¬
tents of reg pair HL
Z80 LD SP,HL LoaD into SP the con¬
tents of reg pair HL
6 1 Register F9 SP «- HL
(8080 = 5 states)
Interrupt Instructions
8085 DI
Disable Interrupts
Z80 DI
Disable Interrupts
XX-X-X-X
4 1 Implied F3 IFF «* 0
XX-X-XXX
Microprocessor Instruction Set Tables 407
EXPANDED TABLE OF 8085/8080 AND Z80 (8080 SUBSET) INSTRUCTIONS LISTED
BY CATEGORY ( Continued )
Micro
Mnemonic
Operation 8085 > sz^a-p-c
T #
Address
Op
Boolean/Arith.
Notes
Z80>sz-h-pnc
Mode
Operation
8085
El
Enable Interrupts
xx-x-x-x
4 1
Implied
FB
IFF *■ 1
Z80
El
Enable Interrupts
xx-x-xxx
8085
RIM
(not covered here - see
note at end of table)
8085
SIM
(not covered here - see
note at end of table)
Input-Output Instructions
8085
OUT dd
OUTput to port dd
xx-x-x-x
10
The contents of
the
contents of A
2
Direct
D3
dd port «■ A
accumulator are sent
to a
Z80
OUT ddA
OUTput to port dd
contents of A
xx-x-xxx
11
specified output port.
8085
IN dd
INput into A one byte
xx-x-x-x
10
One byte from the specified
from port dd
2
Direct
DB
A «- dd port
port is copied into
the
Z80
IN A,dd
INput into A one byte
from port dd
xx-x-xxx
11
(byte)
accumulator.
Address Modes
Implied
Register
Immediate
Direct
Register Indirect (Reg Ind)
Abbreviations and Explanations
a = address (a single hex digit)
aa = address (two hex digits - 1 byte)
aaaa = address (four hex digits - 2 bytes)
Flags _
If one of the flag letter designations is in the column for that
particular flag it indicates that the flag is affected by this operation
and could be set or cleared depending on the result of the operation.
One of the following could also appear in a flag column:
PSW = program status word (flags)
S = stack
SP = stack pointer
PC = program counter
IFF = interrupt enable flip-flop
A = accumulator
B,C,D,E,H,L = registers
L = low-order byte
H = high-order byte
A ? ..A 0 = accumulator bits 0 through 7
d = data (a single hex digit)
dd = data (two hex digits - 1 byte)
dddd = data (four hex digits - 2 bytes)
- = no flag is represented by this column, a blank bit in the
status register
x = flag not affected by this operation
1 = flag always set by this operation
0 = flag always cleared by this operation
8085
S - sign flag
Z = zero flag
A = auxiliary carry flag (usually labeled "AC")
P = parity flag
C = carry flag (usually labeled "CY")
408 Microprocessor Instruction Set Tables
Z80
S = sign
Z = zero flag
H = half carry flag
P = parity/overflow flag (usually labeled "P/V")
N * negative flag
C = carry flag
RIM & SIM- These two instructions related to interrupts are not
covered in this table. They apply only to the 8085
(neither is available in either the 8080 or Z80).
Addressing Modes - A Summar y
Implied: These instructions contain the source and destination of
the data by implication.
Symbols in the Page Heading
T = T states
# = number of bytes
Special Notes
Register: In this mode the operand and its source are specified and
data is operated on in the registers only.
Immediate: The data to be operated on follows the instruction op
code in memory; that is, it is the next byte in memory after the
instruction.
States = When two numbers appear in the "States*’ column
separated by a slash, the lower number indicates the
number of states if the condition is false and the
operation does not occur, and the larger number indicates
the number of states if the condition is true and the
operation does occur.
8080 = The 8080 behaves the same as the 8085 unless special
information is provided in the "Notes" column for the
8080.
Direct: The full address of the location of the operand in contained
in bytes 2 and 3, that is, the next two bytes in memory after the
instruction. The low-order byte comes first, and the high-order
second.
Register Indirect (Reg Ind): In this addressing mode several steps
are involved. Included in the instruction is a register pair, the
contents of that register pair contains the address where that
operand may be found, not the operand itself.
Microprocessor Instruction Set Tables
409
MINI TABLE OF 8085/8080 AND Z80 (8080 SUBSET) INSTRUCTIONS LISTED BY CATEGORY
8085
Z80
Op
Operation
8085
Z80
Op
Operation
CPU Control Instructions
MOV C,M
LD C,(HL)
4E
c*m hl
NOP
NOP
00
Nothing happens
MOV DA
LD DA
57
D «- A
HLT
HALT
76
Stop processing
MOV D3
LD D3
50
D «* B
MOV D,C
LD D,C
51
D «- C
Data Transfer Instructions
MOV D,D
LD D,D
52
D <- D
MOV AA
LD AA
7F
A <- A
MOV D,E
LD D,E
53
D <- E
MOV A,B
LD A,B
78
A <- B
MOV D,H
LD D,H
54
D <- H
MOV A,C
LD A,C
79
A <- C
MOV D,L
LD D,L
55
D <- L
MOV A,D
LD A,D
7A
A <- D
MOV D t M
LD D,(HL)
56
D * m hl
MOV A,E
LD A,E
7B
A «- E
MOV EA
LD EA
5F
E <- A
MOV A,H
LD A,H
1C
A<-H
MOV E3
LD E,B
58
E <- B
MOV A,L
LD A,L
ID
A<-L
MOV E,C
LD E,C
59
E <-C
MOV A,M
LD A,(HL)
7E
A <* M hl
MOV E,D
LD E,D
5A
E<-D
MOV BA
LD BA
47
B «- A
MOV E,E
LD E,E
5B
E «* E
MOV B,B
LD B3
40
B «- B
MOV E,H
LD E,H
5C
E <- H
MOV B,C
LD B,C
41
B <- C
MOV E,L
LD E,L
5D
E<-L
MOV B,D
LD B,D
42
B <* D
MOV E,M
LD E,(HL)
5E
e-m hl
MOV B,E
LD B,E
43
B <- E
MOV HA
LD HA
67
H <- A
MOV B,H
LD B,H
44
B<-H
MOV H3
LD H3
60
H<-B
MOV B,L
LD B,L
45
B L
MOV H,C
LD H,C
61
H «- C
MOV B,M
LD B,(HL)
46
b " m hl
MOV H,D
LD H,D
62
H <- D
MOV CA
LD CA
4F
C <- A
MOV H,E
LD H,E
63
H <- E
MOV C,B
LD C3
48
C<r B
MOV H,H
LD H,H
64
H H
MOV C,C
LD C,C
49
c*-c
MOV H,L
LD H,L
65
H «■ L
MOV C,D
LD C,D
4A
C<-D
MOV H,M
LD H,(HL)
66
h-m hl
MOV C,E
LD C,E
4B
C<-E
MOV LA
LD LA
6F
L <- A
MOV C,H
LD C,H
4C
C<-H
MOV L3
LD L,B
68
L+ B
MOV C,L
LD C,L
4D
C «- L
MOV L,C
LD L,C
69
L <- C
410 Microprocessor Instruction Set Tables
8085
Z80
Op
Operation
8085
Z80
Op
Operation
MOV L,D
LD L,D
6A
L«- D
STAX D
LD (DE)A
12
^DE A
MOV L,E
LD L,E
6B
L <- E
SHLD aaaa
LD (aaaa),HL
22
MOV L,H
LD L,H
6C
L<-H
M aaaa + 1 ” H
MOV L,L
LD L,L
6D
L «- L
XCHG
EX DE,HL
EB
DE » HL
MOV L,M
LD L,(HL)
6E
l-m hl
MOV MA
LD (HL)A
77
M hl ** A
Flag Instructions
MOV M,B
LD (HL),B
70
M hl «- B
STC
SCF
37
C + 1
MOV M,C
LD (HL),C
71
m hl ** c
CMC
CCF
3F
c<- C
MOV M,D
LD (HL),D
72
m hl * D
MOV M,E
LD (HL),E
73
M hl E
Arithmetic
Instructions
MOV M,H
LD (HL),H
74
M H l H
MOV M,L
LD (HL),L
75
M hl L
ADDA
ADD AA
87
A *■ A + A
MVI A,dd
LD A,dd
3E
A <- dd
ADD B
ADD A.B
80
A <- A + B
MVI B,dd
LD B,dd
06
B <- dd
ADD C
ADD A,C
81
A <- A + C
MVI C,dd
LD C,dd
0E
C <- dd
ADD D
ADD A,D
82
A «- A + D
MVI D,dd
LD D,dd
16
D <- dd
ADD E
ADD A.E
83
A «- A + E
MVI E,dd
LD E,dd
IE
E <- dd
ADD H
ADD A,H
84
A <■ A + H
MVI H,dd
LD H,dd
26
H <- dd
ADD L
ADD A,L
85
A «■ A + L
MVI L,dd
LD L,dd
2E
L «- dd
ADD M
ADD A,(HL)
86
A <- A + M hl
MVI M,dd
LD (HL),dd
36
m hl *■ dd
ADC A
ADC AA
8F
A <■ A + A + C
LXI B,dddd
LD BC.dddd
01
BC «- dddd
ADC B
ADC A,B
88
A «• A + B + C
LXI D,dddd
LD DE.dddd
11
DE *■ dddd
ADC C
ADC A,C
89
A *■ A + C + C
LXI H,dddd
LD HL.dddd
21
HL <- dddd
ADC D
ADC A,D
8A
A «■ A + D + C
LDAX B
LD A,(BC)
0A
a^m bc
ADC E
ADC A,E
8B
A «- A + E + C
LDAX D
LD A,(DE)
1A
A *■ M de
ADC H
ADC A,H
8C
A «- A + H + C
LHLD aaaa
LD HL,(aaaa)
2A
ADC L
ADC A,L
8D
A «- A + L + C
H - M_ m
ADC M
ADC A,(HL)
8E
A <- A + M hl + C
LDA aaaa
LD A,(aaaa)
3A
SUB A
SUB A
97
A <- A - A
STA aaaa
LD (aaaa)^A
32
A
SUB B
SUB B
90
A <- A - B
STAX B
LD (BC)A
02
M BC *" A
SUB C
SUB C
91
A «■ A - C
Microprocessor Instruction Set Tables 411
MINI TABLE OF 8085/8080 AND Z80 (8080 SUBSET) INSTRUCTIONS LISTED BY CATEGORY ( Continued )
8085
Z80
Op
Operation
8085
Z80
Op
Operation
SUB D
SUB D
92
A «• A - D
ANA H
AND H
A4
A <- A AND H
SUB E
SUB E
93
A <- A - E
ANAL
AND L
A5
A «- A AND L
SUB H
SUB H
94
A *■ A - H
ANA M
AND (HL)
A6
A «- A AND M hl
SUB L
SUB L
95
A «- A - L
XRA A
XOR A
AF
A «- A XOR A
SUB M
SUB (HL)
96
A <• A -
XRA B
XORB
A8
A «- A XOR B
SBB A
SBC AA
9F
A <- A - A - C
XRA C
XOR C
A9
A «- A XOR C
SBB B
SBC A,B
98
A «- A - B - C
XRA D
XOR D
AA
A «- A XOR D
SBB C
SBC A,C
99
A *■ A - C - C
XRA E
XOR E
AB
A «- A XOR E
SBB D
SBC A,D
9A
A <- A - D - C
XRA H
XOR H
AC
A <- A XOR H
SBB E
SBC A,E
9B
A <- A - E - C
XRA L
XOR L
AD
A «- A XOR L
SBB H
SBC A,H
9C
A*- A-H-C
XRA M
XOR (HL)
AE
A +■ A XOR M hl
SBB L
SBC A,L
9D
A «- A - L - C
ORA A
ORA
B7
A <- A OR A
SBB M
SBC A,(HL)
9E
A *■ A - M hl - C
ORAB
ORB
B0
A «- A OR B
DAD B
ADD HLJBC
09
HL «- HL + BC
ORA C
OR C
B1
A «- A OR C
DAD D
ADD HL,DE
19
HL <- HL + DE
ORAD
ORD
B2
A^-AORD
DAD H
ADD HL,HL
29
HL «- HL + HL
ORAE
ORE
B3
A «■ A OR E
ADI dd
ADD A,dd
C6
A <- A + dd
ORAH
OR H
B4
A A OR H
A Cl dd
ADC A,dd
CE
A <- A + dd + C
ORAL
ORL
B5
A<*AORL
SUI dd
SUB dd
D6
A <■ A - dd
ORA M
OR (HL)
B6
A *- A OR M hl
SBI dd
SBC A,dd
DE
A <- A - dd - C
ANI dd
AND dd
E6
A *■ A AND dd
DAA
DAA
27
A «- BCD (A)
XRI dd
XOR dd
EE
A A XOR dd
ORI dd
OR dd
F6
A A OR dd
Logical Instructions
—
CMA
CPL
2F
A «- A
ANA A
AND A
A7
A <- A AND A
ANA B
AND B
A0
A ♦- A AND B
Rotate and Shift Instructions
ANA C
AND C
A1
A <- A AND C
RLC
RLCA
07
n
-t
>
>
o
J
ANA D
AND D
A2
A «- A AND D
1...J
ANA E
AND E
A3
A *■ A AND E
RRC
RRCA
OF
|—*-a 7 ... Aq p^c
412 Microprocessor Instruction Set Tables
8085
Z80
Op
Operation
8085
Z80
Op
Operation
RAL
RLA
17
|“ c *-A 7 .. . A 0 -*~
Unconditional Jump Instructions
RAR
RRA
IF
p^A 7 .. . A 0 —►C—|
JMP aaaa JP aaaa
C3
PC *■ aaaa
PCHL
JP (HL)
E9
PCh-H
PCl *■ L
Increment and Decrement Instruction*
INR A
INCA
3C
A «- A + 1
Test (Compare) Instructions
INRB
INC B
04
B <- B + 1
CMP A
CPA
BF
A - A
INR C
INC C
OC
C «- C + 1
CMP B
CP B
B8
A - B
INR D
INC D
14
D «• D + 1
CMP C
CP c
B9
A-C
INR E
INC E
1C
E «- E + 1
CMP D
CP D
BA
A-D
INR H
INCH
24
H <- H + 1
CMP E
CPE
BB
A - E
INR L
INC L
2C
L «- L + 1
CMP H
CP H
BC
A- H
INR M
INC (HL)
34
^HL *■ ^HL + 1
CMP L
CP L
BD
A-L
INXB
INC BC
03
BC *■ BC + 1
CMPM
CP (HL)
BE
a-m hl
INXD
INC DE
13
DE «- DE + 1
CPI dd
CP dd
FE
A - dd
INX H
INC HL
23
HL *■ HL + 1
DCR A
DEC A
3D
A «- A - 1
Conditional Jumo (Branch) Instructions
DCR B
DEC B
05
B <- B - 1
DCR C
DEC C
0D
C<- C- 1
JNZ aaaa
JP NZ,aaaa
C2
PC <* aaaa
If Z = 0
DCR D
DEC D
15
D «- D - 1
JZ aaaa
JP Z,aaaa
CA
PC «- aaaa
DCR E
DEC E
ID
E «- E - 1
If Z = 1
DCR H
DECH
25
H «• H - 1
JNC aaaa
JP NC,aaaa
D2
PC <- aaaa
If C = 0
DCR L
DEC L
2D
L «- L - 1
JC aaaa
JP C,aaaa
DA
PC *- aaaa
DCR M
DEC (HL)
35
m hl *■ m hl ■ 1
If C - 1
DCX B
DEC BC
OB
BC «- BC - 1
JPO aaaa
JP PO.aaaa
E2
PC <- aaaa
If P = 0
DCXD
DEC Dk
IB
DE «- DE - 1
JPE aaaa
JP PE,aaaa
EA
PC <- aaaa
DCX H
DEC HL
2B
HL «- HL - 1
If P = 1
JP aaaa
JP P,aaaa
F2
PC aaaa
If S = 0
Microprocessor Instruction Set Tables 413
MINI TABLE OF 8085/8080 AND Z80 (8080 SUBSET) INSTRUCTIONS LISTED BY CATEGORY ( Continued)
g085 Z80 Op Operation 8085_ Z80 _Op_ Operation _
JM aaaa
JP M,aaaa
FA
PC «- aaaa
RNZ
RET NZ
CO
If Z = 0
If S = 1
PC L <-S
PCh * S
RZ
RETZ
C8
If Z = 1
Subroutine Instructions
PCl *■ S
PCh-S
CALL aaaa
CALL aaaa
CD
S PCjr
S^PCl
PC «- aaaa
RNC
RET NC
DO
If C = 0
PCl *■ S
PCh-S
CNZ aaaa
CALL NZ,aaaa
C4
If Z = 0
RC
RET C
D8
If C = 1
S-PCn
S *■ PCl
PCl *■ S
PCh-S
PC <- aaaa
RPO
RET PO
E0
If P = 0
CZ aaaa
CALL Z,aaaa
CC
If Z = 1
S^PC„
S *■ PCx
PC <- aaaa
RPE
RET PE
E8
PCl^S
PCh^S
If P = 1
pc l *■ s
CNC aaaa
CALL NC,aaaa
D4
If C - 0
S^PC H
S<-PCl
PCh-S
RP
RET P
F0
If S = 0
PC «- aaaa
PCl *" S
PCh-S
CC aaaa
CALL C,aaaa
DC
If C = 1
F8
If S = 1
PCl *■ S
PC„^S
s «- PC H
S-PCl
PC «- aaaa
RM
RET M
CPO aaaa
CALL PO,aaaa
E4
If P = 0
s <- PCh
S^PC L
PC <- aaaa
RST0
RST00H
C7
S *" PCh
S «■ PCl
PC «- OOOOH
S-PCn
RST 1
RST08H
CF
CPE aaaa
CALL PE,aaaa
EC
If P = 1
s<- PCh
S *■ PCl
PC «- 0008H
S * PCl
PC«- aaaa
RST 2
RST 10H
D7
S *" PCh
S «• PCl
PC «- 0010H
If S = 0
CP aaaa
CALL P,aaaa
F4
S-PCh
PC «■ aaaa
RST 3
RST 18H
DF
s *■ PCh
S «• PCl
PC «■ 0018H
CM aaaa
CALL M,aaaa
FC
If S = 1
S<-PCh
S * PCl
PC «- aaaa
RST 4
RST 20H
E7
s «- PCh
S «• PCl
PC «- 0020H
C9
PCl«-S
PCh^S
RST 5
RST 28H
EF
S<- PCh
RET
RET
S *■ PCl
PC «- 0028H
414 Microprocessor Instruction Set Tables
8085
Z80
Op
Operation
8085
Z80
Op
Operation
RST6
RST30H
F7
S-PCh
POP D
POP DE
DI
E «- S
S PC L
D <- S
PC <- 0030H
RST 7
RST38H
FF
S-PCh
POPH
POP HL
El
L<-S
H «- S
S * PCl
PC «- 0038H
POP PSW
POP AF
FI
flags <- S
A<-S
Stack Instructions
XTHL
EX (SP),HL
E3
h ** S
LXI SP,dddd
LD SP,dddd
31
SP <- dddd
H " s < n ~o
SPHL
LD SP.HL
F9
SP *• HL
DAD SP
ADD HL,SP
39
HL <- HL + SP
I NX SP
INC SP
33
SP <- SP + 1
DCX SP
DEC SP
3B
SP <- SP - 1
Interrupt Instructions
PUSH B
PUSH BC
C5
S <- B
S <- C
DI
DI
F3
IFF 0
PUSH D
PUSH DE
D5
S<-D
El
El
FB
IFF «• 1
S <- E
PUSH H
PUSH HL
E5
S <- H
S <- L
Input-Outout InstrnrtioTiQ
PUSH PSW
PUSH AF
F5
S «- A
S «- flags
POP B
POP BC
Cl
C 4- S
OUT dd
OUT ddA
D3
dd port A
B «- S
IN dd
IN A,dd
DB
A <- dd port (byte)
CONDENSED TABLE OF 8085/8080 AND Z80 (8080 SUBSET) INSTRUCTIONS LISTED BY CATEGORY
8085
Z80
Op
CPU Control Instructions
NOP
NOP
00
HLT
HALT
76
Data Transfer Instructions
MOV AA LD AA 7F
MOV A,B LD A,B 78
MOV A,C LD A,C 79
MOV A,D LD A,D 7A
MOV A,E LD A,E 7B
8085
Z80
Op
MOV A,H
LD A,H
1C
MOV A,L
LD A,L
7D
MOV A,M
LD A,(HL)
7E
MOV BA
LD BA
47
MOV B,B
LD B,B
40
MOV B,C
LD B,C
41
MOV B,D
LD B,D
42
MOV B,E
LD B,E
43
MOV B,H
LD B,H
44
MOV B,L
LD B,L
45
MOV B,M
LD B,(HL)
46
MOV CA
LD CA
4F
MOV C,B
LD C,B
48
MOV C,C
LD C,C
49
MOV C,D
LD C,D
4A
MOV C,E
LD C,E
4B
8085
Z80
Op
MOV C,H
LD C,H
4C
MOV C,L
LD C,L
4D
MOV C,M
LD C,(HL)
4E
MOV DA
LD DA
57
MOV D,B
LD D,B
50
MOV D,C
LD D,C
51
MOV D,D
LD D,D
52
MOV D,E
LD D,E
53
MOV D,H
LD D,H
54
MOV D,L
LD D,L
55
MOV D,M
LD D,(HL)
56
MOV EA
LD EA
5F
MOV E,B
LD E,B
58
MOV E,C
LD E,C
59
MOV E,D
LD E,D
5A
MOV E,E
LD E,E
5B
Microprocessor Instruction Set Tables 415
CONDENSED TABLE OF 8085/8080 AND Z80 (8080 SUBSET) INSTRUCTIONS LISTED
BY CATEGORY ( Continued)
8085
Z80
Op
8085
Z80
Op
8085
Z80
Op
MOV E,H
LD E,H
5C
Arithmetic Instructions
ANAL
AND L
A5
MOV E,L
LD E,L
5D
ANA M
AND (HL)
A6
MOV E,M
LD E,(HL)
5E
XRA A
XOR A
AF
MOV HA
LD HA
67
ADDA
ADD AA
87
XRA B
XORB
A8
MOV H,B
LD H,B
60
ADD B
ADD A,B
80
XRA C
XOR C
A9
MOV H,C
LD H,C
61
ADD C
ADD A,C
81
XRA D
XOR D
AA
MOV H,D
LD H,D
62
ADD D
ADD A,D
82
XRA E
XOR E
AB
MOV H,E
LD H,E
63
ADD E
ADD A,E
83
XRA H
XOR H
AC
MOV H,H
LD H,H
64
ADD H
ADD A,H
84
XRA L
XOR L
AD
MOV H,L
LD H,L
65
ADD L
ADD A,L
85
XRA M
XOR (HL)
AE
MOV H,M
LD H,(HL)
66
ADD M
ADD A,(HL)
86
ORA A
ORA
B7
MOV LA
LD LA
6F
ADC A
ADC AA
8F
ORAB
ORB
B0
MOV L,B
LD L,B
68
ADC B
ADC A,B
88
ORA C
ORC
B1
MOV L,C
LD L,C
69
ADC C
ADC A,C
89
ORA D
ORD
B2
MOV L,D
LD L,D
6A
ADC D
ADC A,D
8A
ORAE
ORE
B3
MOV L,E
LD L,E
6B
ADC E
ADC A,E
8B
ORA H
OR H
B4
MOV L,H
LD L,H
6C
ADC H
ADC A,H
8C
ORA L
ORL
B5
MOV L,L
LD L,L
6D
ADC L
ADC A,L
8D
ORA M
OR (HL)
B6
MOV L,M
LD L,(HL)
6E
ADC M
ADC A,(HL)
8E
ANI dd
AND dd
E6
MOV MA
LD (HL)A
77
SUB A
SUB A
97
XRI dd
XOR dd
EE
MOV M,B
LD (HL),B
70
SUB B
SUB B
90
ORI dd
OR dd
F6
MOV M,C
LD (HL),C
71
SUB C
SUB C
91
CMA
CPL
2F
MOV M,D
LD (HL),D
72
SUB D
SUB D
92
MOV M,E
LD (HL),E
73
SUB E
SUB E
93
MOV M,H
LD (HL),H
74
SUB H
SUB H
94
MOV M,L
LD (HL),L
75
SUB L
SUB L
95
Rotate and Shift Instructions
MVI A,dd
LD A,dd
3E
SUB M
SUB (HL)
96
MVI B,dd
LD B,dd
06
SBB A
SBC AA
9F
MVI Qdd
LD C,dd
OE
SBBB
SBC A,B
98
RLC
RLCA
07
MVI D,dd
LD D,dd
16
SBB C
SBC A,C
99
RRC
RRCA
OF
MVI E,dd
LD E,dd
IE
SBB D
SBC A,D
9A
RAL
RLA
17
MVI H,dd
LD H,dd
26
SBB E
SBC A,E
9B
RAR
RRA
IF
MVI L,dd
LD L,dd
2E
SBB H
SBC A,H
9C
MVI M,dd
LD (HL),dd
36
SBB L
SBC A,L
9D
LXI B,dddd
LD BC,dddd
01
SBB M
SBC A,(HL)
9E
LXI D,dddd
LD DE,dddd
11
DAD B
ADD HL,BC
09
Increment and Decrement Instructions
LXI H,dddd
LD HL,dddd
21
DAD D
ADD HL,DE
19
LDAXB
LD A,(BC)
0A
DAD H
ADD HL,HL
29
LDAXD
LD A,(DE)
1A
ADI dd
ADD A,dd
C6
INR A
INCA
3C
LHLD aaaa
LD HL,(aaaa)
2A
ACI dd
ADC A,dd
CE
INR B
INC B
04
LDA aaaa
LD A,(aaaa)
3A
SUI dd
SUB dd
D6
INR C
INC C
OC
STA aaaa
LD (aaaa)A
32
SBI dd
SBC A,dd
DE
INR D
INC D
14
STAX B
LD (BC)A
02
DAA
DAA
27
INR E
INC E
1C
STAX D
LD (DE)A
12
INR H
INCH
24
SHLD aaaa
LD (aaaa),HL
22
INR L
INC L
2C
XCHG
EX DE,HL
EB
INR M
INC (HL)
34
Logical Instructions
INX B
INC BC
03
I NX D
INC DE
13
INX H
INC HL
23
Flag Instructions
ANA A
AND A
A7
DCR A
DEC A
3D
ANA B
AND B
A0
DCR B
DEC B
05
ANA C
AND C
A1
DCR C
DEC C
0D
STC
SCF
37
ANA D
AND D
A2
DCR D
DEC D
15
CMC
CCF
3F
ANA E
AND E
A3
DCR E
DEC E
ID
ANA H
AND H
A4
DCR H
DEC H
25
416 Microprocessor Instruction Set Tables
Z80
Op
8085
Z80
Op
DCRL
DEC L
2D
DCRM
DEC (HL)
35
DCXB
DEC BC
0B
DCX D
DEC DE
IB
DCX H
DEC HL
2B
Unconditional Jump Instructions
JMP aaaa JP aaaa C3
PCHL JP (HL) E9
Test (Compare) Instructions
CMP A
CPA
BF
CMP B
CP B
B8
CMP C
CP C
B9
CMP D
CP D
BA
CMP E
CPE
BB
CMP H
CP H
BC
CMP L
CP L
BD
CMP M
CP (HL)
BE
CPI dd
CP dd
FE
Conditional Jump (Branch) Instructions
JNZ aaaa
JP NZ,aaaa
C2
JZ aaaa
JP Z,aaaa
CA
JNC aaaa
JP NC,aaaa
D2
8085
Z80
Op
JC aaaa
JP C,aaaa
DA
JPO aaaa
JP PO,aaaa
E2
JPE aaaa
JP PE,aaaa
EA
JP aaaa
JP P,aaaa
F2
JM aaaa
JP M,aaaa
FA
Subroutine Instructions
CALL aaaa
CALL aaaa
CD
CNZ aaaa
CALL NZ,aaaa
C4
CZ aaaa
CALL Z,aaaa
CC
CNC aaaa
CALL NC,aaaa
D4
CC aaaa
CALL C,aaaa
DC
CPO aaaa
CALL PO,aaaa
E4
CPE aaaa
CALL PE,aaaa
EC
CP aaaa
CALL P,aaaa
F4
CM aaaa
CALL M,aaaa
FC
RET
RET
C9
RNZ
RET NZ
CO
RZ
RETZ
C8
RNC
RET NC
DO
RC
RETC
D8
RPO
RET PO
E0
RPE
RET PE
E8
RP
RET P
FO
RM
RET M
F8
RST 0
RST00H
C7
RST 1
RST08H
CF
RST 2
RST 10H
D7
RST 3
RST18H
DF
RST 4
RST20H
E7
RST 5
RST28H
EF
RST 6
RST30H
F7
RST 7
RST38H
FF
8085
Stack Instructions
LXI SP,dddd
LD SP,dddd
31
DAD SP
ADD HL,SP
39
INX SP
INC SP
33
DCX SP
DEC SP
3B
PUSH B
PUSH BC
C5
PUSH D
PUSH DE
D5
PUSH H
PUSH HL
E5
PUSH PSW
PUSH AF
F5
POP B
POP BC
Cl
POP D
POP DE
DI
POP H
POP HL
El
POP PSW
POP AF
FI
XTHL
EX (SP),HL
E3
SPHL
LD SP,HL
F9
Interrupt Instructions
DI DI F3
El El FB
Input-Output Instructions
OUT dd OUT ddA D3
IN dd IN A,dd DB
CONDENSED TABLE OF 8085/8080 AND Z80 (8080 SUBSET) INSTRUCTIONS LISTED BY OP CODE
Op 8080/8085 Z80_ Op 8080/8085 Z80_ Op 8080/8085 Z80
00
NOP
NOP
01
LXI B,dddd
LD BC,dddd
02
STAX B
LD (B C)A
03
INX B
INC BC
04
INR B
INC B
05
DCR B
DEC B
06
MVI B,dd
LD B,dd
07
RLC
RLCA
09
DAD B
ADD HL,BC
0A
LDAX B
LD A,(BC)
0B
DCX B
DEC BC
0C
INR C
INC C
0D
DCR C
DEC C
0E
MVI C,dd
LD C,dd
OF
RRC
RRCA
11
LXI D,dddd
LD DE.dddd
12
STAX D
LD (DE)A
13
INX D
INC DE
14
INR D
INC D
15
DCR D
DEC D
16
MVI D,dd
LD D,dd
17
RAL
RLA
19
DAD D
ADD HL,DE
1A
LDAX D
LD A,(DE)
IB
DCX D
DEC DE
1C
INRE
INCE
ID
DCR E
DEC E
IE
MVI E,dd
LD E,dd
IF
RAR
RRA
21
LXI H,dddd
LD HL,dddd
22
SHLD aaaa
LD (aaaa),HL
23
INX H
INC HL
24
INR H
INC H
Microprocessor Instruction Set Tables 417
CONDENSED TABLE OF 8085/8080 AND Z80 (8080 SUBSET) INSTRUCTIONS LISTED
BY OP CODE ( Continued )
Op
8080/8085
zso
Qp
8080/8085
25
DCRH
DECH
5F
MOV EA
26
MVI H,dd
LD H,dd
60
MOV H,B
27
DAA
DAA
61
MOV H,C
29
DAD H
ADD HL,HL
62
MOV H,D
2A
LHLD aaaa
LD HL,(aaaa)
63
MOV H,E
2B
DCX H
DEC HL
64
MOV H,H
2C
INR L
INC L
65
MOV H,L
2D
DCRL
DEC L
66
MOV H,M
2E
MVI L,dd
LD L,dd
67
MOV HA
2F
CMA
CPL
68
MOV L,B
31
LXI SP,dddd
LD SP,dddd
69
MOV L,C
32
STA aaaa
LD (aaaa)A
6A
MOV L,D
33
INX SP
INC SP
6B
MOV L,E
34
INR M
INC (HL)
6C
MOV L,H
35
DCR M
DEC (HL)
6D
MOV L,L
36
MVI M,dd
LD (HL),dd
6E
MOV L,M
37
STC
SCF
6F
MOV LA
39
DAD SP
ADD HL,SP
70
MOV M,B
3A
LDA aaaa
LD A,(aaaa)
71
MOV M,C
3B
DCX SP
DEC SP
72
MOV M,D
3C
INR A
INCA
73
MOV M,E
3D
DCR A
DEC A
74
MOV M,H
3E
MVI A,dd
LD A,dd
75
MOV M,L
3F
CMC
CCF
76
HLT
40
MOV B,B
LD B,B
77
MOV MA
41
MOV B,C
LD B,C
78
MOV A,B
42
MOV B,D
LD B,D
79
MOV A,C
43
MOV B,E
LD B,E
7A
MOV A,D
44
MOV B,H
LD B,H
7B
MOV A,E
45
MOV B,L
LD B,L
7C
MOV A,H
46
MOV B,M
LD B,(HL)
7D
MOV A,L
47
MOV BA
LD BA
7E
MOV A,M
48
MOV C,B
LD C,B
7F
MOV AA
49
MOV C,C
LD C,C
80
ADD B
4A
MOV C,D
LD C,D
81
ADD C
4B
MOV C,E
LD C,E
82
ADD D
4C
MOV C,H
LD C,H
83
ADD E
4D
MOV C,L
LD C,L
84
ADD H
4E
MOV C,M
LD C,(HL)
85
ADD L
4F
MOV CA
LD CA
86
ADD M
50
MOV D,B
LD D,B
87
ADDA
51
MOV D,C
LD D,C
88
ADC B
52
MOV D,D
LD D,D
89
ADC C
53
MOV D,E
LD D,E
8A
ADC D
54
MOV D,H
LD D,H
8B
ADC E
55
MOV D,L
LD D,L
8C
ADC H
56
MOV D,M
LD D,(HL)
8D
ADC L
57
MOV DA
LD DA
8E
ADC M
58
MOV E,B
LD E,B
8F
ADC A
59
MOV E,C
LD E,C
90
SUB B
5A
MOV E,D
LD E,D
91
SUB C
5B
MOV E,E
LD E,E
92
SUB D
5C
MOV E,H
LD E,H
93
SUB E
5D
MOV E,L
LD E,L
94
SUB H
5E
MOV E,M
LD E,(HL)
95
SUB L
Z80
Qp
8080/8085
Z80
LD EA
96
SUB M
SUB (HL)
LD H,B
97
SUB A
SUB A
LD H,C
98
SBB B
SBC A,B
LD H,D
99
SBB C
SBC A,C
LD H,E
9A
SBB D
SBC A,D
LD H,H
9B
SBB E
SBC A,E
LD H,L
9C
SBB H
SBC A,H
LD H,(HL)
9D
SBB L
SBC A,L
LD HA
9E
SBB M
SBC A,(HL)
LD L,B
9F
SBB A
SBC AA
LD L,C
A0
ANAB
AND B
LD L,D
A1
ANA C
AND C
LD L,E
A2
ANA D
AND D
LD L,H
A3
ANA E
AND E
LD L,L
A4
ANA H
AND H
LD L,(HL)
A5
ANA L
AND L
LD LA
A6
ANA M
AND (HL)
LD (HL),B
A7
ANA A
AND A
LD (HL),C
A8
XRA B
XORB
LD (HL),D
A9
XRA C
XOR C
LD (HL),E
AA
XRA D
XORD
LD (HL),H
AB
XRA E
XOR E
LD (HL),L
AC
XRA H
XOR H
HALT
AD
XRA L
XOR L
LD (HL)A
AE
XRA M
XOR (HL)
LD A,B
AF
XRA A
XOR A
LD A,C
B0
ORA B
OR B
LD A,D
B1
ORA C
OR C
LD A,E
B2
ORA D
OR D
LD A,H
B3
ORA E
ORE
LD A,L
B4
ORA H
OR H
LD A,(HL)
B5
ORAL
ORL
LD A A
B6
ORA M
OR (HL)
ADD A,B
B7
ORA A
ORA
ADD A,C
B8
CMP B
CP B
ADD AD
B9
CMP C
CP C
ADD A,E
BA
CMP D
CP D
ADD A,H
BB
CMP E
CP E
ADD A,L
BC
CMP H
CP H
ADD A,(HL)
BD
CMP L
CP L
ADD A A
BE
CMP M
CP (HL)
ADC A,B
BF
CMP A
CPA
ADC A,C
CO
RNZ
RET NZ
ADC A,D
Cl
POP B
POP BC
ADC A,E
C2
JNZ aaaa
JP NZ,aaaa
ADC A,H
C3
JMP aaaa
JP aaaa
ADC A,L
C4
CNZ aaaa
CALL NZ,aaaa
ADC A,(HL)
C5
PUSH B
PUSH BC
ADC AA
C6
ADI dd
ADD A,dd
SUB B
C7
RST0
RST00H
SUB C
C8
RZ
RET Z
SUB D
C9
RET
RET
SUBE
CA
JZ aaaa
JP Z,aaaa
SUB H
CC
CZ aaaa
CALL Z,aaaa
SUB L
CD
CALL aaaa
CALL aaaa
418 Microprocessor Instruction Set Tables
Z80
Op 8080/8085
Z80
Op 8080/8085
Z80
CE
ACI dd
ADC A,dd
CF
RST1
RST08H
DO
RNC
RET NC
D1
POP D
POP DE
D2
JNC aaaa
JP NC.aaaa
D3
OUT dd
OUT ddA
D4
CNC aaaa
CALL NC,aaaa
D5
PUSH D
PUSH DE
D6
SUI dd
SUB dd
D7
RST 2
RST 10H
D8
RC
RET C
DA
JC aaaa
JP C,aaaa
DB
IN dd
IN A,dd
DC
CC aaaa
CALL C,aaaa
DE
SBI dd
SBC A,dd
DF
RST 3
RST18H
E0
RPO
RET PO
El
POP H
POP HL
E2
JPO aaaa
JP PO,aaaa
E3
XTHL
EX (SP),HL
E4
CPO aaaa
CALL PO,aaaa
E5
PUSH H
PUSH HL
E6
ANI dd
AND dd
E7
RST 4
RST20H
E8
RPE
RET PE
E9
PCHL
JP (HL)
EA
JPE aaaa
JP PE,aaaa
EB
XCHG
EX DE,HL
EC
CPE aaaa
CALL PE,aaaa
EE
XRI dd
XOR dd
EF
RST 5
RST28H
F0
RP
RET P
FI
POP PSW
POP AF
F2
JP aaaa
JP P,aaaa
F3
DI
DI
F4
CP aaaa
CALL P,aaaa
F5
PUSH PSW
PUSH AF
F6
ORI dd
OR dd
F7
RST 6
RST30H
F8
RM
RET M
F9
SPHL
LD SP,HL
FA
JM aaaa
JP M,aaaa
FB
El
El
FC
CM aaaa
CALL M,aaaa
FE
CPI dd
CP dd
FF
RST 7
RST38H
BY 8085^8080 MNEMONIC 8085 8080 ^ Z8 ° (8 ° 8 ° SUBSET) INSTRUCTIONS LISTED ALPHABETICALLY
8085
Z80
Op
ACI dd
ADC A,dd
CE
ADC A
ADC A A
8F
ADC B
ADC A,B
88
ADC C
ADC A,C
89
ADC D
ADC A,D
8A
ADC E
ADC A,E
8B
ADC H
ADC A,H
8C
ADC L
ADC A,L
8D
ADC M
ADC A,(HL)
8E
ADD A
ADD AA
87
ADD B
ADD A,B
80
ADD C
ADD A,C
81
ADD D
ADD A,D
82
ADD E
ADD A,E
83
ADD H
ADD A,H
84
ADD L
ADD A,L
85
ADD M
ADD A,(HL)
86
ADI dd
ADD A,dd
C6
ANA A
AND A
A7
ANA B
AND B
A0
ANA C
AND C
A1
ANA D
AND D
A2
ANA E
AND E
A3
ANA H
AND H
A4
ANA L
AND L
A5
ANA M
AND (HL)
A6
ANI dd
AND dd
E6
CALL aaaa
CALL aaaa
CD
CC aaaa
CALL C,aaaa
DC
CM aaaa
CALL M,aaaa
FC
CMA
CPL
2F
CMC
CCF
3F
CMP A
CP A
BF
CMP B
CP B
B8
8085
Z80
Op
CMP C
CP c
B9
CMP D
CP D
BA
CMP E
CP E
BB
CMP H
CP H
BC
CMP L
CP L
BD
CMP M
CP (HL)
BE
CNC aaaa
CALL NC,aaaa
D4
CNZ aaaa
CALL NZ,aaaa
C4
CP aaaa
CALL P,aaaa
F4
CPE aaaa
CALL PE,aaaa
EC
CPI dd
CP dd
FE
CPO aaaa
CALL PO,aaaa
E4
CZ aaaa
CALL Z,aaaa
CC
DAA
DAA
27
DAD B
ADD HL,BC
09
DAD D
ADD HL,DE
19
DAD H
ADD HL,HL
29
DAD SP
ADD HL,SP
39
DCR A
DEC A
3D
DCRB
DEC B
05
DCR C
DEC C
0D
DCR D
DEC D
15
DCR E
DECE
ID
DCR H
DECH
25
DCR L
DEC L
2D
DCR M
DEC (HL)
35
DCXB
DEC BC
0B
DCXD
DEC DE
IB
DCX H
DEC HL
2B
DCX SP
DEC SP
3B
DI
DI
F3
El
El
FB
HLT
HALT
76
IN dd
IN A,dd
DB
8085
Z80
Op
INR A
INCA
3C
INRB
INC B
04
INR C
INC C
OC
INR D
INC D
14
INRE
INC E
1C
INR H
INCH
24
INR L
INC L
2C
INR M
INC (HL)
34
I NX B
INC BC
03
INX D
INC DE
13
I NX H
INC HL
23
INX SP
INC SP
33
JC aaaa
JP C,aaaa
DA
JM aaaa
JP M,aaaa
FA
JMP aaaa
JP aaaa
C3
JNC aaaa
JP NC,aaaa
D2
JNZ aaaa
JP NZ,aaaa
C2
JP aaaa
JP P,aaaa
F2
JPE aaaa
JP PE,aaaa
EA
JPO aaaa
JP PO,aaaa
E2
JZ aaaa
JP Z,aaaa
CA
LDA aaaa
LD A,(aaaa)
3A
LDAX B
LD A,(BC)
0A
LDAXD
LD A,(DE)
1A
LHLD aaaa
LD HL,(aaaa)
2A
LXI B,dddd
LD BC,dddd
01
LXI D,dddd
LD DE,dddd
11
LXI H,dddd
LD HL,dddd
21
LXI SP,dddd
LD SP,dddd
31
MOV AA
LD AA
7F
MOV A,B
LD A,B
78
MOV A,C
LD A,C
79
MOV A,D
LD A,D
7A
MOV A,E
LD A,E
7B
Microprocessor Instruction Set Tables 419
CONDENSED TABLE OF 8085/8080 AND Z80 (8080 SUBSET) INSTRUCTIONS LISTED ALPHABETICALLY
BY 8085/8080 MNEMONIC ( Continued )
8085
Z80
Op
MOV A,H
LD A,H
7C
MOV A,L
LD A,L
7D
MOV A,M
LD A,(HL)
7E
MOV BA
LD BA
47
MOV B,B
LD B,B
40
MOV B,C
LD B,C
41
MOV B,D
LD B,D
42
MOV B,E
LD B,E
43
MOV B,H
LD B,H
44
MOV B,L
LD B,L
45
MOV B,M
LD B,(HL)
46
MOV CA
LD CA
4F
MOV C,B
LD C,B
48
MOV C,C
LD C,C
49
MOV C,D
LD C,D
4A
MOV C,E
LD C,E
4B
MOV C,H
LD C,H
4C
MOV C,L
LD C,L
4D
MOV C,M
LD C,(HL)
4E
MOV DA
LD DA
57
MOV D,B
LD D,B
50
MOV D,C
LD D,C
51
MOV D,D
LD D,D
52
MOV D,E
LD D,E
53
MOV D,H
LD D,H
54
MOV D,L
LD D,L
55
MOV D,M
LD D,(HL)
56
MOV EA
LD EA
5F
MOV E,B
LD E,B
58
MOV E,C
LD E,C
59
MOV E,D
LD E,D
5A
MOV E,E
LD E,E
5B
MOV E,H
LD E,H
5C
MOV E,L
LD E,L
5D
MOV E,M
LD E,(HL)
5E
MOV HA
LD HA
67
MOV H,B
LD H,B
60
MOV H,C
LD H,C
61
MOV H,D
LD H,D
62
MOV H,E
LD H,E
63
MOV H,H
LD H,H
64
MOV H,L
LD H,L
65
MOV H,M
LD H,(HL)
66
MOV LA
LD LA
6F
MOV L,B
LD L,B
68
MOV L,C
LD L,C
69
MOV L,D
LD L,D
6A
MOV L,E
LD L,E
6B
8085
Z80
Op
MOV L,H
LD L,H
6C
MOV L,L
LD L,L
6D
MOV L,M
LD L,(HL)
6E
MOV MA
LD (HL)A
77
MOV M,B
LD (HL),B
70
MOV M,C
LD (HL),C
71
MOV M,D
LD (HL),D
72
MOV M,E
LD (HL),E
73
MOV M,H
LD (HL),H
74
MOV M,L
LD (HL),L
75
MVI A,dd
LD A,dd
3E
MVI B,dd
LD B,dd
06
MVI C,dd
LD C,dd
OE
MVI D.dd
LD D,dd
16
MVI E,dd
LD E,dd
IE
MVI H,dd
LD H,dd
26
MVI L,dd
LD L,dd
2E
MVI M,dd
LD (HL),dd
36
NOP
NOP
00
ORA A
ORA
B7
ORA B
ORB
B0
ORA C
ORC
B1
ORA D
ORD
B2
ORA E
ORE
B3
ORA H
OR H
B4
ORAL
ORL
B5
ORAM
OR (HL)
B6
ORI dd
OR dd
F6
OUT dd
OUT ddA
D3
PCHL
JP (HL)
E9
POP B
POP BC
Cl
POP D
POP DE
D1
POPH
POP HL
El
POP PSW
POP AF
FI
PUSH B
PUSH BC
C5
PUSH D
PUSH DE
D5
PUSH H
PUSH HL
E5
PUSH PSW
PUSH AF
F5
RAL
RLA
17
RAR
RRA
IF
RC
RET C
D8
RET
RET
C9
RLC
RLCA
07
RM
RET M
F8
RNC
RET NC
DO
RNZ
RET NZ
CO
RP
RET P
F0
8085 Z80_Op_
RPE RET PE E8
RPO RET PO E0
RRC RRCA OF
RST 0 RST 00H C7
RST1 RST 08H CF
RST 2 RST 10H D7
RST 3 RST 18H DF
RST 4 RST 20H E7
RST 5 RST 28H EF
RST 6 RST 30H F7
RST 7 RST 38H FF
RZ RET Z C8
SBB A SBC AA 9F
SBB B SBC A,B 98
SBB C SBC AC 99
SBB D SBC A,D 9A
SBB E SBC A,E 9B
SBB H SBC A,H 9C
SBB L SBC A,L 9D
SBB M SBC A,(HL) 9E
SBI dd SBC A,dd DE
SHLD aaaa LD (aaaa),HL 22
SPHL LD SP,HL F9
STA aaaa LD (aaaa)A 32
STAX B LD (BQA 02
STAX D LD (DE)A 12
STC SCF 37
SUB A SUB A
SUB B SUB B
SUB C SUB C
SUB D SUB D
SUB E SUB E
SUB H SUB H
SUB L SUB L
SUB M SUB (HL)
SUI dd SUB dd
XCHG EX DE,HL
XRA A XOR A
XRA B XOR B
XRA C XOR C
XRA D XOR D
XRA E XOR E
XRA H XOR H
XRA L XOR L
XRA M XOR (HL)
XRI dd XOR dd
XTHL EX (SP),HL
420 Microprocessor Instruction Set Tables
CONDENSED TABLE OF 8085/8080 AND Z80 (8080 SUBSET)
BY Z80 MNEMONIC
INSTRUCTIONS LISTED ALPHABETICALLY
Z80
8080/8085
Op
ADC A,(HL)
ADC M
8E
ADC AA
ADC A
8F
ADC A,B
ADC B
88
ADC A,C
ADC C
89
ADC A,D
ADC D
8A
ADC A,dd
ACI dd
CE
ADC A,E
ADC E
8B
ADC A,H
ADC H
8C
ADC A,L
ADC L
8D
ADD A,(HL)
ADD M
86
ADD AyA
ADDA
87
ADD A,B
ADD B
80
ADD A,C
ADD C
81
ADD A,D
ADD D
82
ADD A,dd
ADI dd
C6
ADD A F
Ann p?
Q->
o3
ADD A,H
ADD H
84
ADD A,L
ADD L
85
ADD HL,BC
DAD B
09
ADD HL,DE
DAD D
19
ADD HL,HL
DAD H
29
ADD HL,SP
DAD SP
39
AND (HL)
ANA M
A6
AND A
ANA A
A7
AND B
ANA B
A0
AND C
ANA C
A1
AND D
ANA D
A2
AND dd
ANI dd
E6
AND E
ANA E
A3
AND H
ANA H
A4
AND L
ANA L
A5
CALL aaaa
CALL aaaa
CD
CALL C,aaaa
CC aaaa
DC
CALL M,aaaa
CM aaaa
FC
CALL NC,aaaa
CNC aaaa
D4
CALL NZ,aaaa
CNZ aaaa
C4
CALL P,aaaa
CP aaaa
F4
CALL PE,aaaa
CPE aaaa
EC
CALL PO,aaaa
CPO aaaa
E4
CALL Z,aaaa
CZ aaaa
CC
CCF
CMC
3F
CP (HL)
CMP M
BE
CPA
CMP A
BF
CP B
CMP B
B8
CP C
CMP C
B9
CP D
CMP D
BA
CP dd
CPI dd
FE
CP E
CMP E
BB
CP H
CMP H
BC
CP L
CMP L
BD
CPL
CMA
2F
DAA
DAA
27
DEC (HL)
DCR M
35
DEC A
DCR A
3D
DEC B
DCR B
05
Z80
8080/8085
Op
DEC BC
DCX B
0B
DEC C
DCR C
0D
DEC D
DCR D
15
DEC DE
DCX D
IB
DECE
DCR E
ID
DECH
DCR H
25
DEC HL
DCX H
2B
DEC L
DCR L
2D
DEC SP
DCX SP
3B
DI
DI
F3
El
El
FB
EX (SP),HL
XTHL
E3
EX DE,HL
XCHG
EB
HALT
HLT
76
IN A,dd
IN dd
DB
INC (HL)
INRM
34
INCA
INR A
3C
INC B
INRB
04
INC BC
INX B
03
INC C
INR C
OC
INC D
INR D
14
INC DE
INX D
13
INC E
INRE
1C
INC H
INR H
24
INC HL
INX H
23
INC L
INR L
2C
INC SP
INX SP
33
JP (HL)
PCHL
E9
JP aaaa
JMP aaaa
C3
JP C,aaaa
JC aaaa
DA
JP M,aaaa
JM aaaa
FA
JP NC,aaaa
JNC aaaa
D2
JP NZ,aaaa
JNZ aaaa
C2
JP P,aaaa
JP aaaa
F2
JP PE,aaaa
JPE aaaa
EA
JP PO.aaaa
JPO aaaa
E2
JP Z,aaaa
JZ aaaa
CA
LD (aaaa)A
STA aaaa
32
LD (aaaa),HL
SHLD aaaa
22
LD (BC)A
STAX B
02
LD (DE)A
STAX D
12
LD (HL)A
MOV MA
77
LD (HL),B
MOV M,B
70
LD (HL),C
MOV M,C
71
LD (HL),D
MOV M,D
72
LD (HL),dd
MVT M,dd
36
LD (HL),E
MOV M,E
73
LD (HL),H
MOV M,H
74
LD (HL),L
MOV M,L
75
LD A,(aaaa)
LDA aaaa
3A
LD A,(BC)
LDAX B
0A
LD A,(DE)
LDAX D
1A
LD A,(HL)
MOV A,M
7E
LD AA
MOV AA
7F
LD A,B
MOV A,B
78
Z80
8080/8085
Op
LD A,C
MOV A,C
79
LD A,D
MOV A,D
7A
LD A,dd
MVI A,dd
3E
LD A,E
MOV A,E
7B
LD A,H
MOV A,H
7C
LD A,L
MOV A,L
7D
LD B,(HL)
MOV B,M
46
LD BA
MOV BA
47
LD B,B
MOV B,B
40
LD B,C
MOV B,C
41
LD BC,dddd
LXI B,dddd
01
LD B,D
MOV B,D
42
LD B,dd
MVI B,dd
06
LD B,E
MOV B,E
43
LD B,H
MOV B,H
44
LD B,L
MOV B,L
45
LD C,(HL)
MOV C,M
4E
LD CA
MOV CA
4F
LD C,B
MOV C,B
48
LD C,C
MOV C,C
49
LD C,D
MOV C,D
4A
LD C,dd
MVI C,dd
0E
LD C,E
MOV C,E
4B
LD C,H
MOV C,H
4C
LD C,L
MOV C,L
4D
LD D,(HL)
MOV D,M
56
LD DA
MOV DA
57
LD D,B
MOV D,B
50
LD D,C
MOV D,C
51
LD D,D
MOV D,D
52
LD D,dd
MVI D,dd
16
LD D,E
MOV D,E
53
LD DE,dddd
LXI D,dddd
11
LD D,H
MOV D,H
54
LD D,L
MOV D,L
55
LD E,(HL)
MOV E,M
5E
LD EA
MOV EA
5F
LD E,B
MOV E,B
58
LD E,C
MOV E,C
59
LD E,D
MOV E,D
5A
LD E,dd
MVI E,dd
IE
LD E,E
MOV E,E
5B
LD E,H
MOV E,H
5C
LD E,L
MOV E,L
5D
LD H,(HL)
MOV H,M
66
LD HA
MOV HA
67
LD H,B
MOV H,B
60
LD H,C
MOV H,C
61
LD H,D
MOV H,D
62
LD H,dd
MVI H,dd
26
LD H,E
MOV H,E
63
LD H,H
MOV H,H
64
LD H,L
MOV H,L
65
LD HL,(aaaa)
LHLD aaaa
2A
LD HL,dddd
LXI H.dddd
21
Microprocessor Instruction Set Tables 421
CONDENSED TABLE OF 8085/8080 AND Z80 (8080 SUBSET) INSTRUCTIONS LISTED ALPHABETICALLY
BY Z80 MNEMONIC ( Continued )
Z80
8080/8085
Op
Z80
8080/8085
Op
Z80
8080/8085
Op
LD L,(HL)
MOV L,M
6E
PUSH BC
PUSH B
C5
SBC A,B
SBB B
98
LD LA
MOV LA
6F
PUSH DE
PUSH D
D5
SBC A,C
SBB C
99
LD L,B
MOV L,B
68
PUSH HL
PUSH H
E5
SBC A,D
SBB D
9A
LD L,C
MOV L,C
69
RET
RET
C9
SBC A,dd
SBI dd
DE
LD L,D
MOV L,D
6A
RET C
RC
D8
SBC A,E
SBB E
9B
LD L,dd
MVI L,dd
2E
RET M
RM
F8
SBC AH
SBB H
9C
LD L,E
MOV L,E
6B
RET NC
RNC
DO
SBC AL
SBB L
9D
LD L,H
MOV L,H
6C
RET NZ
RNZ
CO
SCF
STC
37
LD L,L
MOV L,L
6D
RET P
RP
F0
SUB (HL)
SUB M
96
LD SP,dddd
LXI SP,dddd
31
RET PE
RPE
E8
SUB A
SUB A
97
LD SP,HL
SPHL
F9
RET PO
RPO
E0
SUB dd
SUI dd
D6
NOP
NOP
00
RET Z
RZ
C8
SUB B
SUB B
90
OR (HL)
ORA M
B6
RLA
RAL
17
SUB C
SUB C
91
ORA
ORA A
B7
RLCA
RLC
07
SUB D
SUB D
92
ORB
ORAB
B0
RRA
RAR
IF
SUB E
SUB E
93
OR C
ORA C
B1
RRCA
RRC
OF
SUB H
SUB H
94
OR D
ORA D
B2
RST00H
RST 0
C7
SUB L
SUB L
95
OR dd
ORI dd
F6
RST08H
RST 1
CF
XOR (HL)
XRA M
AE
OR E
ORA E
B3
RST10H
RST 2
D7
XOR A
XRA A
AF
OR H
ORA H
B4
RST18H
RST 3
DF
XOR B
XRA B
A8
OR L
ORA L
B5
RST20H
RST 4
E7
XOR C
XRA C
A9
OLTr ddA
OUT dd
D3
RST 28H
RST 5
EF
XOR D
XRA D
AA
POP AF
POP PSW
FI
RST30H
RST 6
F7
XOR dd
XRI dd
EE
POP BC
POP B
Cl
RST38H
RST 7
FF
XOR E
XRA E
AB
POP DE
POP D
D1
SBC A,(HL)
SBBM
9E
XOR H
XRA H
AC
POP HL
POPH
El
SBC AA
SBB A
9F
XOR L
XRA L
AD
PUSH AF
PUSH PSW
F5
EXPANDED TABLE OF 6800 INSTRUCTIONS LISTED BY CATEGORY
Mne- Operation Boolean/Arith. Flags Address Assembler Op - #
monic Operation HINZVC Mode_Notation_
NOP No Operation
WAI WAIt for
interrupt
CPU Control Instructions
Nothing xxxxxx Implied NOP
PC + 1 -> PC xlxxxx Implied WAI
pc l"> S
PCh + S
X L + S
x„ + s
A + S
B + S
CCR S
01 2 1 Only the program counter is
incremented. No operation
occurs.
3E 9 1 After those actions shown in
the "Boolean/Arithmetic
Operation" column take place,
the current program is
suspended. If 1 = 0 and the
Interrupt Request line is taken
low then 1 = 1 and the
microprocessor will begin to
execute a program whose
address is found in memory
locations FFF8 and FFF9.
422 Microprocessor Instruction Set Tables
Mne- Operation
monic
Boolean/Arith. Flags Address Assembler
Operation _HINZVC Mode Notation
Op
#
Notes
Data Transfer Instructions
LDAA
LoaD Accumulator A M -> A
xxNZOx
Immediate
LDAA #$dd
86
2 2
Direct
LDAA Saa
96
3 2
Indexed
LDAA Sff,X
A6
5 2
Extended
LDAA $aaaa
B6
4 3
LDAB
LoaD Accumulator B M -> B
xxNZOx
Immediate
LDAB #$dd
C6
2 2
Direct
LDAB $aa
D6
2 2
Indexed
LDAB Sff,X
E6
5 2
Extended
LDAB $aaaa
F6
4 3
STAA
STore Accumulator A A -* M
xxNZOx
Direct
STAA Saa
97
4 2
Indexed
STAA $ff,X
A7
6 2
Extended
STAA Saaaa
B7
5 3
STAB
STore Accumulator B B -» M
xxNZOx
Direct
STAB Saa
D7
4 2
Indexed
STAB $ff,X
E7
6 2
Extended
STAB Saaaa
F7
5 3
TAB
Transfer A to B A -* B
xxNZOx
Implied
TAB
16
2 1
TBA
Transfer B to A B -> A
xxNZOx
Implied
TBA
17
2 1
LDX
LoaD X register M -> X H
xxNZOx
Immediate
LDX #$dddd
CE
3 3
(M + 1) -> X L
Direct
LDX Saa
DE
4 2
Indexed
LDX Sff.X
EE
6 2
Extended
LDX Saaaa
FE
5 3
STX
STore X register X H ■+ M
xxNZOx
Direct
STX Saa
DF
5 2
X L *» (M + 1)
Indexed
STX Sff.X
EF
7 2
Extended
STX Saaaa
FF
6 3
CLR
CLeaR memory 00 ■+ M
xxOlOO
Indexed
CLR $ff,X
6F
7 2
location
Extended
CLR Saaaa
7F
6 3
CLRA
CLeaR accumulator A 00 ■+ A
xxOlOO
Implied
CLRA
4F
2 1
CLRB
CLeaR accumulator B 00 •+ B
xxOlOO
Implied
CLRB
5F
2 1
Flag Instructions
CLC CLear Cany flag 0 - C xxxxxO Implied CLC
Microprocessor Instruction Set Tables 423
Mne¬
monic
EXPANDED
Operation
TABLE OF 6800 INSTRUCTIONS LISTED BY CATEGORY ( Continued)
Boolean/Arith. Flags Address Assembler Op ~ # Notes
Operation HINZVC Mode Notation
CLI
CLear Interrupt flag
0 -► I
xOxxxx Implied
CLI
OE
2 1
CLV
CLear overflow flag
0 ■+ V
xxxxVx Implied
CLV
QA
2 1
SEC
SEt Carry flag
1 -> C
xxxxxl Implied
SEC
OD
2 1
SEI
SEt Interrupt flag
1 -► I
xlxxxx Implied
SEI
OF
2 1
SEV
SEt overflow flag
1 -► V
xxxxlx Implied
SEV
OB
2 1
TAP
Transfer Accumulator
A to Processor con¬
dition code register
A + CCR
HINZVC Implied
TAP
06
2 1
TPA
Transfer Processor
condition code reg¬
ister to accumulator
A
CCR ■* A
xxxxxx Implied
TPA
07
2 1
Arithmetic Instructions
ADDA ADO accumulator A A + M -> A
HxNZVC Immediate
ADDA #$dd
8B
2
2
to memory location
Direct
ADDA $aa
9B
3
2
Indexed
ADDA $ff,X
AB
5
2
Extended
ADDA Saaaa
BB
4
3
ADDB ADD accumulator B B + M -» B
HxNZVC Immediate
ADDB #$dd
CB
2
2
to memory location
Direct
ADDB $aa
DB
3
2
Indexed
ADDB $ff,X
EB
5
2
Extended
ADDB Saaaa
FB
4
3
ABA
Add accumulator B
to accumulator A
A + B -» A
HxNZVC Implied
ABA
IB
2 1
ADCA AdD with Carry
A + M + C -» A HxNZVC Immediate
ADCA #$dd
89
2
2
accumulator A to
Direct
ADCA Saa
99
3
2
memory location
Indexed
ADCA $ff,X
A9
5
2
Extended
ADCA Saaaa
B9
4
3
ADCB AdD with Carry
B + M + C -» B HxNZVC Immediate
ADCB #$dd
C9
2
2
accumulator B to
Direct
ADCB Saa
D9
3
2
memory location
Indexed
ADCB $ff,X
E9
5
2
Extended
ADCB Saaaa
F9
4
3
424 Microprocessor Instruction Set Tables
Mne¬
monic
SUBA
SUBB
SB A
SBCA
SBCB
DAA
ANDA
ANDB
ORAA
ORAB
Operation Boolean/Arith.
___Operation
SUBtract memory A - M -> A
location from
accumulator A
SUBtract memory B - M -> B
location from
accumulator B
Subtract accumulator A - B -> A
B from accumulator A
SuBtract with
Carry memory
location from
accumulator A
A - M - C A
SuBtract with
Carry memory
location from
accumulator B
B - M - C -► B
Decimal Adjust
(converts bin¬
accumulator A
ary number into
BCD number)
Flags Address Assembler Op ~ # Notes
HINZVC Mode Notation
xxNZVC Immediate
SUBA #$dd
80
Direct
SUBA $aa
90
Indexed
SUBA $ff,X
AO
Extended
SUBA Saaaa
BO
xxNZVC
Immediate
SUBB #$dd
CO
Direct
SUBB $aa
DO
Indexed
SUBB $ff,X
E0
Extended
SUBB Saaaa
F0
xxNZVC
Implied
SBA
10
xxNZVC Immediate
SBCA #$dd
82
Direct
SBCA Saa
92
Indexed
SBCA $ff,X
A2
Extended
SBCA Saaaa
B2
xxNZVC
Immediate
SBCB #Sdd
C2
Direct
SBCB Saa
D2
Indexed
SBCB $ff,X
E2
Extended
SBCB Saaaa
F2
xxNZVC
Implied
DAA
19
2 2
3 2
5 2
4 3
2 2
3 2
5 2
4 3
2 1
2 2
3 _2_
5 2
4 3
2 2
3 2
5 2
4 3
2 1 Converts the number in A to
the BCD number it would be if
the last two operands had been
BCD numbers.
Logical Instructions
AND accumulator A A AND M -» A
with memory loc¬
ation
AND accumulator B B AND M -> B
with memory loc¬
ation
OR Accumulator A A OR M -» A
with memory loc¬
ation
OR Accumulator B B OR M ■» B
with memory loc¬
ation
xxNZOx Immediate
ANDA #$dd
84
2
2
Direct
ANDA Saa
94
3
2
Indexed
ANDA $ff,X
A4
5
2
Extended
ANDA Saaaa
B4
4
3
xxNZOx Immediate
ANDB #$dd
C4
2
2
Direct
ANDB Saa
D4
3
2
Indexed
ANDB Sff,X
E4
5
2
Extended
ANDB Saaaa
F4
4
3
xxNZOx Immediate
ORAA #Sdd
8A
2
2
Direct
ORAA Saa
9A
3
2
Indexed
ORAA Sff,X
AA
5
2
Extended
ORAA Saaaa
BA
4
3
xxNZOx Immediate
ORAB #$dd
CA
2
2
Direct
ORAB $aa
DA
3
2
Indexed
ORAB $ff,X
EA
5
2
Extended
ORAB Saaaa
FA
4
3
Microprocessor Instruction Set Tables 42 5
EXPANDED TABLE OF 6800 INSTRUCTIONS LISTED BY CATEGORY ( Continued)
Mne¬
monic
Operation
Boolean/Arith.
Operation
Flags Address
HINZVC Mode
Assembler
Notation
Op
#
Notes
EORA
Exclusively OR
A EOR M * A
xxNZOx Immediate
EORA #ttd
88
2
2
accumulator A
Direct
EORA Saa
98
3
2
with memory
Indexed
EORA $ff,X
A8
5
2
location
Extended
EORA Saaaa
B8
4
3
EORB Exclusively OR
B EOR M *B
xxNZOx Immediate
EORB #$dd
C8
2
2
accumulator A
Direct
EORB Saa
D8
3
2
with memory
Indexed
EORB $ff,X
E8
5
2
location
Extended
EORB Saaaa
F8
4
3
BIT A BIT test
A AND M
xxNZOx Immediate
BITA #$dd
85
2
2
Accumulator A and a memory
accumulator A
Direct
BITA Saa
95
3
2
location are ANDed but neither
Indexed
BITA $ff,X
A5
5
2
is changed. However, flags N
Extended
BITA Saaaa
B5
4
3
and Z are affected accordingly.
BITB BIT test
BAND M
xxNZOx Immediate
BITB #$dd
C5
2
2
Accumulator B and a memory
accumulator B
Direct
BITB Saa
D5
3
2
location are ANDed but neither
Indexed
BITB $ff,X
E5
5
2
is changed. However, flags N
Extended
BITB Saaaa
F5
4
3
and Z are affected accordingly.
COM
COMpIement memory _
location (l’s com- M -* M
plement)
xxNZOl
Indexed
Extended
COM $ff,X
COM Saaaa
63
73
7 2
6 2
COMA
COMpIement ac¬
cumulator A A -» A
(l’s complement)
xxNZOl
Implied
COMA
43
2 1
COMB
COMpIement ac¬
cumulator B B -* B
(l’s complement)
xxNZOl
Implied
COMB
53
2 1
NEG
NEGate memory loc- 00 - M -» M
ation (2’s comple¬
ment)
xxNZVC
Indexed
Extended
NEG $ff,X
NEG Saaaa
60
70
7 2
6 3
Affects the carry flag as if the
memory location had been
subtracted from zero.
NEGA
NEGate accumu- 00 - A -> A
lator A (2’s com¬
plement)
xxNZVC
Implied
NEGA
40
2 1
Affects the carry flag as if
accumulator A had been
subtracted from zero.
NEGB
NEGate accumu- 00 - B + B
lator B (2’s com¬
plement)
xxNZVC
Implied
NEGB
50
2 1
Affects the carry flag as if
accumulator B had been
subtracted from zero.
Rotate and Shift Instructions
ROL
ROtate memory loc- j— M 7 ... Mo
ation Left | r c I
xxNZVC
Indexed
Extended
ROL $ff,X
ROL Saaaa
69
79
7 2
6 3
426 Microprocessor Instruction Set Tables
Mne- Operation
Boolean/Arith. Flags Address Assembler Op - #
Operation HINZVC Mode Notation
ROLA ROtate to the Left
accumulator A
A 7 ••• A 0 ^-1 xxNZVC Implied ROLA 49 2 1
ROtate to the Left I B 7 ... B 0 xxNZVC Implied ROLB
accumulator B |__|
ROR ROtate memory loc- r*~ M 7 ... M 0 i xxNZVC Indexed ROR $ff,X
ation Right I- C „-1 Extended ROR Saaaa
RORA ROtate to the Right
accumulator A
A? • ■ • A 0 I xxNZVC Implied RORA
r .-l
RORB ROtate to the Right
accumulator B
B 7 .. . Bp | xxNZVC Implied RORB
ASL Arithmetic Shift C -«-M 7 ... M 0 *- 0 xxNZVC Indexed ASL $ff,X 68 7 2
Left memory Extended ASL Saaaa 78 6 3
location
ASLA Arithmetic Shift C A 7 .. . A 0 ^- 0 xxNZVC Implied ASIA
Left accumulator A
48 2 1
ASLB Arithmetic Shift C B ? ... B 0 ^ 0 xxNZVC Implied ASLB
Left accumulator B
58 2 1
ASR Arithmetic Shift j~^M 7 . • • M 0 ~^ C xxNZVC Indexed ASR $ff,X 67 7 2
Right memory loc-
Extended ASR Saaaa 77 6 3
ASRA Arithmetic Shift p-A 7 ...A 0 -^C xxNZVC Implied ASRA
Right accumulator A j [
47 2 1
ASRB Arithmetic Shift i-^ B 7 . . . B 0 -► C xxNZVC Implied ASRB
Right accumulator B I
57 2 1
LSR Logical Shift Right 0 -HV1 7 ... M<f^C xxOZVC Indexed LSR $ff,X 64 7 2
memory location Extended LSR Saaaa 74 6 3
LSRA Logical Shift Right 0-> A ? ..A 0 ^ C xxOZVC Implied LSRA
accumulator A
44 2 1
LSRB Logical Shift Right 0-> B r ..B 0 -> C xxOZVC Implied LSRB
accumulator B
54 2 1
Microprocessor Instruction Set Tables 427
EXPANDED TABLE OF 6800 INSTRUCTIONS LISTED BY CATEGORY ( Continued)
Mne¬
Operation
Boolean/Arith.
Flags
Address
Assembler
Op
~
#
monic
Operation
HINZVC
Mode
Notation
Increment and Decrement Instructions
INC
INCrement memory
M + 1 -» M
xxNZVx
Indexed
INC $ff,X
6C
7
2
location
Extended
INC Saaaa
7C
6
3
INCA
INCrement accum¬
ulator A
A + 1 A
xxNZVx
Implied
INCA
4C
2
1
INCB
INCrement accum¬
ulator B
B + 1 -> B
xxNZVx
Implied
INCB
5C
2
1
DEC
DECrement memory
M - 1 M
xxNZVx
Indexed
DEC $ff,X
6A
7
2
location
Extended
DEC Saaaa
7A
6
3
DECA
DECrement accum¬
ulator A
A - 1 -> A
xxNZVx
Implied
DECA
4A
2
1
DECB
DECrement accum¬
ulator B
B- 1 B
xxNZVx
Implied
DECB
5A
2
1
I NX
INcrement X
(index) register
X + 1 ->X
xxxZxx
Implied
INX
08
4
1
DEX
DEcrement X
X-l + X
XXXzXX Implied
DEX
09
4
1
(index) register
Unconditional Jump Instructions
JMP
JuMP to memory
X + ff 4 PC
xxxxxx
Indexed
JMP Sff,X
6E
4
2
location
(indexed)
aaaa -> PC
Extended
JMP Saaaa
7E
3
3
(extended)
BRA
BRanch Always
PC + 2
xxxxxx
Relative
BRA Srr
20
4
2
to memory loc¬
ation
+ rr -» PC
Test ('Compare')
Instructions
CM PA
CoMPare memory
A-M
xxNZVC
Immediate
CM PA #$dd
81
2
2
location to
Direct
CMPA Saa
91
3
2
accumulator A
Indexed
CMPA $ff,X
A1
5
2
Extended
CMPA Saaaa
B1
4
3
CMPB
CoMPare memory
B - M
xxNZVC
Immediate
CMPB #$dd
Cl
2
2
location to
Direct
CMPB $aa
D1
3
2
accumulator B
Indexed
CMPB Sff,X
El
5
2
Extended
CMPB Saaaa
FI
4
3
Notes
428 Microprocessor Instruction Set Tables
Mne¬
monic
CBA
CPX
TST
TSTA
TSTB
BCC
BCS
BEQ
BGE
BGT
Operation
Boolean/Arith.
Operation
Flags
HINZVC
Address
Mode
Assembler
Notation
Op
#
Compare accum¬
A - B
xxNZVC
Implied
CBA
11
2
1
ulator B to
accumulator A
Compare memory
X H - M
xxNZVx
Immediate
CPX #$dddd
8C
3
3
location to X
X l -(M + 1)
Direct
CPX $aa
9C
4
2
(index) register
Indexed
CPX $ff,X
AC
6
2
Extended
CPX Saaaa
BC
5
3
TEsT memory loc¬
M - 00
xxNZOO
Indexed
TST $ff,X
6D
7
2
ation for zero or
Extended
TST Saaaa
7D
6
3
minus
TEsT accumulator A
for zero or minus
A - 00
xxNZOO
Implied
TSTA
4D
2 1
TEsT accumulator B
for zero or minus
B -00
xxNZOO
Implied
TSTB
5D
2 1
Conditional Jump fBranch") Instructions
Branch if Cany PC + 2 + rr xxxxxx Relative BCC $rr 24 4 2
Clear PC
if C=0
Branch if Carry PC + 2 + rr xxxxxx Relative BCS $rr 25 4 2
Set -► pc
if C=1
Branch if result of PC + 2 + rr
last operation was -» PC
EQual to zero ifZ=l
xxxxxx Relative BEQ $rr 27 4 2
Branch if Greater
than or Equal to
zero
PC + 2 + rr xxxxxx Relative BGE $rr
* PC
if N EOR V = 0
Branch if Greater PC + 2 + rr xxxxxx Relative BGT $rr
Than zero ■+ PC
if Z AND (N
EOR V) = 0
2C 4 2 This branch occurs after the
instructions CBA, CMP, SBA,
or SUB if the 2’s-complement
minuend is greater than or
equal to the 2’s-complement
subtrahend creating an answer
which is greater than or equal
to zero.
2E 4 2 This branch occurs after the
instructions CBA, CMP, SBA,
or SUB if the 2’s-complement
minuend is greater than the 2’s-
complement subtrahend,
creating an answer which is
greater than zero.
Microprocessor Instruction Set Tables 429
EXPANDED TABLE OE 6800 INSTRUCTIONS LISTED BY CATEGORY ( Continued)
Mne¬
monic
BHI
BLE
BLS
BLT
BMI
BNE
BVC
BVS
BPL
Operation Boolean/Arith. Flags Address Assembler Op ~ # Notes
Operation _HINZVC Mode_Notation_
Branch if Higher
PC + 2 + rr
■+ PC
if C AND Z = 0
xxxxxx
Relative
BHI Srr
22
4 2
This branch occurs after the
instructions CBA, CMP, SBA,
or SUB if the unsigned binary
minuend is greater than the
unsigned binary subtrahend.
Branch if Less
than or Equal to
zero
PC + 2 + rr
+ PC
if Z AND (N EOR
V) = 1
xxxxxx
Relative
BLE Srr
2F
4 2
This branch occurs after the
instructions CBA, CMP, SBA,
or SUB if the 2’s-complement
minuend is less than or equal
to the 2 , s-complement
subtrahend, creating an answer
which is less than or equal to
zero.
Branch if Lower
or the Same
PC + 2 + rr
-> PC
if C OR Z = 1
xxxxxx
Relative
BLS Srr
23
4 2
This branch occurs after the
instructions CBA, CMP, SBA,
or SUB if the unsigned binary
minuend is less than or equal
to the unsigned binary
subtrahend.
Branch if Less
Than zero
PC + 2 + rr
-> PC
if N EOR V = 1
xxxxxx
Relative
BLT Srr
2D
4 2
This branch occurs after the
instructions CBA, CMP, SBA,
or SUB if the 2’s-complement
minuend is less than the 2’s-
complement subtrahend,
creating an answer which is less
than zero.
Branch is Minus
PC + 2 + rr
-> PC
if N=1
xxxxxx
Relative
BMI Srr
2B
4 2
Branch if Not Equal
to zero
PC + 2 + rr
PC
if Z = 1
xxxxxx
Relative
BNE Srr
26
4 2
Branch if overflow
Clear
PC + 2 + rr
* PC
if V=0
xxxxxx
Relative
BVC Srr
28
4 2
Branch if overflow
Set
PC + 2 + rr
+ PC
if V=1
xxxxxx
Relative
BVS Srr
29
4 2
Branch if PLus
PC + 2 + rr
•* PC
if N-0
xxxxxx
Relative
BPL Srr
2A
4 2
430 Microprocessor Instruction Set Tables
Mne- Operation
monic
Boolean/Arith.
Operation
Flags Address
HINZVC Mode
Assembler
Notation
Op
- #
Notes
JSR Jump SubRoutine PC + 2 -» PC
PC L S
PC H -S
SP - 2 -> SP
(ff+X) -> PC
PC + 3 -> PC
PCl + S
PCh-S
SP - 2 ^ SP
(aaaa) *♦ PC
Subroutine Instructions
ocx Indexed JSR $ff,X
Extended JSR $aaaa
AD 8 2
BD
9 3
The program counter is
incremented by 2 (Indexed) or
3 (Extended) and the program
counter is pushed onto the
stack 1 byte at a time. At the
memory location indicated by
the addressing mode will be
found the address of the first
instruction of the subroutine.
This address is placed in the
program counter.
RTS
ReTum from
Subroutine
BSR
Branch to
SubRoutine
S + PC„
S^PCl
SP + 2 -> SP
PC + 2 -> PC
PC^S
PCh + S
SP - 2 -» SP
PC + rr ** PC
Implied
RTS
xxxxxx Relative BSR $rr
39 5 1 The address of the next
instruction in the main program
after the last JSR is loaded
from the stack into the
program counter 1 byte at a
time.
8D 8 2 The program counter is
incremented by 2 and pushed
onto the stack 1 byte at a time.
The memory location of the
next instruction is then
calculate by adding the 2’s-
complement binary number rr
to the program counter. This
instruction differs from JSR in
the form of addressing it uses.
Stack Instructions
LDS
LoaD Stack pointer
M -* SP H
xxNZOx
Immediate
LDS #$dddd
8E
3
3
(M + 1) -» SP L
Direct
LDS $aa
9E
4
2
Indexed
LDS $ff,X
AE
6
2
Extended
LDS $aaaa
BE
5
3
STS
STore Stack pointer
SP H -> M
xxNZOx
Direct
STS Saa
9F
5
2
SP L -> (M + 1)
Indexed
STS $ff,X
AF
7
2
Extended
STS $aaaa
BF
6
3
PSHA
PuSH accumulator A
onto the stack
A •* S
SP - 1 -* SP
xxxxxx
Implied
PSHA
36
4
1
Whenever A or B is pushed
onto the stack the stack pointer
PSHB
PuSH accumulator B
onto the stack
B -> S
SP - 1 -* SP
xxxxxx
Implied
PSHB
37
4
1
is decremented by 1. When the
contents of the stack are placed
in A or B the stack pointer is
PULA
PUIL accumulator A
from the stack
S ■* A
SP + 1 -» SP
xxxxxx
Implied
PULA
32
4
1
incremented by 1.
PULB
PUIL accumulator B
from the stack
S -> B
SP + 1 -» SP
xxxxxx
Implied
PULB
33
4
1
Microprocessor Instruction Set Tables 431
EXPANDED TABLE OF 6800 INSTRUCTIONS LISTED BY CATEGORY (Continued)
Mne¬
monic
DBS
INS
TXS
TSX
RTI
SWI
none
Operation Boolean/Arith. Flags Address Assembler Op ~ # Notes
Operation HINZVC Mode Notation
DEcrement Stack
pointer
SP - 1 -» SP
xxxxxx Implied
DES
34
4 1
INcrement Stack
pointer
SP + 1 -> SP
xxxxxx Implied
INS
31
4 1
Transfer X (index)
register to Stack
pointer
X - 1 + SP
xxxxxx Implied
TXS
35
4 1
Transfer Stack
pointer to the X
(index) register
SP + 1 -> X
xxxxxx Implied
TSX
30
4 1
Interrupt Instructions
ReTum from
Interrupt
S + CCR
S 4 B
S -> A
s + x H
s->x L
S-> PC H
S *♦ PCl
HINZVC Implied
RTI
3B
10 1
Software Interrupt
PC + 1 + PC
PC L *+ s
PC^-S
x L ■* s
x H -s
A * S
B + S
CCR *♦ S
xlxxxx Implied
SWI
3F
12 1
After the actions shown in the
"Boolean/Arithmetic
Operation" column take place,
the microprocessor will begin to
execute a program whose
address is found in memory
locations FFFA and FFFB.
Input-Output Instructions
The 6800/6808 has no special
input and output instructions
but rather memory-maps these
operations.
432 Microprocessor Instruction Set Tables
Notes
Addressing Modes
Immediate
Direct
Indexed
Extended
Implied
Relative
Assembler Notation
Mnemonic #$dd
Mnemonic $aa
Mnemonic $ff,X
Mnemonic $aaaa
Mnemonic
Mnemonic $rr
Abbreviations and Explanations
a = address (one hex digit)
d = data (one hex digit)
f = offset (one hex digit) to be added to the X register (ff is
positive - $00-$ff which is decimal 0-255)
r = relative displacement (one hex digit) to be added to the
program counter (rr is 2 , s-complement number and thus
can be positive or negative, -128 to +127)
$ = indicates a hexadecimal number
# = indicates the data follows immediately after the instruction
L = low byte (lower byte of a two byte number)
H = high byte (upper byte of a two byte number)
Flags
H = instruction affects the half carry-flag
I = instruction affects the interrupt flag
N = instruction affects the negative flag
Z = instruction affects the zero flag
V = instruction affects the overflow flag
C = instruction affects the carry flag
0 = instruction always clears affected flag
1 = instruction always sets affected flag
x = flag not affected by instruction
CCR = condition code register (flags)
S = stack
SP = stack pointer
PC = program counter
0 = contents of the memory location in the parenthesis
M 7 ,..M 0 = memory bits 0-7 of a particular memory location
A 7 ..j\q = bits 0-7 of accumulator a
B r ..B 0 - bits 0-7 of accumulator b
X = Index register
0 = One zero bit.
00 = One zero byte.
Symbols in the Page Heading
~ = clock cycles
# ” # °f b yt e s used by instruction (and following address or data
if used)
Addressing Modes - Summary
Immediate (Mnemonic #$dd): In this addressing mode, the operand
(data or number that something is being done to) is contained in the
memory location(s) immediately following the instruction.
Direct (Mnemonic $aa): Direct addressing places the address of the
operand in the byte following the instruction.
Indexed (Mnemonic $ff,X): This mode involves a couple of steps.
First, the number ff (which is the byte after the instruction) is added
to the value in the X register. The number ff is an 8-bit number
which can only be positive (0-255 decimal). Then the operand is
fetched from this newly formed address.
Extended (Mnemonic $aaaa): Extended addressing is the same as
Direct except that a wider range is possible. The first byte is the
instruction as in Direct addressing. The second and third bytes then
form a 16-bit address where the operand can be found.
Implied (Mnemonic): When the operand is within the
microprocessor itself implied addressing is used. In these cases the
location of the operand is contained within the instruction itself.
CLRA (CLeaR accumulator A) is an example of implied addressing.
Relative (Mnemonic $rr): Relative addressing is used exclusively
with the branch and jump instructions. The byte following the
instruction is an 8-bit 2’s-complement number ( + 127 to -128) which
is added to the contents of the program counter. This then is the
address of the next instruction. The location of the next instruction
is being indicated relative to the current location in memoiy (the
current contents of the program counter).
Microprocessor Instruction Set Tables 433
SHORT TABLE OF 6800 INSTRUCTIONS LISTED ALPHABETICALLY
Mne¬
monic
Operation
Assembler
Notation
Op
Mne¬
monic
Operation
Assembler
Notation
Op
ABA
Add accumulator B
ABA
IB
BCS
Branch if Carry
BCS Srr
25
to accumulator A
Set
ADCA
AdD with Carry
ADCA #$dd
89
BEQ
Branch if result of
BEQ Srr
27
accumulator A to
ADCA $aa
99
last operation was
memory location
ADCA $ff,X
A9
EQual to zero
ADCA Saaaa
B9
BGE
Branch if Greater
BGE Srr
2C
ADCB
AdD with Carry
ADCB #$dd
C9
than or Equal to
accumulator B to
ADCB Saa
D9
zero
memory location
ADCB $ff,X
E9
ADCB $aaaa
F9
BGT
Branch if Greater
BGT Srr
2E
Than zero
ADDA
ADD accumulator A
ADDA #$dd
8B
to memory location
ADDA Saa
9B
BHI
Branch if Higher
BHI Srr
22
ADDA $ff,X
AB
ADDA Saaaa
BB
BITA
BIT test
BITA #$dd
85
accumulator A
BITA Saa
95
ADDB
ADD accumulator B
ADDB #Sdd
CB
BITA $ff,X
A5
to memory location
ADDB $aa
DB
BITA Saaaa
B5
ADDB $ff,X
EB
ADDB Saaaa
FB
BITB
BIT test
BITB #$dd
C5
accumulator B
BITB Saa
D5
ANDA
AND accumulator A
ANDA #$dd
84
BITB $ff,X
E5
with memory loc¬
ANDA Saa
94
BITB Saaaa
F5
ation
ANDA $ff,X
A4
ANDA Saaaa
B4
BLE
Branch if Less
BLE Srr
2F
then or Equal to
ANDB
AND accumulator B
ANDB #$dd
C4
zero
with memory loc¬
ANDB Saa
D4
ation
ANDB $ff,X
E4
BLS
Branch if Lower
BLS Srr
23
ANDB Saaaa
F4
or the Same
ASL
Arithmetic Shift
ASL $ff,X
68
BLT
Branch if Less
BLT Srr
2D
Left memory
ASL Saaaa
78
Than zero
location
BMI
Branch is Minus
BMI Srr
2B
ASLA
Arithmetic Shift
ASLA
48
Left accumulator A
BNE
Branch if Not Equal
BNE Srr
26
to zero
ASLB
Arithmetic Shift
ASLB
58
Left accumulator B
BPL
Branch if PLus
BPL Srr
2A
ASR
Arithmetic Shift
ASR $ff,X
67
BRA
BRanch Always
BRA Srr
20
Right memory loc¬
ASR Saaaa
77
to memory loc¬
ation
ation
ASRA
Arithmetic Shift
ASRA
47
BSR
Branch to
BSR Srr
8D
Right accumulator A
SubRoutine
ASRB
Arithmetic Shift
ASRB
57
BVC
Branch if oVerflow
BVC Srr
28
Right accumulator B
Clear
BCC
Branch if Carry
BCC Srr
24
BVS
Branch if oVerflow
BVS Srr
29
Clear
Set
434 Microprocessor Instruction Set Tables
Mne¬
Operation
Assembler
Op
monic
Notation
CBA
Compare accum¬
ulator B to
CBA
11
accumulator A
CLC
CLear Carry flag
CLC
oc
CLI
CLear Interrupt flag
CLI
OE
CLR
CLeaR memory
CLR $ff,X
6F
location
CLR $aaaa
7F
CLRA
CLeaR accumulator A
CLRA
4F
CLRB
CLeaR accumulator B
CLRB
5F
CLV
CLear overflow flag
CLV
OA
CMPA
CoMPare memory
CMPA #$dd
81
location to
CMPA $aa
91
accumulator A
CMPA $ff,X
A1
CMPA $aaaa
B1
CMPB
CoMPare memory
CMPB #$dd
Cl
location to
CMPB $aa
D1
accumulator B
CMPB $ff,X
El
CMPB $aaaa
FI
COM
COMplement memory
COM $ff,X
63
location (l’s com¬
plement)
COM $aaaa
73
COMA
COMplement ac¬
cumulator A
(l’s complement)
COMA
43
COMB
COMplement ac¬
cumulator B
(l’s complement)
COMB
53
CPX
ComPare memory
CPX #$dd
8C
location to X
CPX $aa
9C
(index) register
CPX $ff,X
AC
CPX $aaaa
BC
DAA
Decimal Adjust
accumulator A
DAA
19
DEC
DECrement memory
DEC $ff,X
6A
location
DEC $aaaa
7A
DECA
DECrement accum¬
ulator A
DECA
4A
DECB
DECrement accum¬
ulator B
DECB
5A
DES
DEcrement Stack
pointer
DES
34
Mne¬
Operation
Assembler
Op
monic
Notation
DEX
DEcrement X
(index) register
DEX
09
EORA
Exclusively OR
EORA #$dd
88
accumulator A
EORA $aa
98
with memory
EORA $ff,X
A8
location
EORA Saaaa
B8
EORB
Exclusively OR
EORB #$dd
C8
accumulator A
EORB $aa
D8
with memory
EORB Sff,X
E8
location
EORB Saaaa
F8
INC
INCrement memory
INC $ff,X
6C
location
INC Saaaa
7C
INCA
INCrement accum¬
ulator A
INCA
4C
INCB
INCrement accum¬
ulator B
INCB
5C
INS
INcrement Stack
pointer
INS
31
INX
INcrement X
(index) register
INX
08
JMP
JuMP to memory
JMP $ff,X
6E
location
JMP Saaaa
7E
JSR
Jump SubRoutine
JSR $ff,X
AD
JSR Saaaa
BD
LDAA
LoaD Accumulator A
LDAA #$dd
86
LDAA Saa
96
LDAA $ff,X
A6
LDAA Saaaa
B6
LDAB
LoaD Accumulator B
LDAB #Sdd
C6
LDAB Saa
D6
LDAB $ff,X
E6
LDAB Saaaa
F6
LDS
LoaD Stack pointer
LDS #$dddd
8E
LDS Saa
9E
LDS $ff t X
AE
LDS Saaaa
BE
LDX
LoaD X register
LDX #$dd
CE
LDX Saa
DE
LDX $ff,X
EE
LDX Saaaa
FE
LSR
Logical Shift Right
LSR $ff,X
64
memory location
LSR Saaaa
74
Microprocessor Instruction Set Tables 435
SHORT TABLE OF 6800 INSTRUCTIONS LISTED ALPHABETICALLY ( Continued)
Mne¬
Operation
Assembler
Op
Mne¬
Operation
Assembler
Op
monic
Notation
monic
Notation
LSRA
Logical Shift Right
LSRA
44
RORB
ROtate to the Right
RORB
56
accumulator A
accumulator B
LSRB
Logical Shift Right
LSRB
54
RTI
ReTum from
RTI
3B
accumulator B
Interrupt
NEG
NEGate memory loc¬
NEG $ff,X
60
RTS
ReTum from
RTS
39
ation (2’s comple¬
NEG $aaaa
70
Subroutine
ment)
SBA
Subtract accumulator
SBA
10
NEGA
NEGate accumu¬
lator A (2’s com¬
NEGA
40
B from accumulator A
plement)
SBCA
SuBtract with
SBCA #$dd
82
Carry memory
SBCA Saa
92
NEGB
NEGate accumu¬
NEGB
50
location from
SBCA $ff,X
A2
lator B (2’s com¬
plement)
accumulator A
SBCA Saaaa
B2
SBCB
SuBtract with
SBCB #$dd
C2
NOP
No OPeration
NOP
01
Carry memory
SBCB Saa
D2
location from
SBCB $ff,X
E2
ORAA
OR Accumulator A
ORAA #$dd
8A
accumulator B
SBCB Saaaa
F2
with memory loc¬
ORAA $aa
9A
ation
ORAA $ff,X
AA
SEC
SEt Carry flag
SEC
0D
ORAA Saaaa
BA
SEI
SEt Interrupt flag
SEI
OF
ORAB
OR Accumulator B
ORAB #$dd
CA
with memory loc¬
ORAB $aa
DA
SEV
SEt oVerflow flag
SEV
OB
ation
ORAB $ff,X
EA
ORAB $aaaa
FA
STAA
STore Accumulator A
STAA Saa
97
STAA Sff,X
A7
PSHA
PuSH accumulator A
PSHA
36
STAA Saaaa
B7
onto the stack
STAB
STore Accumulator B
STAB Saa
D7
PSHB
PuSH accumulator B
PSHB
37
STAB $ff,X
E7
onto the stack
STAB Saaaa
F7
PULA
PU1L accumulator A
PULA
32
STS
STore Stack pointer
STS Saa
9F
from the stack
STS $ff,X
AF
STS Saaaa
BF
PULB
PU1L accumulator B
from the stack
PULB
33
STX
STore X register
STX Saa
DF
STX $ff,X
EF
ROL
ROtate memory loc¬
ROL $ff,X
69
STX Saaaa
FF
ation Left
ROL Saaaa
79
SUBA
SUBtract memory
SUBA #$dd
80
ROLA
ROtate to the Left
ROLA
49
location from
SUBA Saa
90
accumulator A
accumulator A
SUBA $ff,X
A0
SUBA Saaaa
B0
ROLB
ROtate to the Left
accumulator B
ROLB
59
SUBB
SUBtract memory
SUBB #$dd
CO
location from
SUBB Saa
DO
ROR
ROtate memory loc¬
ROR $ff,X
66
accumulator B
SUBB $ff,X
E0
ation Right
ROR Saaaa
76
SUBB Saaaa
F0
RORA
ROtate to the Right
accumulator A
RORA
46
SWI
Software Interrupt
SWI
3F
436
Microprocessor Instruction Set Tables
Mne- Operation
monic
Assembler Op
Notation
Mne- Operation
monic
Assembler Op
Notation
TAB
Transfer A to B
TAB
16
TSTA
TEsT accumulator A
TSTA
4D
TAP
Transfer Accumulator
TAP
06
for zero or minus
A to Processor con¬
dition code register
TSTB
TEsT accumulator B
for zero or minus
TSTB
5D
TBA
Transfer B to A
TBA
17
TSX
Transfer Stack
TSX
30
TPA
Transfer Processor
condition code reg¬
TPA
07
pointer to the X
(index) register
ister to accumulator
TXS
Transfer X (index)
TXS
35
A
register to Stack
TST
TEsT memory loc¬
TST $ff,X
6D
pointer
ation for zero or
TST Saaaa
7D
WAI
WAit for
WAI
3E
Interrupt
SHORT TABLE OF 6800 INSTRUCTIONS LISTED BY CATEGORY
Assembler Op Booiean/Arith Flags
Notation _Operation HINZVC
CPU Control Instructions
NOP
01
nothing
xxxxxx
WAI
3E
PC + 1 -» PC
PCl -* S
PCh-S
x L + s
x H ■* s
A -» S
B ■» S
CCR -* S
xlxxxx
Data Transfer Instructions
LDAA #$dd
LDAA $aa
LDAA $ff,X
LDAA Saaaa
86 M -> A
96
A6
B6
xxNZOx
LDAB #$dd
LDAB $aa
LDAB $ff,X
LDAB Saaaa
C6 M -> B
D6
E6
F6
xxNZOx
STAA $aa
STAA $ff,X
STAA Saaaa
97 A *♦ M
A7
B7
xxNZOx
STAB $aa
STAB $ff,X
STAB Saaaa
D7 B -► M
E7
F7
xxNZOx
Assembler
Notation
Op
Booiean/Arith
Operation
Flags
HINZVC
TAB
16
A->B
xxNZOx
TBA
17
B *+ A
xxNZOx
LDX #$dddd
CE
M -> x H
xxNZOx
LDX Saa
DE
(M + 1) -> X L
LDX $ff,X
EE
LDX Saaaa
FE
STX Saa
DF
X H ** M
xxNZOx
STX $ff,X
EF
X L -> (M + 1)
STX Saaaa
FF
CLR $ff,X
6F
00 -> M
xxOlOO
CLR Saaaa
7F
CLRA
4F
00 -» A
xxOlOO
CLRB
5F
00 *♦ B
xxOlOO
Flag Instructions
CLC
oc
0->C
xxxxxO
LI
0E
0 -> I
xOxxxx
CLV
0A
0 4 V
xxxxVx
SEC
0D
1 *» c
xxxxxl
SEI
OF
1 -> I
xlxxxx
Microprocessor Instruction Set Tables 437
SHORT TABLE OF 6800 INSTRUCTIONS LISTED BY CATEGORY ( Continued)
Assembler
Notation
Op
Boolean/Arith
Operation
Flags
HINZVC
SEV
OB
1 -> V
xxxxlx
TAP
06
A 4 CCR
HINZVC
TPA
07
CCR -» A
xxxxxx
Arithmetic Instructions
ADDA #$dd
8B
A + M -> A
HxNZVC
ADDA Saa
9B
ADDA $ff,X
AB
ADDA $aaaa
BB
ADDB #$dd
CB
B + M 4 B
HxNZVC
ADDB $aa
DB
ADDB $ff,X
EB
ADDB Saaaa
FB
ABA
IB
A + B 4 A
HxNZVC
ADCA #$dd
89
A + M + C + A
HxNZVC
ADCA $aa
99
ADCA $ff,X
A9
ADCA Saaaa
B9
ADCB #Sdd
C9
B + M + C-> B
HxNZVC
ADCB $aa
D9
ADCB $ff,X
E9
ADCB Saaaa
F9
SUBA #$dd
80
A - M •+ A
xxNZVC
SUBA Saa
90
SUBA $ff,X
A0
SUBA Saaaa
B0
SUBB #$dd
CO
B - M -► B
xxNZVC
SUBB Saa
DO
SUBB $ff,X
E0
SUBB Saaaa
F0
SBA
10
A - B -> A
xxNZVC
SBCA #$dd
82
A - M - C -> A
xxNZVC
SBCA Saa
92
SBCA $ff,X
A2
SBCA Saaaa
B2
SBCB #$dd
C2
B - M - C B
xxNZVC
SBCB Saa
D2
SBCB $ff,X
E2
SBCB Saaaa
F2
Assembler
Notation
Op
Boolean/Arith
Operation
Flags
HINZVC
DAA
19
(converts bin¬
ary add. of BCD
characters into
BCD format)
xxNZVC
Logical Instructions
ANDA #$dd
84
A AND M A
xxNZOx
ANDA Saa
94
ANDA $ff,X
A4
ANDA Saaaa
B4
ANDB #$dd
C4
B AND M -► B
xxNZOx
ANDB Saa
D4
ANDB $ff,X
E4
ANDB Saaaa
F4
ORAA #$dd
8A
A OR M -> A
xxNZOx
ORAA Saa
9A
ORAA Sff,X
AA
ORAA Saaaa
BA
ORAB #$dd
CA
B OR M 4 B
xxNZOx
ORAB Saa
DA
ORAB $ff,X
EA
ORAB Saaaa
FA
EORA #$dd
88
A EOR M -> A
xxNZOx
EORA $aa
98
EORA $ff,X
A8
EORA Saaaa
B8
EORB #$dd
C8
B EOR M + B
xxNZOx
EORB Saa
D8
EORB Sff.X
E8
EORB Saaaa
F8
BITA #$dd
85
A AND M
xxNZOx
BITA Saa
95
BITA $ff,X
A5
BITA Saaaa
B5
BITB #Sdd
C5
B AND M
xxNZOx
BITB Saa
D5
BITB $ff,X
E5
BITB Saaaa
F5
COM $ff,X
63
M -> M
xxNZOl
COM Saaaa
73
COMA
43
A -> A
xxNZOl
COMB
53
B * B
xxNZOl
438 Microprocessor Instruction Set Tables
Assembler
Notation
Op
Boolean/Arith
Operation
Flags
HINZVC
NEG $ff,X
60
00 - M -» M
xxNZVC
NEG $aaaa
70
NEGA
40
00 - A ■» A
xxNZVC
NEGB
50
00 - B -» B
xxNZVC
Rotate and Shift Instructions
ROL $ff,X
69
|—M 7 ... Mo
1 xxNZVC
ROL $aaaa
79
1 .c_
I
ROLA
49
1— A 7 ... A 0
‘-i-C-
j xxNZVC
ROLB
59
1— B 7 ... B 0
| xxNZVC
ROR $ff,X
66
(-► M 7 ... Mq —I
ROR Saaaa
76
LI c , 1
| xxNZVC
RORA
46
a 7 ... a 0 —|
xxNZVC
1-c-^—1
RORB
56
!-► B 7 ... B 0 —I
xxNZVC
*- c +-—1
ASL $ff,X
68
C^M 7 ...Mo^0
1 xxNZVC
ASL Saaaa
78
ASLA
48
C *+- A 7 ... A 0 o
i xxNZVC
ASLB
58
C-*-B 7 ... B o ^0
1 xxNZVC
ASR $ff,X
67
P^M 7 ... M 0 “^ C
xxNZVC
ASR Saaaa
77
u
ASRA
47
p>A 7 ... a 0 -»-c
: xxNZVC
ASRB
57
B 7 ... B 0 —»-C
xxNZVC
LSR $ff,X
64
0+ c
xxOZVC
LSR Saaaa
74
LSRA
44
0-* A C
xxOZVC
LSRB
54
0* Bj.-Bq-* c
xxOZVC
Increment and Decrement Instructions
INC $ff,X 6C M + 1 -> M xxNZVx
INC Saaaa 7C
Assembler
Notation
Op
Boolean/Arith
Operation
Flags
HINZVC
INCA
4C
A + 1 -* A
xxNZVx
INCB
5C
B + 1 -* B
xxNZVx
DEC $ff,X
6A
M - 1 -» M
xxNZVx
DEC Saaaa
7A
DECA
4A
A - 1 ■* A
xxNZVx
DECB
5A
B - 1 -> B
xxNZVx
INX
08
X + 1 X
xxxZxx
DEX
09
X - 1 -* X
xxxZxx
Unconditional Jump Instructions
JMP $ff,X
JMP Saaaa
6E
7E
X + ff -» PC
(indexed)
aaaa -> PC
(extended)
xxxxxx
BRA Srr
20
PC + 2
xxxxxx
+ rr -> PC
Test (Compare) Instructions
CM PA #$dd
81
A - M
xxNZVC
CMPA Saa
91
CMPA $ff,X
A1
CMPA Saaaa
B1
CMPB #$dd
Cl
B-M
xxNZVC
CMPB Saa
D1
CMPB $ff,X
El
CMPB Saaaa
FI
CBA
11
A - B
xxNZVC
CPX #$dddd
8C
x h -m
xxNZVx
CPX Saa
9C
X L - (M +1)
CPX Sff,X
AC
CPX Saaaa
BC
TST Sff,X
6D
M - 00
xxNZOO
TST Saaaa
7D
TSTA
4D
>
i
o
o
xxNZOO
TSTB
5D
B - 00
xxNZOO
Microprocessor Instruction Set Tables 439
SHORT TABLE OF 6800 INSTRUCTIONS LISTED BY CATEGORY ( Continued)
Assembler Op Boolean/Arith Flags Assembler Op Boolean/Arith
Notation Operation_HINZVC Notation _ °P eration
Conditional .lump (Branch) Instructions
BCC $rr 24 PC + 2 + rr xxxxxx
-> PC
If C=0
BPL $rr 2A PC + 2 + rr
-» PC
If N = 0
Subroutine Instructions
BCS Srr
25
PC + 2 + rr
xxxxxx
JSR $ff,X
AD
PC + 2 -* PC
-> PC
PCl ■* S
If C-l
PCh -s
SP - 2 -> SP
BEQ Srr
27
PC + 2 + rr
xxxxxx
(ff+X) ■» PC
-> PC
If Z=1
JSR Saaaa
BD
PC + 3 ■» PC
PCl ■* S
BGE $rr
2C
PC + 2 + rr
xxxxxx
PC„-S
-> PC
SP - 2 -» SP
If N EOR V = 0
(aaaa) ■» PC
BGTSrr
2E
PC + 2 + rr
xxxxxx
RTS
39
S -> PC H
-» PC
S -» PCl
If Z AND (N
SP + 2 -> SP
EOR V) = 0
BSR Srr
8D
PC + 2 PC
BHI Srr
22
PC + 2 + rr
xxxxxx
pc l + s
-> PC
PCh-S
If C AND Z - 0
SP - 2 -* SP
PC + rr -* PC
BLE Srr
2F
PC + 2 + rr
xxxxxx
* PC
If Z AND (N EOR
Stack Instructions
V) = 1
LDS #$dddd
8E
M -> SP H
BLS Srr
23
PC + 2 + rr
xxxxxx
LDS Saa
9E
(M + 1) -> SP L
-> PC
LDS $ff,X
AE
If C OR Z = 1
LDS Saaaa
BE
BLTSrr
2D
PC + 2 + rr
xxxxxx
STS Saa
9F
SP H ■» M
->PC
STS $ff,X
AF
SP L -> (M + 1)
If N EOR V = 1
STS Saaaa
BF
BMI Srr
2B
PC + 2 + rr
xxxxxx
PSHA
36
A -* S
->PC
SP - 1 -» SP
II
U-4
PSHB
37
B S
BNE Srr
26
PC + 2 + rr
xxxxxx
SP - 1 -> SP
-> PC
If Z=1
PULA
32
S ■» A
SP + 1 -> SP
BVC Srr
28
PC + 2 + rr
xxxxxx
^ PC
PULB
33
S -> B
o
ii
>
SP + 1 SP
BVS Srr
29
PC + 2 + rr
xxxxxx
DES
34
SP - 1 -> SP
PC
If V = 1
INS
31
SP + 1 -» SP
Flags
HINZVC
xxxxxx
xxxxxx
xxxxxx
xxxxxx
xxNZGx
xxNZGx
xxxxxx
xxxxxx
xxxxxx
xxxxxx
xxxxxx
xxxxxx
440 Microprocessor Instruction Set Tables
Assembler
Notation
Op Boolean/Arith Flags
_Operation HINZVC
Assembler Op Boolean/Arith Flags
Notation ___Operation HINZVC
TXS
35 X - 1 -► SP
XXXXXX
TSX
30 SP + 1 •* X
xxxxxx
IntemiDt Instructions
RTI
3B S -» CCR
S ■* B
S ■* A
s^x H
S + X L
s -»PC H
s-pq
HINZVC
3F PC + 1 -> PC xlxxxx
PC L ->S
PCh + S
x L ->s
x H ^s
A -* S
B->S
CCR -> S
Input-Output Instructions
none
CONDENSED TABLE OF 6800 INSTRUCTIONS LISTED BY CATEGORY
°P Assembler _Op Assembler _Op Assembler
CPU Control
Instructions
NOP
01
WAI
3E
Data Transfer
Instructions
LDAA #$dd
86
LDAA $aa
96
LDAA Sff.X
A6
LDAA Saaaa
B6
LDAB #$dd
C6
LDAB $aa
D6
LDAB Sff.X
E6
LDAB Saaaa
F6
STAA Saa
97
STAA Sff.X
A7
STAA Saaaa
B7
STAB Saa
D7
STAB $ff,X
E7
STAB Saaaa
F7
TAB
16
TBA
17
LDX #$dddd
CE
LDX Saa
DE
LDX Sff.X
EE
LDX Saaaa
FE
STX Saa
DF
STX $ff,X
EF
STX Saaaa
FF
CLR $ff,X
6F
CLR Saaaa
7F
CLRA
4F
CLRB
5F
Flag Instructions
CLC
OC
LI
0E
CLV
0A
SEC
0D
SEI
OF
SEV
OB
TAP
06
TPA
07
Arithmetic
Instructions
ADDA #$dd
8B
ADDA Saa
9B
ADDA $ff,X
AB
ADDA Saaaa
BB
ADDB #$dd
CB
ADDB Saa
DB
ADDB $ff,X
EB
ADDB Saaaa
FB
ABA
IB
ADCA #$dd
89
ADCA Saa
99
ADCA Sff.X
A9
ADCA Saaaa
B9
ADCB #$dd
C9
ADCB Saa
D9
ADCB Sff.X
E9
ADCB Saaaa
F9
SUBA #$dd
80
SUBA Saa
90
SUBA Sff.X
A0
SUBA Saaaa
B0
SUBB #$dd
CO
SUBB Saa
DO
SUBB $ff,X
E0
SUBB Saaaa
F0
SBA
10
SBCA #$dd
82
SBCA Saa
92
SBCA Sff.X
A2
SBCA Saaaa
B2
SBCB #$dd
C2
SBCB Saa
D2
SBCB Sff.X
E2
SBCB Saaaa
F2
DAA
19
Logical
Instructions
ANDA #Sdd
84
ANDA $aa
94
ANDA $ff,X
A4
ANDA Saaaa
B4
ANDB #$dd
C4
ANDB Saa
D4
ANDB Sff,X
E4
ANDB Saaaa
F4
ORAA #$dd
8A
ORAA Saa
9A
ORAA $ff,X
AA
ORAA Saaaa
BA
ORAB #$dd
CA
ORAB Saa
DA
ORAB $ff,X
EA
ORAB Saaaa
FA
EORA #$dd
88
EORA Saa
98
EORA $ff,X
A8
EORA Saaaa
B8
EORB #$dd
C8
EORB $aa
D8
EORB $ff,X
E8
EORB Saaaa
F8
Microprocessor Instruction Set Tables 441
Assembler
BITA #$dd
BITA Saa
BITA $ff,X
BITA Saaaa
BITB #$dd
BITB Saa
BITB $ff,X
BITB Saaaa
COM $ff,X
COM Saaaa
COMA
COMB
NEG $ff,X
NEG Saaaa
NEGA
NEGB
Rotate and i
Instructions
ROL $ff,X
ROL Saaaa
ROLA
ROLB
ROR $ff,X
ROR Saaaa
RORA
RORB
ASL $ff,X
ASL Saaaa
ASLA
ASLB
ASR $ff,X
ASR Saaaa
CONDENSED TABLE OF 6800 INSTRUCTIONS LISTED BY CATEGORY ( Continued )
Op
85
95
A5
B5
C5
D5
E5
F5
63
73
43
53
60
70
40
50
69
79
49
59
66
76
46
56
68
78
48
58
67
77
Assembler
Op
Assembler
Op
Assembler
Op
ASRA
47
CMPB #$dd
Cl
RTS
39
ASRB
57
CMPB Saa
D1
BSR Srr
8D
CMPB $ff,X
El
LSR $ff,X
64
CMPB Saaaa
FI
Stack
LSR Saaaa
74
CBA
11
Instructions
LSRA
44
CPX #$dddd
8C
LDS #$dddd
8E
LSRB
54
CPX Saa
9C
LDS Saa
9E
cpx $ff,x
AC
LDS Sff,X
AE
Increment and
CPX Saaaa
BC
LDS Saaaa
BE
Decrement
Instructions
TST Sff,X
6D
STS Saa
9F
TST Saaaa
7D
STS $ff,X
AF
INC $ff,X
6C
STS Saaaa
BF
INC Saaaa
1C
TSTA
4D
TSTB
5D
PSHA
36
INCA
4C
PSHB
37
INCB
5C
Conditional Jump
(Branch)
PULA
32
DEC $ff,X
6A
Instructions
PULB
33
DEC Saaaa
7A
BCC Srr
24
DES
34
DECA
4A
BCS Srr
25
INS
31
DECB
5A
BEQ Srr
27
BGE Srr
2C
TXS
35
INX
08
BGT Srr
2E
TSX
30
DEX
09
BHI Srr
22
BLE Srr
2F
Interrupt
Unconditional
BLS Srr
23
Instructions
Jump Instructions
BLTSrr
2D
BMI Srr
2B
RTI
3B
JMP $ff,X
6E
BNE Srr
26
SWI
3F
JMP Saaaa
7E
BVC Srr
28
BVS Srr
29
Input-Output
BRA Srr
20
BPL Srr
2A
Instructions
Test (Compare)
Subroutine
none
Instructions
Instructions
CMPA #$dd
81
JSR Sff.X
AD
CMPA Saa
91
JSR Saaaa
BD
CMPA $ff,X
A1
CMPA Saaaa
B1
442
Microprocessor Instruction Set Tables
CONDENSED TABLE OF 6800 INSTRUCTIONS LISTED ALPHABETICALLY
Assembler
Op
ABA
IB
ADCA $aa
99
ADCA Saaaa
B9
ADCA $ff,X
A9
ADCA #$dd
89
ADCB $aa
D9
ADCB Saaaa
F9
ADCB $ff,X
E9
ADCB #$dd
C9
ADDA $aa
9B
ADDA Saaaa
BB
ADDA $ff,X
AB
ADDA #$dd
8B
ADDB $aa
DB
ADDB Saaaa
FB
ADDB $ff,X
EB
ADDB #$dd
CB
ANDA $aa
94
ANDA Saaaa
B4
ANDA $ff,X
A4
ANDA #$dd
84
ANDB $aa
D4
ANDB Saaaa
F4
ANDB $ff,X
E4
ANDB #$dd
C4
ASL Saaaa
78
ASL $ff,X
68
ASLA
48
ASLB
58
ASR Saaaa
77
ASR $ff,X
67
ASRA
47
ASRB
57
BCC Srr
24
BCS Sir
25
BEQ Srr
27
BGE Srr
2C
BGT Srr
2E
BHI $rr
22
BITA Saa
95
BITA Saaaa
B5
BITA $ff,X
A5
BITA #$dd
85
BITB $aa
D5
BITB Saaaa
F5
BITB $ff,X
E5
BITB #$dd
C5
BLE Srr
2F
BLS Srr
23
BLTSrr
2D
Assembler
Op
BMI Srr
2B
BNE Srr
26
BPL Srr
2A
BRA Srr
20
BSR $rr
8D
BVC Srr
28
BVS Srr
29
CBA
11
CLC
OC
CLI
0E
CLR Saaaa
7F
CLR $ff,X
6F
CLRA
4F
CLRB
5F
CLV
0A
CMPA Saa
91
CMPA Saaaa
B1
CMPA $ff,X
A1
CMPA #$dd
81
CMPB Saa
D1
CMPB Saaaa
FI
CMPB $ff,X
El
CMPB #$dd
Cl
COM Saaaa
73
COM $ff,X
63
COMA
43
COMB
53
CPX Saa
9C
CPX Saaaa
BC
CPX Sff,X
AC
CPX #$dd
8C
DAA
19
DEC Saaaa
7A
DEC $ff,X
6A
DECA
4A
DECB
5A
DES
34
DEX
09
EORA $aa
98
EORA Saaaa
B8
EORA $ff,X
A8
EORA #$dd
88
EORB Saa
D8
EORB Saaaa
F8
EORB $ff,X
E8
EORB #$dd
C8
INC Saaaa
7C
INC $ff,X
6C
INCA
4C
INCB
5C
Assembler
Op
INS
31
INX
08
JMP Saaaa
7E
JMP $ff,X
6E
JSR Saaaa
BD
JSR $ff,X
AD
LDAA Saa
96
LDAA Saaaa
B6
LDAA $ff,X
A6
LDAA #$dd
86
LDAB Saa
D6
LDAB Saaaa
F6
LDAB $ff,X
E6
LDAB #$dd
C6
LDS $aa
9E
LDS Saaaa
BE
LDS $ff,X
AE
LDS #Sdddd
8E
LDX Saa
DE
LDX Saaaa
FE
LDX $ff,X
EE
LDX #$dd
CE
LSR Saaaa
74
LSR $ff,X
64
LSRA
44
LSRB
54
NEG Saaaa
70
NEG Sff,X
60
NEGA
40
NEGB
50
NOP
01
ORAA Saa
9A
ORAA Saaaa
BA
ORAA $ff,X
AA
ORAA #$dd
8A
ORAB Saa
DA
ORAB Saaaa
FA
ORAB $ff,X
EA
ORAB #Sdd
CA
PSIIA
36
PSHB
37
PULA
32
PULB
33
ROL Saaaa
79
ROL Sff,X
69
ROLA
49
ROLB
59
ROR Saaaa
76
ROR $ff,X
66
RORA
46
Assembler
Op
RORB
56
RTI
3B
RTS
39
SBA
10
SBCA Saa
92
SBCA Saaaa
B2
SBCA Sff,X
A2
SBCA #Sdd
82
SBCB Saa
D2
SBCB Saaaa
F2
SBCB $ff,X
E2
SBCB #$dd
C2
SEC
0D
SEI
OF
SEV
0B
STAA Saa
97
STAA Saaaa
B7
STAA $ff,X
A7
STAB Saa
D7
STAB Saaaa
F7
STAB $ff,X
E7
STS Saa
9F
STS Saaaa
BF
STS Sff,X
AF
STX Saa
DF
STX Saaaa
FF
STX $ff,X
EF
SUBA Saa
90
SUBA Saaaa
B0
SUBA $ff,X
A0
SUBA #$dd
80
SUBB Saa
DO
SUBB Saaaa
FO
SUBB $ff,X
E0
SUBB #$dd
CO
SWI
3F
TAB
16
TAP
06
TBA
17
TPA
07
TST Saaaa
7D
TST $ff,X
6D
TSTA
4D
TSTB
5D
TSX
30
TXS
35
WAI
3E
Microprocessor Instruction Set Tables 443
CONDENSED TABLE OF 6800 INSTRUCTIONS LISTED BY OP CODE
Op
Assembler
Op
Assembler
01
NOP
49
ROLA
06
TAP
4A
DECA
07
TPA
4C
INCA
08
INX
4D
TSTA
09
DEX
4F
CLRA
0A
CLV
50
NEGB
OB
SEV
53
COMB
OC
CLC
54
LSRB
0D
SEC
56
RORB
0E
CLI
57
ASRB
OF
SEI
58
ASLB
10
SBA
59
ROLB
11
CBA
5A
DECB
16
TAB
5C
INCB
17
TBA
5D
TSTB
19
DAA
5F
CLRB
IB
ABA
60
NEG $ff,X
20
BRA $rr
63
COM $ff,X
22
BHI Srr
64
LSR $ff,X
23
BLS $rr
66
ROR $ff,X
24
BCC $rr
67
ASR $ff,X
25
BCS Srr
68
ASL $ff,X
26
BNE Srr
69
ROL $ff,X
27
BEQ Sit
6A
DEC $ff,X
28
BVC Srr
6C
INC $ff,X
29
BVS Srr
6D
TST $ff,X
2A
BPL Srr
6E
JMP $ff,X
2B
BMI Srr
6F
CLR $ff,X
2C
BGE Srr
70
NEG Saaaa
2D
BLT Srr
73
COM Saaaa
2E
BGT Srr
74
LSR Saaaa
2F
BLE Srr
76
ROR Saaaa
30
TSX
77
ASR Saaaa
31
INS
78
ASL Saaaa
32
PULA
79
ROL Saaaa
33
PULB
7A
DEC Saaaa
34
DES
7C
INC Saaaa
35
TXS
7D
TST Saaaa
36
PSHA
7E
JMP Saaaa
37
PSHB
7F
CLR Saaaa
39
RTS
80
SUBA #$dd
3B
RTI
81
CMPA #$dd
3E
WAI
82
SBCA #$dd
3F
SWI
84
ANDA #Sdd
40
NEGA
85
BITA #$dd
43
COMA
86
LDAA #Sdd
44
LSRA
88
EORA #$dd
46
RORA
89
ADCA #$dd
47
ASRA
8A
ORAA #$dd
48
ASLA
8B
ADDA #$dd
Op
Assembler
Op
Assembler
8C
CPX #Sdd
C4
ANDB #$dd
8D
BSR Srr
C5
BITB #$dd
8E
LDS #$dddd
C6
LDAB #$dd
90
SUBA $aa
C8
EORB #$dd
91
CMPA $aa
C9
ADCB #$dd
92
SBCA Saa
CA
ORAB #Sdd
94
ANDA $aa
CB
ADDB #$dd
95
BETA Saa
CE
LDX #$dd
96
LDAA Saa
DO
SUBB Saa
97
STAA Saa
D1
CMPB Saa
98
EORA Saa
D2
SBCB Saa
99
ADCA Saa
D4
ANDB Saa
9A
ORAA Saa
D5
BITB Saa
9B
ADDA Saa
D6
LDAB Saa
9C
CPX Saa
D7
STAB $aa
9E
LDS Saa
D8
EORB Saa
9F
STS $aa
D9
ADCB Saa
A0
SUBA $ff,X
DA
ORAB $aa
A1
CMPA $ff,X
DB
ADDB Saa
A2
SBCA Sff,X
DE
LDX Saa
A4
ANDA $ff,X
DF
STX Saa
AS
BITA $ff,X
E0
SUBB $ff,X
A6
LDAA $ff,X
El
CMPB $ff,X
A7
STAA $ff,X
E2
SBCB Sff,X
A8
EORA $ff,X
E4
ANDB $ff,X
A9
ADCA $ff,X
E5
BITB $ff,X
AA
ORAA $ff,X
E6
LDAB $ff,X
AB
ADDA $ff,X
E7
STAB $ff,X
AC
CPX $ff,X
E8
EORB $ff,X
AD
JSR $ff,X
E9
ADCB Sff,X
AE
LDS $ff,X
EA
ORAB $ff,X
AF
STS $ff,X
EB
ADDB $ff,X
B0
SUBA Saaaa
EE
LDX $ff,X
B1
CMPA Saaaa
EF
STX $ff,X
B2
SBCA Saaaa
F0
SUBB Saaaa
B4
ANDA Saaaa
FI
CMPB Saaaa
B5
BITA Saaaa
F2
SBCB Saaaa
B6
LDAA Saaaa
F4
ANDB Saaaa
B7
STAA Saaaa
F5
BITB Saaaa
B8
EORA Saaaa
F6
LDAB Saaaa
B9
ADCA Saaaa
F7
STAB Saaaa
BA
ORAA Saaaa
F8
EORB Saaaa
BB
ADDA Saaaa
F9
ADCB Saaaa
BC
CPX Saaaa
FA
ORAB Saaaa
BD
JSR Saaaa
FB
ADDB Saaaa
BE
LDS Saaaa
FE
LDX Saaaa
BF
STS Saaaa
FF
STX Saaaa
CO
SUBB #$dd
Cl
CMPB #$dd
C2
SBCB #$dd
444 Microprocessor Instruction Set Tables
EXPANDED TABLE OF 8086/8088 INSTRUCTIONS LISTED BY CATEGORY
CPU Cont rol Instructions
^ ESCape
The ESC instruction allows the 8086/8088 to pass instructions to the 8087 math
coprocessor. The instructions for the coprocessor appear as a 6-bit code embedded
m the escape instruction. The 8086/8088 performs a NOP while the 8087 executes
the mstruction. IFlags affected - none]
HLT HaLT
The HLT instruction causes the 8086/8088 to stop fetching and executing
instructions and enter a halt state. To exit from the halt state the microprocessor
must receive a hardware reset or interrupt signal, fFlags affegted . nnn „j
L0CK LOCK
LOCK is a prefix which can be used in front of 8086/8088 instructions. It prevents
any other processors from gaining access to the systems buses during the following
instruction. [Flags affected - none] 6
N( “ ) P No OPeration
The NOP instruction simply uses up three clock cycles during which nothing is done
and no flags are affected. It is useful 1) in programs requiring time delays, and 2)
as a means to hold space open in programs so instructions can be added at a later
date. [Hags affected - none]
WAIT WAIT
The WAIT instruction causes the 8086/8088 to enter a wait state or idle condition
during which no further processing occurs (except valid interrupts) until a signal is
received on the TEST pin. fFlags afferieH - nnn.|
Data T ransfer Instructions
Load AH from Flag
The LAHF instruction copies the low-order byte of the flag (status) register to AH.
The flags themselves are not affected. The low order byte of the 8086/8088 status
register is the same as that of the 8085. This instruction is used primarily to
translate 8085 software into 8086/8088 software. fFlags afferieH - nnn P ]
Load Data Segment
The LDS mstruction performs two distinct operations. First it loads two
consecutive bytes of memory into one of the 16-bit general, index, or pointer
registers. Then it loads the next two consecutive bytes of memory into the 16-bit
DS register.
For example, if DI = 1000 then:
LDS BX,[DI]
copies the contents of memory locations 1000 and 1001 of the data segment
into register BX and the contents of memory locations 1002 and 1003 of the
data segment into register DS.
[Flags affected - none]
Microprocessor Instruction Set Tables 445
EXPANDED TABLE OF 8086/8088 INSTRUCTIONS LISTED BY CATEGORY ( Continued )
LEA
LES
MOV
SAHF
XCHG
XLAT
Flag Instructions
CLC
Load Effective Address
The LEA instruction loads one of the 16-bit general, index, or pointer registers
from another register or memory.
Example:
LEA CX,[SI]
copies the number (address) in the SI register to the CX register.
[Flags affected - none!
Load Extra Segment
The LES instruction performs two distinct operations. First it loads two consecutive
bytes of memory into one of the 16-bit general, index, or pointer registers. Then
it loads the next two consecutive bytes of memory into the 16-bit ES register.
For example, if DI = 1000 then:
LES BX,[DI]
copies the contents of memory locations 1000 and 1001 of the data segment
into register BX and the contents of memory locations 1002 and 1003 of the
data segment into register ES. [Flags affected - nonel
MOVe
The MOV instruction copies the contents of a register, memory location, or
immediate number to a register or memory location. The source and destination
must both be of the same length and both cannot be memory locations. [Flags
affected - none!
Store AH in Flags
The SAHF instruction copies AH to the low-order byte of the flag (status) register.
The low-order byte of the 8086/8088 status register is the same as that of the 8085.
This instruction is used primarily to translate 8085 software into 8086/8088 software.
After this instruction is executed SF, ZF, AF, PF, and CF will correspond to bits
7, 6, 4, 2, and 1 of AH respectively. [Flags affected - SF. ZF, AF, P F, CF1
eXCHanGe
The XCHG instruction exchanges the contents of two registers or a register and a
memory location. Segment registers cannot be used nor can two memory locations.
The source and destination must be of the same length. [Flags affected - none]
trans(X)LATe
The XLAT instruction is used to look up values in a table. First the location of the
beginning of the table must be loaded into the BX register. Then the relative
location within the table of the desired value must be placed in the AL register.
When the XLAT instruction is executed the value of BX is added to AL to form
an address. The contents of that address then replaces the former value in AL.
This instruction can be used to translate ASCII values into EBCDIC values for
example. [Flags affected - nonel
CLear Carry flag
The CLC instruction places a zero (0) in the carry flag bit of the status register.
[Flags affected - CF = 01
446 Microprocessor Instruction Set Tables
CLD
CLI
CMC
STC
STD
STI
CLear Direction flag (auto-increment)
Wh™ th D P ' a “ s a 2cro <°> th = direction Hag bit of the status register.
When thus nag is cleared (0), SI and DI will automatically increment when certain
string instructions are executed. fFlags affected - DF=n]
CLear Interrupt-enable flag
Ssto 1 irr n laC “ " lhe ' nterru Pt'enabie flag bit of the status
pb -^ on ihe nmi p “ - « s
CoMplement Carry flag
0 h h 2? h “i""? “ ver,s 0>8 “■ of Ike status register. If the CF is
(.Ip, ° c “ scd 10 a L If * ts a f. t mil be changed to 0. IFlans affect.H .
SeT Carry flag
j^TC^uctaplaces a one (1) in the cnry flag bi, of the status register.
SeT Direction flag (auto-decrement)
Whefoc , " st ™ ctlon Pjaees a one (1) in the direction n ag bit of the status register.
When this nag is set (!) SI and DI will automatically decrement when ce,tainting
instructions are executed. fFlags affected - DF=i] ®
SeT Interrupt enable flag
register^ CilT ‘ °”'™ “ lhe “'-“Pt-aabl. Hag bit of the status
register. When this flag is set (1) the 8086/8088 will respond to interrupt signals
on the INTR pin. fFl ags affected . rr-i] P Upt SlgnalS
Arithmetic Instructions
ASCII Adjust for Addition
The AAA instruction can be used after addition to adjust or alter the number in
AL to what it would be if the last two operands were ASCII numbers. AH will be
cleared. fFlags effected - AF. CF. O F (undefined!. SF (undefined! 7F
(undefined!. PF ('undefined')]
ASCII Adjust for Division
The AAD instruction is used before division by a single-digit, unpacked, BCD
number. First you must have an unpacked, two-digit, BCD number in AX. The
AAD mstruction can then be used to adjust that number. This adjustment must
occur before any division can take place. The adjustment changes the two-digit,
unpacked, BCD number in AX into its equivalent binary number in AL. AH is
changed to OOh. Next, AX can be divided by an 8-bit, single-digit, unpacked BCD
number. The binary quotient will be in AL with the binary remainder in AH.
Note: To use this instruction with ASCII numbers the "3" in the upper nibble must
be masked out of the numbers first. fFlags affected - SF. ZF. PF. OF (undefined!.
AF (undefined!. CF (undefined!]
Microprocessor Instruction Set Tables 447
AAM
AAS
ADC
ADD
CBW
CWD
EXPANDED TABLE OF 8086/8088 INSTRUCTIONS LISTED BY CATEGORY ( Continued)
ASCII Adjust for Multiplication
The AAM instruction adjusts the product after multiplication of two, unpacked,
single-digit, BCD numbers. To use this instruction you must have two single-digit,
unpacked, BCD numbers. One must be in AL and the other in a register or
memory location. After you multiply the two single-digit, unpacked, BCD numbers
the binary answer will be in AL. The AAM instruction will convert it to its
unpacked BCD equivalent. Note: To use this instruction with ASCII numbers you
must first mask the "3" in the upper nibble. [Flags affected - SF, ZF, PF, AF
fnndefinedL OF (undefined!. CF (u ndefined)]
ASCII Adjust for Subtraction
The AAS instruction can be used after subtraction to adjust or alter the number in
AL to what it would be if the last two operands were ASCII numbers. AH will be
cleared. [Flags affected - AF, CF, OF (u ndefined!. SF (undefined), ZF
(undefined}, PF (undefined!!
AdD with Carry
The ADC instruction works the same as the ADD instruction except that it adds
the value in the carry flag (CF) to the sum of the two operands. [Flags affected^
CF. PF. AF. ZF. SF. OF]
ADD
The ADD instruction adds a binary number in a source register, memory location,
or immediate number to a destination binary number in a register or memory
location. The result is placed in the destination location. The source and
destination are assumed to be binary, both must be of the same size (byte or word),
and both cannot be memory locations. [Flags a ffected - CF, PF, AF, ZF, SF, OF]
Convert Byte to Word
The CBW instruction takes bit 7 (the highest-order bit) of AL and duplicates it in
every bit of AH. This converts an 8-bit signed-binary number in AL into a 16-bit
signed-binary number in AX. This must be done before division (IDIV) involving
two 8-bit signed-binary numbers to convert the dividend (in AL) into its 16-bit form
(in AX). (For unsigned-binary numbers place 00H in AH.) It can also be used
before integer multiplication (IMUL) involving an 8-bit operand and a 16-bit
operand. The 8-bit operand can be converted to a 16-bit operand before the IMUL
instruction is executed. [Flags affe cted - nonel
Convert Word to Double word
The CWD instruction is similar to the CBW instruction except that it converts 16-
bit values into 32-bit values instead of 8-bit to 16-bit. It takes bit 15 (the highest-
order bit) of AX and duplicates it in every bit of DX. This converts a 16-bit
signed-binary number in AX into a 32-bit signed-binary number in DX:AX (high
16 bits in DX, low 16 bits in AX). This must be done before division involving two
16-bit numbers to convert the dividend (in AX) into its 32-bit form (in DX.AX).
[Flags affected - none!
448 Microprocessor Instruction Set Tables
DAA
DAS
DIV
IDIV
IMUL
Decimal Adjust for Addition
“ thC C ° ntentS ° fALfrom a binar y number to a packed
( C ° ded de ) C,mal ) number when used after addition. When addition is
packed m BCD T™* *° ^ binary numbers ‘ If the y were “ fact
packed BCD numbers then the DAA instruction would have to be used after the
dchbon to correct the result. Note that DAA only works on AL so each byte of
mu ti-byte packed BCD number must be moved into AL, added adjusted^ and
Decimal Adjust for Subtraction
The DAS instruction adjusts the contents of AL from a binary number to a packed
CD (binary-coded-decimal) number when used after subtraction When
subtraction is Performed the operands are assumed to be binary numbers. If they
Xr I s S f DUmberS theD the ° AS instruction would have to be used
fch bt rf ° C ° rr f Ct the rCSUlt N ° te th3t DAS onl y works AL so
^ a multi-byte packed BCD number must be moved into AL, subtracted,
adjusted and then the result moved back out to make room for the next byte
[Fl ags affected - SF, ZF. AF. PF C F, OF Amde.fin.Ht] * '
Divide (unsigned)
The DIV instruction can divide a 16-bit unsigned-binary number in AX by an 8-bit
unsigned-binary number in a register or memory location. If you want to divide one
-bit number by another you must first change the dividend in AL into a 16-bit
number by placing 00H in AH. After execution the result (quotient) will be in AL
and the remainder in AH.
D| v can also divide a 32-bit unsigned-binary number in DX:AX (high-order
word in DX, low-order word in AX) by a 16-bit unsigned-binary number in a
register or memory location. If you wish to divide one 16-bit number by another
7 ““LS2 . COnV “‘ the divid “ d ” AX into a 32-bit number in DX:AX by
p acing (MOOT m DX. The result (quotient) will be in AX and the remainder in
, . . t H y^ gal ~ ° F fundefined!. SF fllndeline dl. ZF fllndeti-edl SB
(undefined), PF (undefined ), CF (undefined^
Integer Division (signed)
The IDIV instruction can divide a 16-bit signed-binary number in AX by an 8-bit
signed-binary number in a register or memory location. The result (quotient) will
be in AL and the remainder in AH. It can also divide a 32-bit signed-binary
number in DX:AX (high-order word in DX, low-order word in AX) by a 16-bit
signed-binary number in a register or memory location. The result (quotient) will
be m AX and the remainder in DX. Important! - See CBW and CWD. fFlags
~ g | ted ~ ° F fllndpfined ^ SF (undefined), ZF (u ndefined). AF (undefined PF
(undefined). CF (undefined!) --
Integer MULtiplication (signed)
The IMUL instruction multiplies a signed binary number in a register or memory
location times a signed number in AL if 8-bit or AX if 16-bit. If two 8-bit numbers
are multiplied then a 16-bit answer will be found in AX. If two 16-bit numbers are
multiplied then a 32-bit answer will be found in DX:AX (high byte in DX, low byte
in AX). To multiply an 8-bit signed binary number by a 16-bit signed-binary
number see the CBW instruction. fFlags affected - OF. CF. SF (undefined) 7F
(unde fined), AF (undefined). PF (undefined)] -
Microprocessor Instruction Set Tables 449
EXPANDED TABLE OF 8086/8088 INSTRUCTIONS LISTED BY CATEGORY ( Continued )
MUL
SBB
SUB
Lo gical Instructions
AND
NEG
NOT
MULtiply (unsigned)
The MUL instruction multiplies an unsigned binary number in a register or memory
location times an unsigned number in AL if 8-bit or AX if 16-bit. If two 8-bit
numbers are multiplied then a 16-bit answer will be found in AX. If two 16-bit
numbers are multiplied then a 32-bit answer will be found in DX:AX (high byte in
DX, low byte in AX). [Flags affected - OF. CF. SF (undefined), ZF ( undefined),
AF (undefinedi. PF (undefined)!
SuBtract with Borrow
The SBB instruction is the same as the SUB instruction except that the value in the
carry flag (CF) is also subtracted. That is, the source (second operand) and CF are
both subtracted from the destination (first operand). The source and destination
must both be either 8-bit or 16-bit. All values are assumed to be binary. [Flags
affected - OF. SF. ZF. AF. PF. CF]
SUBtract
The SUB instruction subtracts the contents of a source (the second operand m
8086/8088 assembly language) register, memory location, or an immediate number
from the contents of a destination (the first operand in 8086/8088 assembly
language) register or memory location. The result is placed in the destination
location. The source and destination must both be of the same size (byte or word)
and both cannot be memory locations. [Flags affected - CF, PF, AF, ZF, SF, OF]
logical AND
The AND instruction performs a logical AND of each bit of the source and
destination operands. The source (second operand in 8086/8088 assembly language)
can be an immediate number, register, or memory location. The destination can
be a register or memory location. Both source and destination cannot be memory
locations. Both operands can be 8-bit or both can be 16-bit. Neither can be a
segment register. After execution the source is unchanged but the destination will
contain the result of the ANDing operation. [Flags affected - OF=Q, SF, ZF, P F,
CF=0. AF (undefined)!
NEGate (2’s complement)
The NEG instruction produces the 2’s complement of a binary number. This can
be done manually by inverting each bit then adding one (1). This instruction is also
essentially the same as subtracting the number from zero. [Flags affected - OF, SF ,
ZF. AF. PF. CF1
NOT
The NOT instruction inverts every bit of the operand. The operand can be in a
register or memory location. [Flags affe cted - nonel
450 Microprocessor Instruction Set Tables
OR
The OR instruction performs a logical OR of each bit of the source and destination
operands. The source (second operand in 8086/8088 assembly language) can be an
immediate number, register, or memory location. The destination can be a register
or memory location. Both source and destination cannot be memory locations
Both operands can be 8-bit or both can be 16-bit. Neither can be a segment
register. After execution the source is unchanged but the destination will contain
the result of the ORing operation. [Flags affected - OF=Q. SF. ZF. PF C F=n AF
(undefined - )] 1 1 1 - 4 -
exclusive OR
The XOR instruction performs a logical XOR of each bit of the source and
destination operands. The source (second operand in 8086/8088 assembly language)
can be an immediate number, register, or memory location. The destination can
be a register or memory location. Both source and destination cannot be memory
locations. Both operands can be 8-bit or both can be 16-bit. Neither can be a
segment register. After execution the source is unchanged but the destination will
contain the result of the XORing operation. [Flags affected - O F=Q SF ZF PF
CF=Q, AF (undefined)] ~' l ~’ *
Shift Instructions
Rotate through Carry to the Left
CF -MSB -*-LSB *
The RCL instruction rotates the bits of the destination as shown above. After an
RCL instruction the destination will have rotated toward the left, the carry flag will
hold the bit most recently rotated out of the MSB, and the LSB will hold the bit
most recently rotated from the carry flag. The destination can be a register or
memory location. If you want to rotate one bit position you specify a "1" in the
instruction. If you want to rotate more than one bit position place the number of
bits in the CL register and include that register in the instruction.
Examples:
RCL AX,1
rotates AX one bit position
RCL AX,CL
rotates AX the number of bit positions indicated by the
number held in the CL register.
[Flags affected - OF CF]
Microprocessor Instruction Set Tables 451
RCR
ROL
EXPANDED TABLE OF 8086/8088 INSTRUCTIONS LISTED BY CATEGORY ( Continued)
Rotate through Carry to the Right
I—*- CF-► MSB-*- LSB —|
The RCR instruction rotates the bits of the destination as shown above. After an
RCR instruction the destination will have rotated toward the right, the carry flag
will hold the bit most recently rotated from the LSB, and the MSB wall hold the bit
most recently rotated from the carry flag. The destination can be a register or
memory location. If you want to rotate one bit position you specify a "1" in the
instruction. If you want to rotate more than one bit position place the number of
bits in the CL register and include that register in the instruction.
Examples:
RCR AX,1
rotates AX one bit position
RCR AX,CL
rotates AX the number of bit positions indicated by the
number held in the CL register.
[Flags affected - OF. CF1
ROtate Left
CF -*-MSB --LSB --1
The ROL instruction rotates the bits of the destination as shown above. After an
ROL instruction the destination will have rotated toward the left, and the carry flag
and the LSB will both contain the same bit which was most recently rotated into
them from the MSB. The destination can be a register or memory location. If you
want to rotate one bit position you specify a "1" in the instruction. If you want to
rotate more than one bit position place the number of bits in the CL register and
include that register in the instruction.
Examples:
ROL AX,1
rotates AX one bit position
ROL AX,CL
rotates AX the number of bit positions indicated by the
number held in the CL register.
[Flags affected - OF. CF1
452 Microprocessor Instruction Set Tables
ROR
SAL/SHL
ROtate Right
CF MSB-*- LSB-1
The ROR instruction rotates the bits of the destination as shown above. After an
ROR instruction the destination will have rotated toward the right, and the carry
flag and the MSB will both contain the same bit which was most recently rotated
into them from the LSB. The destination can be a register or memory location.
If you want to rotate one bit position you specify a "1" in the instruction. If you
want to rotate more than one bit position place the number of bits in the CL
register and include that register in the instruction.
Examples:
ROR AX,1
rotates AX one bit position
ROR AX.CL
rotates AX the number of bit positions indicated by the
number held in the CL register.
fFlaes affected - OF. CF]
Shift Arithmetic Left/SHift logical Left
CF ■* -MSB-*-LSB -*-0
The SAL or SHL instruction shifts the bits of the destination as shown above.
After an SAL/SHL instruction the destination will have shifted toward the left, the
carry flag will contain the bit most recently shifted out of the MSB, and the LSB
will contain a 0. The destination can be a register or memory location. If you want
to rotate one bit position you specify a "1" in the instruction. If you want to rotate
more than one bit position place the number of bits in the CL register and include
that register in the instruction.
Examples:
SHL AX,1
rotates AX one bit position
SHL AX,CL
rotates AX the number of bit positions indicated by the
number held in the CL register.
(Debug Note: DEBUG only allows the SHL mnemonic.)
fFlaes affected - OF. S F. ZF. PF. CF. AF (undefinpHi]
Microprocessor Instruction Set Tables 453
SAR
SHR
EXPANDED TABLE OF 8086/8088 INSTRUCTIONS LISTED BY CATEGORY ( Continued)
Shift Arithmetic Right
i-► MSB-► LSB-► CF
The SAR instruction shifts the bits of the destination as shown above. After an
SAR instruction the destination will have shifted to the right, the MSB will contain
what it did before the instruction (i.e,, it duplicates itself and shifts a copy of itself
to the right), and the carry flag will hold the bit most recently shifted out of the
LSB. The destination can be a register or memory location. If you want to rotate
one bit position you specify a "1" in the instruction. If you want to rotate more than
one bit position place the number of bits in the CL register and include that
register in the instruction.
Examples:
SAR AX,1
rotates AX one bit position
SAR AX,CL
rotates AX the number of bit positions indicated by the
number held in the CL register.
[Flavs affected - OF. SF. ZF. PF, CF. AF /undefined)!
SHift logical Right
0-►MSB-► LSB-►CF
The SHR instruction shifts the bits of the destination as shown above. After an
SHR instruction the destination will have shifted toward the right, the MSB will
contain a 0, and the carry flag will hold the bit most recently shifted in from the
LSB. The destination can be a register or memory location. If you want to rotate
one bit position you specify a "1" in the instruction. If you want to rotate more than
one bit position place the number of bits in the CL register and include that
register in the instruction.
Examples:
SHR AX,1
rotates AX one bit position
SHR AX,CL
rotates AX the number of bit positions indicated by the
number held in the CL register.
[Flags affected - OF. SF. ZF. PF. CF. AF (undefined)]
4 54 Microprocessor Instruction Set Tables
Increment and Decrement Instructions
DEC DECrement
The DEC instruction decreases the value in the destination by 1. The destination
is assumed to be a binary number and can be a register (except a segment register)
or memory location. It is worthwhile to note that the CF is not affected by this
instruction. fFlags affected - OF. SF. ZF. AF. PF]
INC INCrement
The INC instruction increases the value in the destination by 1. The destination is
assumed to be a binary number and can be a register (except a segment register)
or memory location. It is worthwhile to note that the CF is not affected by this
instruction. fFlags affected - OF. SF. ZF. AF. PF]
Unconditional .Tump Instructions
imp jump
JMP is an unconditional jump instruction which causes the 8086/8088 to continue
executing instructions at some other place in the program. The jump can be
classified as s hort , near, or for. The short and near instructions are relative to the
current instruction pointer (IP) location. Since the IP always points to the next
instruction to be executed you start counting forward or backward from the next
instruction after the JMP instruction. A short jump can be up to a maximum of
127 memory bytes forward from the current IP position (7E 16 or +127 10 ) or up to
128 memory bytes backward from the current IP position (80 16 or -128 10 ). A near
jump can be anywhere within the current 64K code segment. The assembler will
calculate this as being up to 32,767 bytes forward (7FFF 16 or +32,767 10 ) or 32,768
bytes backward (8000 16 or -32,768 10 ) from the current IP position. A far jump can
be anywhere in the 1-Mbyte addressing range of the 8086/8088. The far jump
specifies both the desired code segment (CS) and the desired instruction pointer
(IP). Debug Note: When you want to JMP you do not need to be concerned about
calculating the distance forward or backward from the current instruction pointer
(IP) position. Simply specify the location you want to go to in the form
JMP XXXX
where XXXX is the memory location (and therefore the desired instruction pointer
value) for the short and near jumps and DEBUG will determine whether this is a
forward or backward jump and will calculate the exact distance for you. Likewise
if you want to use the value in a register as your destination simply specify that
register and Debug will calculate the relative jump distance for you. In the case
of the far jump specify the location you want to jump to in the form
JMP YYYY:XXXX
where YYYY is the code segment (CS) and XXXX is the instruction pointer (IP).
[Flags affected - none]
M icr op rocessor I ns truction Set Tables 4 55
EXPANDED TABLE OF 8086/8088 INSTRUCTIONS LISTED BY CATEGORY (Continued)
Test (Compare) Instructions
CMP CoMPare
The CMP instruction is used to compare two operands for the purpose of affecting
flags according to the outcome. That is, the compare instruction subtracts the
source operand (the second operand) from the destination (the first operand).
Neither operand is changed; only the flags are affected. The source can be an
immediate number, a register, or a memory location. The destination can be a
register or memory location. Both operands cannot be memory locations. [Flags
affected - OR SF. ZF. AF, PF, CB
TEST TEST
The TEST instruction ANDs the source and destination operands but neither stores
a result nor changes either operand. Rather, the flags are affected by the ANDing.
This is useful before a conditional jump instruction. The source can be an
immediate number, register, or memory location. The destination can be a register
or memory location. Both operands cannot be memory locations. [ Flags affected :
OF=0. CF=0. SF. ZF. AF (undefined^ PF (only lower 8 bits of destination)]
Conditional Jump (Branch) Instructions
JA/JNBE Jump if Above/Jump if Not Below nor Equal
The JA/JNBE conditional jump instruction will cause program execution to transfer
to another location in a range from +127 bytes to -128 bytes from the instruction
following the jump instruction if CF=0 and if ZF=0 (both must be 0). If this
condition is not true no jump occurs. When used after CMP, this instruction is
referring to the unsigned values of the operands used by the CMP instruction.
DEBUG Note: Regardless of which mnemonic is used during assembly, DEBUG
always disassembles this op code as JA. [Flags affected - nonel
JAE/JNB/JNC Jump if Above or Equal/Jump if Not Below/Jump if No Carry
The JAE/JNB/JNC conditional jump instruction will cause program execution to
transfer to another location in a range from +127 bytes to -128 bytes from the
instruction following the jump instruction if CF=0. If this condition is not true no
jump occurs. When used after CMP, this instruction is referring to the unsigned
values of the operands used by the CMP instruction. Debug Note: Regardless of
which mnemonic is used during assembly, DEBUG always disassembles this op code
as JNB. [Flags affected - nonel
JB/JNAE/JC Jump if Below/Jump if Not Above nor Equal/Jump if Carry
The JB/JNAE/JC conditional jump instruction will cause program execution to
transfer to another location in a range from +127 bytes to -128 bytes from the
instruction following the jump instruction if CF = 1. If this condition is not true no
jump occurs. When used after CMP, this instruction is referring to the unsigned
values of the operands used by the CMP instruction. DEBUG Note: Regardless of
which mnemonic is used during assembly, DEBUG always disassembles this op code
as JB. [Flags affected - nonel
456 Microprocessor Instruction Set Tables
JBE/JNA
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
Jump if Below or Equal/Jump if Not Above
The JBE/JNA conditional jump instruction will cause program execution to transfer
to another location in a range from +127 bytes to -128 bytes from the instruction
following the jump instruction if CF=0 or ZF=1. If this condition is not true no
jump occurs. When used after CMP, this instruction is referring to the unsigned
values of the operands used by the CMP instruction. Debug Note: Regardless of
which mnemonic is used during assembly, Debug always disassembles this op code
as JBE. [Flags affected - none]
Jump if CX register is Zero
The JCXZ conditional jump instruction will cause program execution to transfer to
another location in a range from +127 bytes to -128 bytes from the instruction
following the jump instruction if the CX register is 0. If this condition is not true
no jump occurs. [Flags affected - none]
Jump if Equal to/jump if Zero
The JE/JZ conditional jump instruction will cause program execution to transfer
to another location in a range from +127 bytes to -128 bytes from the instruction
following the jump instruction if ZF=1. If this condition is not true no jump
occurs. When used after CMP, this instruction is referring to the values of the
operands used by the CMP instruction. Debug Note: Regardless of which
mnemonic is used during assembly, Debug always disassembles this op code as
JZ. [Flags affected - none]
Jump if Greater/Jump if Not Less than nor Equal
The JG/JNLE conditional jump instruction will cause program execution to transfer
to another location in a range from +127 bytes to -128 bytes from the instruction
following the jump instruction if (SF XOR OF) OR ZF = 0. To say it another
way, the jump occurs if the sign flag and the overflow flag are equal (both 0 or both
1) at the same time that the zero flag is 0. Only two combinations are possible.
If SF=0, OF=0, and ZF=0 the jump occurs; or if SF=1, OF=l, and ZF=0 the
jump also occurs. If this condition is not true no jump occurs. When used after
CMP, this instruction is referring to the signed values of the operands used by the
CMP instruction. DEBUG Note: Regardless of which mnemonic is used during
assembly, DEBUG always disassembles this op code as JG. [Flags affected - non*]
Jump if Greater than or Equal/Jump if Not Less
The JGE/JNL conditional jump instruction will cause program execution to transfer
to another location in a range from +127 bytes to -128 bytes from the instruction
following the jump instruction if SF=OF. If this condition is not true no jump
occurs. When used after CMP, this instruction is referring to the signed values of
the operands used by the CMP instruction. DEBUG Note: Regardless of which
mnemonic is used during assembly, Debug always disassembles this op code as
JGE. [Flags affected - none]
Microprocessor Instruction Set Tables 457
EXPANDED TABLE OF 8086/8088 INSTRUCTIONS LISTED BY CATEGORY ( Continued )
JL/JNGE Jump if Less/Jump if Not Greater than nor Equal
The JGE/JNL conditional jump instruction will cause program execution to transfer
to another location in a range from +127 bytes to -128 bytes from the instruction
following the jump instruction if the SF does not equal the OF. If this condition
is not true no jump occurs. When used after CMP, this instruction is referring to
the signed values of the operands used by the CMP instruction. Debug Note:
Regardless of which mnemonic is used during assembly, DEBUG always
disassembles this op code as JL. [Flags affected - none!
JLE/JNG Jump if Less than or Equal/Jump if Not Greater
The JLE/JNG conditional jump instruction will cause program execution to transfer
to another location in a range from +127 bytes to -128 bytes from the instruction
following the jump instruction if (SF XOR OF) OR ZF = 1. To say it another
way, the jump occurs if the sign flag and the overflow flag are not equal, or if the
zero flag is 0. Only two combinations do not produce the jump. If SF = 0, OF=0,
and ZF=0 then no jump occurs; or if SF=1, OF=l, and ZF=0 then no jump
occurs. When used after CMP, this instruction is referring to the signed values of
the operands used by the CMP instruction. Debug Note: Regardless of which
mnemonic is used during assembly, Debug always disassembles this op code as
JLE. [Flags affected - nonel
JNE/JNZ Jump if Not Equal to/jump if Not Zero
The JNE/JNZ conditional jump instruction will cause program execution to transfer
to another location in a range from +127 bytes to -128 bytes from the instruction
following the jump instruction if ZF = 0. If this condition is not true no jump
occurs. When used after CMP, this instruction is referring to the values of the
operands used by the CMP instruction. DEBUG Note: Regardless of which
mnemonic is used during assembly, DEBUG always disassembles this op code as
JNZ. [Flags affected - nonel
JNO Jump if Not Overflow
An overflow occurs when the result of a signed arithmetic operation is too large to
fit in the register or memory location. The JNO conditioned jump instruction will
cause program execution to transfer to another location in a range from +127 bytes
to -128 bytes from the instruction following the jump instruction if OF = 0, that is,
if an overflow has not occurred. If this condition is not true no jump occurs.
[Flags affected - nonel
JNP/JPO Jump if Not Parity/Jump if Parity Odd
When the result of an operation which affects the parity flag has a result which has
an odd number of Is in it then the PF=0. The JNP/JPO conditional jump
instruction will cause program execution to transfer to another location in a range
from +127 bytes to -128 bytes from the instruction following the jump instruction
if PF=0. If this condition is not true no jump occurs. Debug Note: Regardless of
which mnemonic is used during assembly, Debug always disassembles this op code
as JPO. [Flags affected - nonel
458 Microprocessor Instruction Set Tables
Jump if Not Sign
The JNS conditional jump instruction will cause program execution to transfer to
another location in a range from +127 bytes to -128 bytes from the instruction
following the jump instruction if SF=0. If this condition is not true no jump occurs.
Since a 0 in the sign flag occurs when the result of the last operation was a
positive signed number, this instruction is essentially saying to jump if the last
operation produced a positive signed result. fFlags affected - none]
Jump if Overflow
An overflow occurs when the result of a signed arithmetic operation is too large to
fit in the register or memory location. The JO conditional jump instruction will
cause program execution to transfer to another location in a range from +127 bytes
to -128 bytes from the instruction following the jump instruction if OF=l, that is,
if an overflow has occurred. If this condition is not true no jump occurs. fFlags
affected - none]
Jump if Parity/Jump if Parity Even
When the result of an operation which affects the parity flag has a result which has
an even number of Is in it then the PF=1. The JP/JPE conditional jump
instruction will cause program execution to transfer to another location in a range
from +127 bytes to -128 bytes from the instruction following the jump instruction
if PF= 1. If this condition is not true no jump occurs. DEBUG Note: Regardless of
which mnemonic is used during assembly, Debug always disassembles this op code
as JPE. fFlags affected - none]
Jump if Sign
The JS conditional jump instruction will cause program execution to transfer to
another location in a range from +127 bytes to -128 bytes from the instruction
following the jump instruction if SF= 1. If this condition is not true no jump occurs.
Since a 1” in the sign flag occurs when the result of the last operation was a
negative signed number, this instruction is essentially saying to jump if the last
operation produced a negative signed result. fFlags affected - none]
CALL procedure
The CALL instruction causes the 8086/8088 to leave its current location in the
program and to begin executing a procedure (a small special purpose program or
subroutine located in a different place in memory) and then automatically return
after that procedure is finished. The call can be classified as near or far. The near
instruction is relative to the current instruction pointer (IP) location. Since the IP
always points to the next instruction to be executed you start counting forward or
backward from the next instruction after the CALL instruction. A near call can be
anywhere within the current 64K code segment. The assembler will calculate this
as being up to 32,767 bytes forward (7FFF 16 or +32,767 10 ) or 32,768 bytes backward
(8000 16 or -32,768 10 ) from the current IP position. When a near call is executed the
contents of the instruction pointer (IP) are pushed onto the stack so that the
8086/8088 will know where to return after the procedure has been finished. A far
call can be anywhere in the 1-Mbyte addressing range of the 8086/8088. The far
call specifies both the desired code segment (CS) and the desired instruction pointer
Microprocessor Instruction Set Tables 459
RET
Stack
POP
POPF
EXPANDED TABLE OF 8086/8088 INSTRUCTIONS LISTED BY CATEGORY (Continued)
(IP). When a far call is executed the contents of both the instruction pointer (IP)
and the code segment (CS) are pushed onto the stack so that the 8086/8088 will
know where to return after the procedure has been finished. Debug Note: When
you want to CALL a procedure you do not need to be concerned about calculating
the distance forward or backward from the current instruction pointer (IP)
position. Simply specify the location of the procedure in the form
CALL XXXX
where XXXX is the memory location (and therefore the desired instruction pointer
value) for the near call and DEBUG will determine whether that location is forward
or backward and will calculate the exact distance for you. Likewise if you want
to use the value in a register as your destination simply specify that register and
DEBUG will calculate the relative distance for you. In the case of a far call specify
the location of the procedure in the form
CALL YYYYiXXXX
where YYYY is the code segment (CS) and XXXX is the instruction pointer (IP).
(See also RETurn.) [Flags affected - none]
RETurn from subroutine
The RET instruction is placed at the end of a procedure or subroutine. It marks
the end of that procedure and causes the 8086/8088 to return to the instruction
immediately following the CALL instruction which began this particular procedure.
The 8086/8088 knows where to return because the CALL instruction pushed the
contents of the instruction pointer (IP) onto the stack. The RET instruction pops
the value of the IP from the stack and places it in the IP. In the case of a far call
the return instruction pops both the IP value and the code segment (CS) value from
the stack. DEBUG Note: Debug accepts both RET and RETN as the mnemonics
for a return from a near call. When disassembled both will appear as RET. To
specify a return from a far call the mnemonic RETF must be used and it will be
disassembled as RETF. [Flags affected - none]
POP from stack
The POP instruction copies the word at the top of the stack to the destination
operand. The destination can be a general-purpose register, segment register, or
two consecutive memory locations. (The CS register is illegal.) After the POP, the
stack pointer (SP) is incremented by 2 to point to the new top-of-stack. [Flags
affected - none]
POP Flags from stack
The POPF instruction copies the word at the top of the stack into the flag register,
replacing the values of all flags. The stack pointer (SP) is then incremented by 2.
(Using POPF and PUSHF provides a way to change the TF. There is no
instruction for directly altering this flag.) [Flags affected - OF. DF. IF. TF. SF. ZF.
AF, PF, CF]
460 Microprocessor Instruction Set Tables
PUSH
PUSH onto stack
The PUSH instruction decrements the stack pointer (SP) by 2 and then copies the
source operand (word) to the new top-of-stack. The source can be a general-
purpose register, segment register, or two consecutive memory locations. [Flags
affected - none]
PUSHF PUSH Flags onto stack
The PUSHF instruction decrements the stack pointer (SP) by 2 and then copies the
flag register to the new top-of-stack. fFlaes affected - none]
Interrupt Instructions
I NT INTerrupt
The INT instruction causes program execution to be transferred to a special type
of routine whose address is pointed to by an interrupt vector. There are 256
interrupt vectors in memory locations OOOOOh to 003FFh. Each vector is 4 bytes in
length and contains the address (CS:IP) of the routine which handles this particular
type of interrupt. The INT operand is a decimal number from 0 through 255 which
identifies which interrupt vector is to be used. The actual memory location of the
interrupt is calculated by multiplying the operand by 4. That answer forms the
decimal equivalent of the beginning of the four memory locations which hold the
interrupt vector. When the INT instruction is executed the following occur:
1. The stack pointer is decremented by 2 and the flags are pushed onto the
stack.
2. IF and TF are cleared.
3. The stack pointer is decremented by 2 and CS is pushed onto the stack.
4. The new CS is fetched from the interrupt vector and the interrupt vector
+ 1 .
5. The stack pointer is decremented by 2 and IP is pushed onto the stack.
6. The new IP is fetched from the interrupt vector + 2 and the interrupt
vector + 3.
7. Begin execution of the interrupt routine located at memory location CS:IP.
The routine will continue until a IRET instruction is encountered, at which point
program execution will pick up where it left off immediately after the INT
instruction. fFlaes affected - IF and TF]
INTO INTerrupt on Overflow
The INTO instruction initiates a software interrupt which is, in all respects, the
same as that produced by the INT instruction except that the INTO instruction is
conditional, and the operand cannot be specified but is automatically type 4. That
is, the INTO instruction will branch to the interrupt routine only if OF = 1 and there
is no choice as to where the interrupt vector will come from. It will always be a
Microprocessor Instruction Set Tables 461
EXPANDED TABLE OF 8086/8088 INSTRUCTIONS LISTED BY CATEGORY ( Continued)
type 4 interrupt which is held in the 4 bytes starting at memory location lOh. This
instruction is most often used after arithmetic operations to handle any overflow
conditions. See the discussion for the I NT instruction for more details, [Flags
affected - IF and TF1
TRET Interrupt RETurn
The IRET instruction is used to return from an interrupt routine (whether a
hardware or software interrupt). The IP, CS, and flags are all popped from the
stack and program execution continues from the instruction immediately following
the INT instruction. The IRET instruction has no operand. [Flags affected - OF,
DF. IF. TF. SF. ZF. AF, FF. CF1
Input-Output Instructions
IN INput
The IN instruction allows a byte or word to be acquired from an I/O device
[source] and placed in AL (byte) or AX (word) [destination]. An I/O address
[source operand] from OOh through FFh can be specified directly in the instruction.
If an address larger than FFh is desired a 16-bit address can be placed in DX used
as the source operand in the IN instruction. Only AX and AL can be used as
destinations [destination operand] by the IN instruction.
Example:
IN AL,45 copy a byte from I/O address 45h into AL
IN AX,78 copy a word from I/O address 78h into AX
IN AL,DX copy a byte from the I/O address pointed to by the contents
of DX and place in AL
I/O port addresses F8h through FFh are reserved by Intel for future hardware and
software products and should not be used for any other purpose. [Flags affected -
none]
OUT OUTput
The OUT instruction allows a byte or word to be sent from AL (byte) or AX
(word) [source] to an I/O device [destination]. An I/O address [destination
operand] from OOh through FFh can be specified directly in the instruction. If an
address larger than FFh is desired a 16-bit address can be placed in DX used as the
destination operand in the OUT instruction. Only AX and AL can be used as
sources [source operand] by the OUT instruction.
Example:
OUT 45,AL copy a byte from AL to I/O address 45h
462 Microprocessor Instruction Set Tables
OUT 78,AX copy a word from AX to I/O address 78h
String Instructions
CMPS/CMPSB/CMPSW
LODS/LODSB/LODSW
MOVS/MOVSB/MOVSW
OUT DX,AL copy a byte from AL to the I/O address pointed to by the
contents of DX
I/O port addresses F8h through FFh are reserved by Intel for future hardware and
software products and should not be used for any other purpose. IFlags affected -
none]
CoMpare Strings/CoMPare Strings Byte/CoMPare Strings Word
The CMPS/CMPSB/CMPSW instruction is used to compare the contents of two
memory bytes, two words, or two entire sections of memory. The SI (source index)
is used to point to the source in the DS (data segment). The DI (destination index)
is used to point to the destination in the ES (extra segment). The 8086/8088 makes
the comparison by subtracting the destination from the source. Neither operand is
changed by the comparison; only flags are affected. After the comparison DI and
SI are automatically incremented (if DF=0) or decremented (if DF=1). The
increment/decrement is 1 if the CMPB mnemonic is used or 2 if CMPW is used.
The REP/REPE/REPZ and REPNE/REPNZ repeat prefixes can be used with this
instruction to compare an entire section of memory. Debug Note: Only the
CMPSB and CMPSW mnemonics are accepted by DEBUG. [Flags affected - OF.
SF. ZF. AF. PF. CF]
LOaD String/LOaD String Byte/LOaD String Word
The LODS/LODSB/LODSW instruction loads (copies) either a byte (LODSB)
from the memory location pointed to by SI into AL, or a word (LODSW) from the
memory location pointed to by SI into AX. SI is either automatically incremented
by 1 (LODSB) or by 2 (LODSW) if DF=0, or SI is automatically decremented by
1 (LODSB) or by 2 (LODSW) if DF=1. The REP/REPE/REPZ and
REPNE/REPNZ repeat prefixes can be used with this instruction. DEBUG Note:
Debug only accepts the LODSB and LODSW mnemonics. IFlags affected - none] ,
MOVe String/MOVe String Byte/MOVe String Word
The MOVS/MOVSB/MOVSW instruction is used to transfer the contents of a
block of memory to another area in memory. The SI (source index) is used to
point to the source in the DS (data segment). The DI (destination index) is used
to point to the destination in the ES (extra segment). After the move DI and SI
are automatically incremented (if DF=0) or decremented (if DF=1). The
increment/decrement is 1 if the MOVSB mnemonic is used or 2 if MOVSW is
used. The REP/REPE/REPZ and REPNE/REPNZ repeat prefixes can be used
with this instruction to move an entire section of memory. Debug Note: Only the
MOVSB and MOVSW mnemonics are accepted by Debug, fFlags affected - none]
Microprocessor Instruction Set Tables 463
EXPANDED TABLE OF 8086/8088 INSTRUCTIONS LISTED BY CATEGORY ( Continued)
REP/REPE/REPZ
REPNE/REPNZ
SCAS/SCASB/SCASW
STOS/STOSB/STOSW
Loop Instructions
LOOP
REPeat/REPeat if Equal/REPeat if Zero
REP/REPE/REPZ is a prefix which causes string instructions to be repeated the
number of times indicated by the value in CX. Each time the string instruction is
repeated CX is decremented by one. This continues 1) in the case of MOVS and
STOS, until CX = 0, or 2) in the case of CMPS and SCAS, until either CX=0 or
the compared bytes or words are not equal (ie. ZF=0). Debug Note: REP, REPE,
and REPZ are all mnemonics for the same op code and Debug disassembles all
of them as REPZ. [Flags affected - nonel
REPeat if Not Equal/REPeat if Not Zero
REPNE/REPNZ is a prefix which causes string instructions to be repeated the
number of times indicated by the value in CX. Each time the string instruction is
repeated CX is decremented by 1. This continues 1) in the case of MOVS and
STOS, until CX = 0, or 2) in the case of CMPS and SCAS, until either CX = 0 or
the compared bytes or words are equal (ie. ZF=1). DEBUG Note: REPNE and
REPNZ are mnemonics for the same op code and DEBUG disassembles all of them
as REPNZ. [Flags affected - none]
SCAn String/SCAn String Byte/SCAn String Word
The SCAS/SCASB/SCASW instruction is used to check a string for the occurrence
or non-occurrence of a particular byte or word. The instruction accomplishes this
by subtracting the byte or word in the extra segment (ES) which is pointed to by
DI from AL (if a byte) or AX (if a word). Neither the contents of the string nor
those of AX/AL are changed; however the flags are affected by the operation.
After the operation, DI is automatically incremented (if DF = 0) or decremented (if
DF = 1). DI will be incremented or decremented by 1 for byte scans or by 2 for
word scans. The REP/REPE/REPZ prefix can be used to scan for the non¬
occurrence of a byte or word. The REPNE/REPNZ prefix can be used to scan for
the occurrence of a byte or word. Debug Note: Debug only recognizes the SCASB
and SCASW mnemonics. [Flags affected - OF. SF. ZF. AF. PF. CF1
STOre String/STOre String Byte/STOre String Word
The STOS/STOSB/STOSW instruction copies a byte from AL or a word from AX
to a memory location in the extra segment (ES) pointed to by DI. After the
operation, DI is automatically incremented (if DF=0) or decremented (if DF=1).
DI will be incremented or decremented by 1 for a byte store or by 2 for a word
store. The REP/REPE/REPZ and REPNE/REPNZ repeat prefixes can be used
with this instruction to store a certain value in a range of memory locations.
DEBUG Note: Only the STOSB and STOSW mnemonics are accepted by DEBUG.
[Flags affected - nonel
LOOP
The LOOP instruction provides a way to repeat a group of instructions the number
of times indicated by the value in the CX register. The LOOP instruction
unconditionally transfers program execution to a memory location in the range of -
128 to +127 bytes from the address of the instruction immediately following the
464 Microprocessor Instruction Set Tables
LOOP instruction if CX > 0. Each time the LOOP instruction is executed CX is
decremented by 1; then the value of CX is checked. If CX > 0, program execution
will branch to the location indicated by the operand of the LOOP instruction. If
CX = 0, the program does not branch and the instruction immediately following
the LOOP instruction is executed next. As CX is decremented wraparound occurs
from OOOOh to FFFFh. 1 Flags affected - none]
LOOPE/LOOPZ LOOP while Equal/LOOP while Zero
The LOOPE/LOOPZ instruction provides a way to repeat a group of instructions
the number of times indicated by the value in the CX register. The
LOOPE/LOOPZ instruction transfers program execution to a memory location in
the range of -128 to +127 bytes from the address of the instruction immediately
following the LOOP instruction if CX > 0 and ZF=1. Each time the LOOP
instruction is executed CX is decremented by 1; then the values of CX and ZF are
checked. If CX > 0, program execution will branch to the location indicated by the
operand of the LOOP instruction if ZF=1 also. If either CX = 0 or ZF=0, the
program does not branch, and the instruction immediately following the LOOP
instruction is executed next. As CX is decremented wraparound occurs from OOOOh
to FFFFh. fFlags affected - none]
LOOPNE/LOOPNZ LOOP while Not Equal/LOOP while Not Zero
The LOOPNE/LOOPNZ instruction provides a way to repeat a group of
instructions the number of times indicated by the value in the CX register. The
LOOPNE/LOOPNZ instruction transfers program execution to a memory location
in the range of -128 to +127 bytes from the address of the instruction immediately
following the LOOP instruction if CX > 0 and ZF=0. Each time the LOOP
instruction is executed CX is decremented by 1; then the values of CX and ZF are
checked. If CX > 0, program execution will branch to the location indicated by the
operand of the LOOP instruction if ZF=0 also. If either CX = 0 or ZF=1, the
program does not branch, and the instruction immediately follo wing the LOOP
instruction is executed next. As CX is decremented wraparound occurs from OOOOh
to FFFFh. IFlags affected - none]
CONDENSED TABLE OF 8086/8088 INSTRUCTIONS LISTED BY CATEGORY
CPU Control Instructions
ESC
ESCape
HLT
HaLT
LOCK
LOCK
NOP
No OPeration
WAIT
WAIT
Microprocessor Instruction Set Tables 465
CONDENSED TABLE OF 8086/8088 INSTRUCTIONS LISTED BY CATEGORY ( Continued)
Data Transfer Instructions
LAHF
Load AH from Flag
LDS
Load Data Segment
LEA
Load Effective Address
LES
Load Extra Segment
MOV
MOVe
SAHF
Store AH in Flags
XCHG
eXCHanGe
XLAT
trans(X)LATe
Flag Instructions
CLC
CLear Carry flag
CLD
CLear Direction flag (auto-increment)
CLI
CLear Interrupt-enable flag
CMC
CoMplement Carry flag
STC
SeT Carry flag
STD
SeT Direction flag (auto-decrement)
STI
SeT Interrupt enable flag
Arithmetic Instructions
AAA
ASCII Adjust for Addition
AAD
ASCII Adjust for Division
AAM
ASCII Adjust for Multiplication
AAS
ASCII Adjust for Subtraction
ADC
AdD with Carry
ADD
ADD
CBW
Convert Byte to Word
CWD
Convert Word to Double word
DAA
Decimal Adjust for Addition
DAS
Decimal Adjust for Subtraction
DIV
Divide (unsigned)
IDIV
Integer Division (signed)
IMUL
Integer MULtiplication (signed)
MUL
MULtiply (unsigned)
SBB
SuBtract with Borrow
SUB
SUBtract
Logical Instructions
AND
logical AND
NEC
NEGate (2’s complement)
NOT
NOT
OR
OR
XOR
exclusive OR
466 Microprocessor Instruction Set Tables
Rotate and Shift Instructions
RCL
Rotate through Carry to the Left
RCR
Rotate through Carry to the Right
ROL
ROtate Left
ROR
ROtate Right
SAL/SHL
Shift Arithmetic Left/SHift logical LefT
SAR
Shift Arithmetic Right
SHR
SHift logical Right
Increment and Decrement Instructions
DEC
DECrement
INC
INCrement
Unconditional .TumD Instructions
JMP
Jump
Test (Compare) Instructions
CMP
CoMPare
TEST
TEST
Conditional .TumD (Branch) Instructions
JA/JNBE
Jump if Above/Jump if Not Below nor Equal
JAE/JNB/JNC
Jump if Above or Equal/Jump if Not Below/Jump if No Carry
JB/JNAE/JC
Jump if Below/Jump if Not Above nor Equal/Jump if Carry
JBE/JNA
Jump if Below or Equal/Jump if Not Above
JCXZ
Jump if CX register is Zero
JE/JZ
Jump if Equal to/jump if Zero
JG/JNLE
Jump if Greater/Jump if Not Less than nor Equal
JGE/JNL
Jump if Greater than or Equal/Jump if Not Less
JL/JNGE
Jump if Less/Jump if Not Greater than nor Equal
JLE/JNG
Jump if Less than or Equal/Jump if Not Greater
JNE/JNZ
Jump if Not Equal to/jump if Not Zero
JNO
Jump if Not Overflow
JNP/JPO
Jump if Not Parity/Jump if Parity Odd
JNS
Jump if Not Sign
JO
Jump if Overflow
JP/JPE
Jump if Parity/Jump if Parity Even
JS
Jump if Sign
Microprocessor Instruction Set Tables
467
CONDENSED TABLE OF 8086/8088 INSTRUCTIONS LISTED BY CATEGORY ( Continued)
Subroutine Instructions
CALL
RET
Stack Instructions
POP
POPF
PUSH
PUSHF
Interrupt Instructions
INT
INTO
IRET
Input-Output Instructions
IN
OUT
String Instructions
CMPS/CMPSB / CMPSW
LODS/LODSB/LODSW
MO VS/MO VSB/MO VSW
REP/REPE/REPZ
REPNE/REPNZ
SCAS/SCASB/SCASW
STOS/STOSB/STOSW
Loop Instructions
LOOP
LOOPE/LOOPZ
LOOPNE/LOOPNZ
CALL procedure
RETurn from subroutine
POP from stack
POP Flags from stack
PUSH onto stack
PUSH Flags onto stack
INTerrupt
INTerrupt on Overflow
Interrupt RETurn
INput
OUTput
CoMpare Strings/CoMPare Strings Byte/CoMPare Strings Word
LOaD String/LOaD String Byte/LOaD String Word
MOVe String/MOVe String Byte/MOVe String Word
REPeat/REPeat if Equal/REPeat if Zero
REPeat if Not Equal/REPeat if Not Zero
SCAn String/SCAn String Byte/SCAn String Word
STOre String/STOre String Byte/STOre String Word
LOOP
LOOP while Equal/LOOP while Zero
LOOP while Not Equal/LOOP while Not Zero
468 Microprocessor Instruction Set Tables
CONDENSED TABLE OF 8086/8088 INSTRUCTIONS LISTED ALPHABETICALLY
AAA
AAD
AAM
AAS
ADC
ADD
AND
CALL
CBW
CLC
CLD
CLI
CMC
CMP---
CMPS/CMPSB/CMPSW
CWD
DAA
DAS
DEC
DIV
ESC
HLT
IDIV
IMUL
IN
INC
INT
INTO
IRET
JA/JNBE
JAE/JNB/JNC
JB/JNAE/JC
JBE/JNA
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LAHF
LDS
ASCII Adjust for Addition
ASCII Adjust for Division
ASCII Adjust for Multiplication
ASCII Adjust for Subtraction
AdD with Carry
ADD
logical AND
CALL procedure
Convert Byte to Word
CLear Carry flag
CLear Direction flag (auto-increment)
CLear Interrupt-enable flag
CoMplement Carry flag
CoMPare
CoMpare Strings/CoMPare Strings Byte/CoMPare Strings Word
Convert Word to Double word
Decimal Adjust for Addition
Decimal Adjust for Subtraction
DECrement
Divide (unsigned)
ESCape
HaLT
Integer Division (signed)
Integer MULtiplication (signed)
INput
INCrement
INTerrupt
INTerrupt on Overflow
Interrupt RETurn
Jump if Above/Jump if Not Below nor Equal
Jump if Above or Equal/Jump if Not Below/Jump if No Carry
Jump if Below/Jump if Not Above nor Equal/Jump if Carry
Jump if Below or Equal/Jump if Not Above
Jump if CX register is Zero
Jump if Equal to/jump if Zero
Jump if Greater/Jump if Not Less than nor Equal
Jump if Greater than or Equal/Jump if Not Less
Jump if Less/Jump if Not Greater than nor Equal
Jump if Less than or Equal/Jump if Not Greater
JuMP unconditional
Jump if Not Equal to/jump if Not Zero
Jump if Not Overflow
Jump if Not Parity/Jump if Parity Odd
Jump if Not Sign
Jump if Overflow
Jump if Parity/Jump if Parity Even
Jump if Sign
Load AH from Flag
Load Data Segment
Microprocessor Instruction Set Tables
469
CONDENSED TABLE OF 8086/8088 INSTRUCTIONS LISTED ALPHABETICALLY ( Continued)
LEA
LES
LOCK
LODS/LODSB/LODSW
LOOP
LOOPE/LOOPZ
LOOPNE/LOOPNZ
MOV
MO VS/MO VSB/MOVSW
MUL
NEC
NOP
NOT
OR
OUT
POP
POPF
PUSH
PUSHF
RCL
RCR
REP/REPE/REPZ
REPNE/REPNZ
RET
ROL
ROR
SAHF
SAL/SHL
SAR
SBB
SCAS/SCASB/SCASW
SHR
STC
STD
STI
STOS/STOSB/STOSW
SUB
TEST
WAIT
XCHG
XLAT
XOR
Load Effective Address
Load Extra Segment
LOCK
LOaD String/LOaD String Byte/LOaD String Word
LOOP
LOOP while Equal/LOOP while Zero
LOOP while Not Equal/LOOP while Not Zero
MOVe
MOVe String/MOVe String Byte/MOVe String Word
MULtiply (unsigned)
NEGate (2’s complement)
No OPeration
NOT
OR
OUTput
POP from stack
POP Flags from stack
PUSH onto stack
PUSH Flags onto stack
Rotate through Carry to the Left
Rotate through Carry to the Right
REPeat/REPeat if Equal/REPeat if Zero
REPeat if Not Equal/REPeat if Not Zero
RETurn from subroutine
ROtate Left
ROtate Right
Store AH in Flags
Shift Arithmetic Left/SHift logical Left
Shift Arithmetic Right
SuBtract with Borrow
SC An String/SCAn String Byte/SCAn String Word
SHift logical Right
SeT Carry flag
SeT Direction flag (auto-decrement)
SeT Interrupt enable flag
STOre String/STOre String Byte/STOre String Word
SUBtract
TEST
WAIT
eXCHanGe (source with destination)
trans(X)LATe
exclusive OR
470 Microprocessor Instruction Set Tables
EXPANDED TABLE OF 6502 INSTRUCTIONS LISTED BY CATEGORY
Mne- Operation Boolean/Arith Flags Address Assembler Op ~ #
mon ' c _ Operation NV-BDIZC Mode Notation
CPU Control Instructions
NOP No Operation
Nothing
xx-xxxxx
Implied
NOP
EA 2 1
BRK BReaK (forced
interrupt)
PC + 2 S
SP - 2 -> SP
PSR -> S
SP - 1 -» s
SFFFE -» PC
xx-lxlxx
Implied
BRK
00 7 1
Data Transfer Instructions
LDA
LoaD Accumulator
M -» A
Nx-xxxZx
Immediate
LDA #$dd
A9
2
2
Absolute
LDA $aaaa
AD
4
3
Zero Page
LDA $aa
A5
3
2
Indxd Indct
LDA ($ff,X)
A1
6
2
IndctIndxd
LDA ($aa),Y
B1
5*
2
Zero page,X
LDA $ff,X
B5
4
2
Absolute,X
LDA $ffff,X
BD
4*
3
Absolute,Y
LDA $ffff,Y
B9
4*
3
LDX
LoaD X register
M X
Nx-xxxZx
Immediate
LDX #$dd
A2
2
2
Absolute
LDX $aaaa
AE
4
3
Zero page
LDX $aa
A6
3
2
Absolute,Y
LDX $ffff,Y
BE
4*
3
Zero page,Y
LDX $ff,Y
B6
4
2
LDY
LoaD Y register
M -> Y
Nx-xxxZx
Immediate
LDY #$dd
AO
2
2
Absolute
LDY $aaaa
AC
4
3
Zero page
LDY $aa
A4
3
2
Zero page,X
LDY $ff,X
B4
4
2
Absolute,X
LDY $ffff,X
BC
4*
3
STA
STore Accumulator
A + M
xx-xxxxx
Absolute
STA $aaaa
8D
4
3
Zero page
STA $aa
85
3
2
Indxd Indct
STA ($ff,X)
81
6
2
Indct Indxd
STA ($aa),Y
91
6
2
Zero page,X
STA $ff,X
95
4
2
Absolute,X
STA $ffff,X
9D
5
3
Absolute,Y
STA $ffff,Y
99
5
3
STX
STore X register
X -» M
xx-xxxxx
Absolute
STX $aaaa
8E
4
3
Zero page
STX $aa
86
3
2
Zero page,Y
STX $ff,Y
96
4
2
STY
STore Y register
Y - M
xx-xxxxx
Absolute
STY $aaaa
8C
4
3
Zero page
STY $aa
84
3
2
Zero page,X
STY $ff,X
94
4
2
TAX
Transfer Accumulator A -> X
Nx-xxxZx
Implied
TAX
AA
2
1
to X register
TXA
Transfer X register
X -► A
Nx-xxxZx
Implied
TXA
8A
2
1
to Accumulator
Notes
Microprocessor Instruction Set Tables
471
EXPANDED TABLE OF 6502 INSTRUCTIONS LISTED BY CATEGORY ( Continued )
Mne¬
monic
Operation Boolean/Arith
Operation
Flags
NV-BDIZC
Address
Mode
Assembler
Notation
Op
#
Notes
TAY
Transfer Accumulator A -» Y
to Y register
Nx-xxxZx
Implied
TAY
A8
2
1
TYA
Transfer Y register Y ■* A
to Accumulator
Nx-xxxZx
Implied
TYA
98
2
1
Flae Instructions
CLC
CLear Carry flag
0 C
xx-xxxxO
Implied
CLC
18
2
1
CLD
CLear Decimal flag
0 -> D
xx-xOxxx
Implied
CLD
D8
2
1
CLI
CLear Interrupt flag
0 + I
xx-xxOxx
Implied
CLI
58
2
1
CLV
CLear overflow flag
0 -» V
xO-xxxxx
Implied
CLV
B8
2
1
SEC
SEt Carry flag
1 * c
xx-xxxxl
Implied
SEC
38
2
1
SED
SEt Decimal flag
1 * D
xx-xlxxx
Implied
SED
F8
2
1
SEI
SEt Interrupt flag
1 -* I
xx-xxlxx
Implied
SEI
78
2
1
Arithmetic Instructions
ADC AdD with Carry
A + M + C -» A
NV-xxxZC
Immediate
ADC #$dd
69
2
2
The carry flag must be cleared
Absolute
ADC $aaaa
6D
4
3
before single-precision addition
Zero page
ADC $aa
65
3
2
or before the first byte of
Indxd Indct
ADC ($ff,X)
61
6
2
multiple-precision addition.
IndctIndxd
ADC ($aa),Y
71
5*
2
Zero page,X
ADC $ff,X
75
4
2
Absolute,X
ADC $ffff,X
7D
4*
3
Absolute,Y
ADC $ffff,Y
79
4*
3
SBC SuBtract with Carry
A - M -
NV-xxxZC
Immediate
SBC #$dd
E9
2
2
The carry flag must be set
(l-C) - A
Absolute
SBC $aaaa
ED
4
3
before single-precision
Zero page
SBC Saa
E5
3
2
subtraction or before the First
Note: (l-C) =
Indxd Indct
SBC ($ff,X)
El
6
2
byte of multiple-precision
Borrow
Indct Indxd
SBC ($aa),Y
FI
5*
2
subtraction.
Zero page,X
SBC $ff,X
F5
4
2
Absolute,X
SBC $ffff,X
FD
4*
3
The operation of the carry flag
Absolute,Y
SBC Sffff.Y
F9
4*
3
is inverted during subtraction.
Logical Instructions
AND logical AND
A AND M -> A
Nx-xxxZx Immediate
AND #$dd
29
2
2
Absolute
AND $aaaa
2D
4
3
Zero page
AND Saa
25
3
2
Indxd Indct
AND ($ff,X)
21
6
2
Indct Indxd
AND ($aa),Y
31
5
2
Zero page,X
AND $ff,X
35
4
2
Absolute,X
AND $ffff,X
3D
4*
3
Absolute,Y
AND Sffff.Y
39
4*
3
472 Microprocessor Instruction Set Tables
Mne- Operation
monic
EOR Exclusive OR
ORA OR Accumulator
BIT test memory BITs
ASL Arithmetic Shift
Left
LSR Logical Shift Right
ROL Rotate Left
ROR ROtate Right
INC INCrement memory
Boolean/Arith
Operation
Flags
NV-BDIZC
Address
Mode
Assembler
Notation
Op
- #
A EOR M -> A
Nx-xxxZx
Immediate
EOR #$dd
49
2 2
Absolute
EOR Saaaa
4D
4 3
Zero page
EOR $aa
45
3 2
Indxd Indct
EOR ($ff,X)
41
6 2
Indct Indxd
EOR ($aa),Y
51
5* 2
Zero page,X
EOR $ff,X
55
4 2
Absolute,X
EOR $ffff,X
5D
4* 3
Absolute,Y
EOR $ffff,Y
59
4* 3
A OR M-*A
Nx-xxxZx
Immediate
ORA #$dd
09
2 2
Absolute
ORA Saaaa
0D
4 3
Zero page
ORA Saa
05
3 2
Indxd Indct
ORA ($ff,X)
01
6 2
IndctIndxd
ORA ($aa),Y
11
5 2
Zero page,X
ORA $ff,X
15
4 2
Absolute,X
ORA Sffff.X
ID
4* 3
Absolute,Y
ORA Sffff.Y
19
4* 3
A AND M
76-xxxZx
Absolute
BIT Saaaa
2C
4 3
M 7 -» N
Zero page
BIT Saa
24
3 2
m 6 + v
Rotate and Shift Instructions
C «- 7...0 <- 0
Nx-xxxZC
Absolute
ASL Saaaa
0E
6
3
Zero page
ASL $aa
06
5
2
Accumulator
ASL A
0A
2
1
Zero page,X
ASL $ff,X
16
6
2
Absolute,X
ASL $ffff,X
IE
7
3
0 ■* 7...0 -* C
Ox-xxxZC
Absolute
LSR Saaaa
4E
6
3
Zero page
LSR Saa
46
5
2
Accumulator
LSR A
4A
2
1
Zero page,X
LSR $ff,X
56
6
2
Absolute,X
LSR $ffff,X
5E
7
3
Notes
Memory bits 7 and 6 are
transferred into the N and V
flags respectively.
Nx-xxxZC
Absolute ROL
Zero page ROL
Accumulator ROL
Zero page,X ROL
Absolute,X ROL
Saaaa
2E
6
3
Saa
26
5
2
A
2A
2
1
Sff,X
36
6
2
Sffff,X
3E
7
3
a
Nx-xxxZC
Absolute ROR
Zero page ROR
Accumulator ROR
Zero page,X ROR
Absolute,X ROR
Saaaa
6E
6
3
Saa
66
5
2
A
6A
2
1
$ff,X
76
6
2
Sffff,X
7E
7
3
Increment and Decrement Instructions
Absolute
INC Saaaa
EE
6
3
Zero page
INC Saa
E6
5
2
Zero page,X
INC $ff,X
F6
6
2
Absolute,X
INC Sffff,X
FE
7
3
Microprocessor Instruction Set Tables 473
EXPANDED TABLE OF 6502 INSTRUCTIONS LISTED BY CATEGORY ( Continued)
Mne- Operation Boolean/Arith Flags Address Assembler Op - # Notes
monic Operation NV-BDIZC Mode_Notation __
I NX
INcrement X
register
X + 1 -> X
Nx-xxxZx
Implied
INX
E8
2
1
I NY
INcrement Y
register
Y + 1 -> Y
Nx-xxxZx
Implied
INY
C8
2
1
DEC
DECrement memory
M - 1 4 M
Nx-xxxZx
Absolute
DEC Saaaa
CE
6
3
Zero page
DEC $aa
C6
5
2
Zero page,X
DEC $ff,X
D6
6
2
Absolute,X
DEC $ffff,X
DE
7
3
DEX
DEcrement X
register
X - 1 -> X
Nx-xxxZx
Implied
DEX
CA
2
1
DEY
DEcrement Y
register
Y - 1 * Y
Nx-xxxZx
Implied
DEY
88
2
1
Unconditional Jump Instructions
JMP
JuMP to new
aaaa -> PC
xx-xxxxx
Absolute
JMP Saaaa
4C
3
3
In the indirect addressing
memory location
{abs addressing}
Indirect
JMP (Saaaa)
6C
5
3
mode, aaaa is not transferred
into the PC but rather the
(aaaa) 4 PC^
contents of memory location
(aaaa + 1) *♦ PC H
aaaa and aaaa + 1 are placed in
(indirect addressing}
the PC
Special Note: Care should be
used with this mode because of
a bug in the 6502 chip family. If
the indirect address is located
at a page boundary (example,
JMP ($5FFF)} an incorrect
address will be generated.
Test (Compare') Instructions
CMP
CoMPare memory
A-M
Nx-xxxZC
Immediate
CMP #$dd
C9
2 2
location to
Absolute
CMP Saaaa
CD
4 3
accumulator
Zero page
CMP Saa
C5
3 2
Indxd Indct
CMP ($ff,X)
Cl
6 2
Indct Indxd
CMP ($aa),Y
D1
5* 2
Zero page,X
CMP $ff,X
D5
4 2
Absolute,X
CMP $ffff,X
DD
4* 3
Absolute,Y
CMP $ffff,Y
D9
4* 3
CPX
ComPare memory
X- M
Nx-xxxZC
Immediate
CPX #$dd
E0
2 2
location to X
Absolute
CPX Saaaa
EC
4 3
register
Zero page
CPX Saa
E4
3 2
CPY
ComPare memory
Y - M
Nx-xxxZC
Immediate
CPY #$dd
CO
2 2
location to Y
Absolute
CPY Saaaa
cc
4 3
register
Zero page
CPY Saa
C4
3 2
474 Microprocessor Instruction Set Tables
Mne- Operation
monic
BCC Branch if Carry
Clear
BCS Branch if Carry
Set
BEO Branch if last
result EQual to
zero
BNE Branch if last
result Not Equal
to zero
BMI Branch if last
result a Minus
(neg) number
BPL Branch is last
result a PLus
(pos) number
BVC Branch if
oVerflow flag
Clear
BVS Branch if
oVerflow flag
Set
JSR Jump to SubRoutine
RTS ReTum from
Subroutine
PI1A PusH Accumulator
onto stack
PLA PulL Accumulator
from stack
PHP PusH Processor
status register
onto stack
Boolean/Arith Flags Address Assembler Op - #
Operation _ NV-BDIZC Mode _ Notation
Conditional Jump ('Branch') Instructions
PC + rr -» PC
if C = 0
xx-xxxxx
Relative
BCC Sit
90 2 + 2
PC + rr -> PC
if C=1
xx-xxxxx
Relative
BCS Srr
BO 2 + 2
PC + rr ^ PC
if Z= 1
xx-xxxxx
Relative
BEQ Srr
F0 2 + 2
PC + rr -» PC
if Z=0
xx-xxxxx
Relative
BNE Srr
DO 2 + 2
PC + rr -> PC
if N=1
xx-xxxxx
Relative
BMI Srr
30 2 + 2
PC + rr + PC
if N = 0
xx-xxxxx
Relative
BPL Srr
10 2 + 2
PC + rr -» PC
if V = 0
xx-xxxxx
Relative
BVC Srr
50 2 + 2
PC + rr ^ PC
if V = 1
xx-xxxxx
Relative
BVS $rr
70 2 + 2
Subroutine Instructions
PC + 2 -> S
aaaa -> PC
SP - 2 -» SP
xx-xxxxx
Absolute
JSR Saaaa
20 6 3
S (2 bytes)
-> PC
PC + 1 -> PC
SP + 2 -> SP
xx-xxxxx
Implied
RTS
60 6 1
Stack Instructions
A -> S
SP - 1 ^ SP
xx-xxxxx
Implied
PHA
48 3 1
S -* A
SP + 1 -> SP
Nx-xxxZx
Implied
PLA
68 4 1
PSR -> S
SP - 1 -> SP
xx-xxxxx
Implied
PHP
08 3 1
Microprocessor Instruction Set Tables 475
EXPANDED TABLE OF 6502 INSTRUCTIONS LISTED BY CATEGORY ( Continued)
Mne¬
monic
Operation
Boolean/Arith
Operation
Flags
NV-BDIZC
Address
Mode
Assembler
Notation
Op
~ #
PLP
PulL Processor
status register
from stack
S -> PSR
SP + 1 * SP
NV-BDIZC
Implied
PLP
28
4 1
TXS
Transfer X
register into
Stack pointer
X->SP
xx-xxxxx
Implied
TXS
9A
2 1
TSX
Transfer Stack
pointer into
X register
SP -> X
Nx-xxxZx
Implied
TSX
BA
2 1
Interrupt Instructions
RTI
ReTum from
Interrupt
S * PSR
SP + 1 -» SP
S (2 bytes)
*> PC
SP + 2 -» SP
NV-BDIZC
Implied
RTI
40
6 1
Input-Output Instructions
The 6502 memory-maps all
input and output rather than
using special instructions.
Notes
Address Modes
Assembler Notation
Immediate
Mnemonic #$dd
Absolute
Mnemonic Saaaa
Zero page
Mnemonic $aa
Accumulator
Mnemonic A
Implied
Mnemonic
Indxd Indct
Mnemonic ($ff,X)
Indct Indxd
Mnemonic ($aa),Y
Zero page,X
Mnemonic $ff,X
Absolute,X
Mnemonic $ffff,X
Absolute,Y
Mnemonic $ffff,Y
Relative
Mnemonic $rr
Indirect
Mnemonic ($aaaa)
Zero page,Y
Mnemonic $ff,Y
Abbreviations and Explanations
Indxd Indct = Indexed Indirect
Indct Indxd = Indirect Indexed
a = address (one hex digit)
d = data (one hex digit)
f = address offset (one hex digit) ($ff is an unsigned binary number
and is therefore positive)
r = relative address (one hex digit) ($rr is a 2’s-complement signed
binary number and can therefore be positive or negative)
* = add 1 cycle if page boundary crossed
+ = add 1 cycle if branch occurs; add 1 more cycle if branch crosses
page
( ) =the contents of the address within parentheses form the actual
address
7...0 = bits 0 through 7 of memory or the accumulator
M 7 , M 6 , etc. = Bits 7, 6, etc. of a memory location
L - low-order byte
H = high-order byte
PC = program counter
S = stack (contents of the top byte of the stack)
SP = stack pointer
PSR = processor status register (flags)
* = Add 1 cycle if crossing page boundary
Flags _
0 = flag always cleared
1 = flag always set
476 Microprocessor Instruction Set Tables
X = flag not affected
N = negative flag
V « overflow flag
B - break flag
D = decimal flag
I = interrupt flag
Z = zero flag
C = carry flag
Symbols in the Page Heading
~ = clock cycles
# = # of bytes used by instruction (and following address or data
if used)
Addressing Modes - Summary
zero since both of these are 8-bit numbers). The microprocessor then
gets the contents of this memory location and the following location
to form an other address where it will then find the data (operand).
Indct Indxd (Mnemonic ($aa),Y): This addressing mode is
sometimes confused with the one above though it does work
differently. First, the microprocessor goes to address $aa and the
address immediately following $aa. It uses the contents of these two
locations to form a 16-bit address to which the Y register is added.
This then forms the actual address where the operand is located.
Zero page,X (Mnemonic $ff,X): In this form of addressing the
number $ff is added to the X register to form a second address
where the operand is located. Because both $ff and X are 8-bit
binary numbers, the actual address must be in page zero. If the sum
of these two numbers exceeds $FF (the end of page zero), any carry
will be ignored and the address will "wrap around" to the beginning
of page zero.
Absolute^ (Mnemonic $fttf,X): In this case, the 16-bit number Sffff
is added to the X register to form the actual address. If this number
exceeds hexadecimal SFFFF, the carry is ignored and the address
"wraps around" to $0000 and continues from there.
Immediate (Mnemonic #$dd): The data to be operated on (#$dd)
is in the next byte of memory after the instruction itself. Therefore
no address is needed.
Absolute (Mnemonic $aaaa): The data to be operated on is found
in the memory location indicated ($aaaa). This is a 2-byte address
and can point to any place in the 6502’s 64K (65,536 byte) addressing
range.
Zero page (Mnemonic $aa): The data to be operated on is found
in the memory location indicated ($aa). This is a 1-byte address and
can point only to a place in page zero of memory. Page zero is
address S00-SFF (decimal 0-255).
Accumulator (Mnemonic A): These are instructions which use
implied addressing, where the data is already in the accumulator.
Implied (Mnemonic): These instructions indicate where the data is
or will be within the instruction itself.
Indxd Indct (Mnemonic ($ff^X)) : In this form of addressing, the
operand (the number which is going to have something done to it)
is found through a multistep process. First, the offset ($ff) is added
to the X register to form an address (this address must be in page
Absolute,Y (Mnemonic Sffff,Y): This address mode works the same
as Absolute,X except that the Y register is used instead.
Relative (Mnemonic $rr): $rr is a 2’s-complement signed binary
number; that is, it can be positive or negative. This number is added
to the current contents of the program counter to determine the
actual address. $rr is different from an offset (Sffff or $ff) because
it is not added to another register but directly to the program
counter itself. It directs the microprocessor relative to its current
place in memory.
Indirect (Mnemonic ($aaaa)): In this mode, the contents of address
Saaaa and the contents of the address immediately following it are
used to form the actual address where the operand is to be found.
(Only the JMP instruction uses this addressing mode.)
Zero page,Y (Mnemonic $ff,Y): This addressing mode is exactly like
the Zero page,X" mode except that register Y is used instead.
Microprocessor Instruction Set Tables
477
SHORT TABLE OF 6502 INSTRUCTIONS LISTED BY CATEGORY
Assembler
Notation
Op
Boolean/Arith
Operation
Flags
NV-BDIZC
Assembler
Notation
Op
Boolean/Arith
Operation
Flags
NV-BDIZC
CPU Control Instructions
TAY
A8
A -> Y
Nx-xxxZx
TYA
98
Y * A
Nx-xxxZx
NOP
EA
Nothing
xx-xxxxx
BRK
00
PC + 2 -* S
xx-lxlxx
Flap Instructions
SP - 2 -> SP
PSR ■» S
SP - 1 * S
CLC
18
0 + C
xx-xxxxO
SFFFE -» PC
CLD
D8
0 4 D
xx-xOxxx
Data Transfer Instructions
CLI
58
o->i
xx-xxOxx
CLV
B8
0 -» V
xO-xxxxx
LDA #$dd
A9
M + A
Nx-xxxZx
LDA $aaaa
AD
SEC
38
1 c
xx-xxxxl
LDA Saa
A5
LDA ($ff,X)
A1
SED
F8
1 -► D
xx-xlxxx
LDA ($aa),Y
B1
LDA $ff,X
B5
SEI
78
1 I
xx-xxlxx
LDA Sffff,X
BD
LDA Sffff.Y
B9
Arithmetic Instructions
LDX #$dd
A2
M -» X
Nx-xxxZx
LDX $aaaa
AE
LDX Saa
A6
ADC #Sdd
69
A + M + C -> A
NV-xxxZC
LDX Sffff.Y
BE
ADC Saaaa
6D
LDX $ff,Y
B6
ADC Saa
65
ADC (Sff.X)
61
LDY #$dd
AO
M *♦ Y
Nx-xxxZx
ADC (Saa),Y
71
LDY Saaaa
AC
ADC $ff,X
75
LDY Saa
A4
ADC $ffff,X
7D
LDY Sff.X
B4
ADC Sffff.Y
79
LDY Sffff.X
BC
SBC #$dd
E9
A - M -
NV-xxxZC
SBC Saaaa
ED
(1-C) ■* A
STA Saaaa
8D
A -> M
xx-xxxxx
SBC Saa
E5
STA Saa
85
SBC ($ff,X)
El
Note: (1-C) =
STA (Sff.X)
81
SBC ($aa),Y
FI
Borrow
STA ($aa),Y
91
SBC $ff t X
F5
STA $ff,X
95
SBC Sffff.X
FD
STA Sffff.X
9D
SBC Sffff.Y
F9
STA Sffff.Y
99
STX Saaaa
8E
X -> M
xx-xxxxx
Logical Instructions
STX Saa
86
STX $ff,Y
96
STY Saaaa
8C
Y -> M
xx-xxxxx
AND #$dd
29
A AND M -» A
Nx-xxxZx
STY Saa
84
AND Saaaa
2D
STY Sff.X
94
AND Saa
25
AND (Sff.X)
21
TAX
AA
A X
Nx-xxxZx
AND ($aa),Y
31
AND Sff.X
35
TXA
8A
X A
Nx-xxxZx
AND Sffff.X
3D
AND Sffff.Y
39
478 Microprocessor Instruction Set Tables
Assembler
Notation
Op
Boolean/A
Operation
EOR #$dd
49
A EOR M
EOR Saaaa
4D
EOR Saa
45
EOR ($ff,X)
41
EOR ($aa),Y
51
EOR $ff,X
55
EOR Sffff.X
5D
EOR Sffff.Y
59
ORA #$dd
09
A OR M -*
ORA Saaaa
OD
ORA $aa
05
ORA ($ff,X)
01
ORA ($aa),Y
11
ORA Sff.X
15
ORA $ffff,X
ID
ORA Sffff.Y
19
BIT Saaaa
2C
A AND M
BIT Saa
24
M 7 ■* N
m 6 *v
Flags
NV-BDIZC
Nx-xxxZx
Nx-xxxZx
76-xxxZx
Rotate and Shift Instructions
ASL Saaaa
0E
ASL Saa
06
ASL A
0A
ASL $ff,X
16
ASL $ffff,X
IE
LSR Saaaa
4E
LSR Saa
46
LSR A
4A
LSR $ff,X
56
LSR $ffff,X
5E
ROL Saaaa
2E
ROL Saa
26
ROL A
2A
ROL $ff,X
36
ROL $ffff,X
3E
ROR Saaaa
6E
ROR Saa
66
ROR A
6A
ROR $ff,X
76
ROR $ffff,X
7E
C <- 7...0 <- 0
0 -» 7...0 -» C
Nx-xxxZC
Ox-xxxZC
Nx-xxxZC
Nx-xxxZC
Increment and Decrement Instructions
INC Saaaa
EE
INC Saa
E6
INC Sff.X
F6
INC Sffff.X
FE
Nx-xxxZx
Assembler
Notation
Op
Boolean/Arith
Operation
Flags
NV-BDIZC
INX
E8
X + 1 -> x
Nx-xxxZx
INY
C8
Y + 1 -» Y
Nx-xxxZx
DEC Saaaa
CE
M - 1 -* M
Nx-xxxZx
DEC Saa
C6
DEC $ff,X
D6
DEC $ffff,X
DE
DEX
CA
X- 1 •» X
Nx-xxxZx
DEY
88
Y - 1 ■» Y
Nx-xxxZx
Unconditional Jump Instructions
JMP Saaaa
4C
aaaa -> PC
(abs addressing}
xx-xxxxx
JMP (Saaaa)
6C
(aaaa) -> PC L
(aaaa + 1) * PC^
(indirect addressing}
Test (Co mpare) Instructions
CMP #$dd
C9
A-M
Nx-xxxZC
CMP Saaaa
CD
CMP Saa
C5
CMP (Sff.X)
Cl
CMP ($aa),Y
D1
CMP Sff.X
D5
CMP Sffff.X
DD
CMP Sffff.Y
D9
CPX #$dd
E0
X - M
Nx-xxxZC
CPX Saaaa
EC
CPX Saa
E4
CPY #$dd
CO
Y - M
Nx-xxxZC
CPY Saaaa
cc
CPY Saa
C4
Conditi onal Jump (Branch) Instructions
BCC Srr
90
PC + rr -» PC
if C = 0
xx-xxxxx
BCS Srr
B0
PC + rr -» PC
if C=1
xx-xxxxx
BEQ Srr
P0
PC + rr -» PC
if Z=1
xx-xxxxx
Microprocessor Instruction Set Tables 470
Assembler
Notation
BNE Srr
BMI Srr
BPL Srr
BVC Srr
BVS Srr
JSR Saaaa
SHORT TABLE OF 6502 INSTRUCTIONS LISTED BY CATEGORY (i Continued)
Op Boolean/Arith Flags Assembler Op Boolean/Arith
Operation _NV-BDIZC Notation _ Operation _
DO PC + rr * PC
if Z=0
30 PC + rr -> PC
if N = 1
10 PC + rr -> PC
if N = 0
50 PC + rr -> PC
if V = 0
70 PC + rr ^ PC
if V = 1
Subroutine Instructions
20 PC + 2 -> S
aaaa *♦ PC
SP - 2 *» SP
60 S (2 bytes)
■* PC
PC + 1 + PC
SP + 2 -> SP
Flags
NV-BDIZC
Assembler
Notation
Op
Boolean/Arith
Operation
Flags
NV-BDIZC
xx-xxxxx
PLA
68
S-> A
SP + 1 -> SP
Nx-xxxZx
xx-xxxxx
PHP
08
PSR -* S
SP - 1 ^ SP
xx-xxxxx
xx-xxxxx
PLP
28
S -* PSR
SP + 1^ SP
NV-BDIZC
xx-xxxxx
TXS
9A
X -> SP
xx-xxxxx
TSX
BA
SP -> X
Nx-xxxZx
Interrupt Instructions
40 s ■+ PSR
SP + l + SP
S (2 bytes)
-► PC
SP + 2 -> SP
Input-Output Instructions
NV-BDIZC
Stack Instructions
48 A -> S
SP - 1 + SP
CONDENSED TABLE OF 6502 INSTRUCTIONS LISTED BY CATEGORY
CPU Control
LDX #$dd
A2
Instructions
LDX Saaaa
AE
LDX $aa
A6
NOP
EA
LDX $ffff,Y
BE
BRK
00
LDX $ff,Y
B6
Data Transfer
LDY #$dd
A0
Instructions
LDY Saaaa
AC
LDY Saa
A4
LDA #$dd
A9
LDY $ff,X
B4
LDA Saaaa
AD
LDY $ffff,X
BC
LDA $aa
A5
LDA ($ff,X)
A1
STA Saaaa
8D
LDA ($aa),Y
B1
ST A $aa
85
LDA Sff.X
B5
STA ($ff,X)
81
LDA $ffff,X
BD
STA (Saa),Y
91
LDA Sffff.Y
B9
STA $ff,X
95
STA $ffff,X
9D
Flae Instructions
STA Sffff.Y
99
CLC
18
STX Saaaa
8E
CLD
D8
STX Saa
86
CLI
58
STX $ff,Y
96
CLV
B8
SEC
38
STY Saaaa
8C
SED
F8
STY Saa
84
SEI
78
STY $ff,X
94
Arithmetic
TAX
AA
Instructions
TXA
8A
ADC #$dd
69
TAY
A8
ADC Saaaa
6D
TYA
98
ADC Saa
65
ADC ($ff,X)
61
480 Microprocessor Instruction Set Tables
CONDENSED TABLE OF 6502 INSTRUCTIONS LISTED BY CATEGORY
0 Continued )
ADC (Saa),Y
ADC $ff,X
ADC Sffff.X
ADC $ffff,Y
SBC #$dd
SBC Saaaa
SBC $aa
SBC ($ff,X)
SBC ($aa),Y
SBC $ff,X
SBC Sffff.X
SBC $ffff,Y
Logical
Instructions
AND
AND
AND
AND
AND
AND
AND
AND
#$dd
Saaaa
$aa
(Sff,X)
($aa),Y
$ff,X
Sffff.x
$ffff,Y
EOR #$dd
EOR Saaaa
EOR Saa
EOR ($ff,X)
EOR ($aa),Y
EOR $ff,X
EOR $ffff,X
EOR Sffff.Y
ORA #$dd
ORA Saaaa
ORA $aa
ORA ($ff,X)
ORA ($aa),Y
ORA $ff,X
71
75
7D
79
E9
ED
E5
El
FI
F5
FD
F9
29
2D
25
21
31
35
3D
39
49
4D
45
41
51
55
5D
59
09
0D
05
01
11
15
ORA $ffff,X
ID
INX
E8
BEQ $rr
F0
ORA Sffff.Y
19
INY
C8
BNE Srr
DO
BIT Saaaa
2C
DEC Saaaa
CE
BMI Srr
30
BIT Saa
24
DEC Saa
C6
BPL Srr
10
BVC Srr
50
DEC $ff,X
D6
Rotate and Shift
DEC Sffff.X
DE
BVS $rr
70
Instructions
DEX
CA
Subroutine
ASL Saaaa
0E
JDc Y
88
Instructions
ASL Saa
06
Unconditional
ASL A
0A
Jump Instructions
JSR Saaaa
20
ASL Sff.X
16
RTS
60
ASL Sffff.X
IE
JMP Saaaa
4C
LSR Saaaa
4E
JMP (Saaaa)
6C
Instructions
LSR Saa
46
Test (Compare)
LSR A
4A
Instructions
PHA
48
LSR $ff,X
56
PLA
68
LSR Sffff.X
5E
CMP #$dd
C9
PHP
08
CMP Saaaa
CD
PLP
28
ROL Saaaa
2E
CMP Saa
C5
TXS
9A
ROL Saa
26
CMP ($ff,X)
Cl
TSX
BA
ROL A
2A
CMP ($aa),Y
D1
ROL $ff,X
36
CMP $ff,X
D5
Interrupt
ROL $ffff,X
3E
CMP $ffff,X
DD
Instructions
CMP $ffff,Y
D9
ROR Saaaa
6E
RTI
40
ROR Saa
66
CPX #$dd
E0
ROR A
6A
CPX Saaaa
EC
Input-Output
ROR $ff,X
76
CPX Saa
E4
Instructions
ROR $ffff,X
7E
CPY #$dd
CO
None
Increment and
CPY Saaaa
cc
Decrement
CPY Saa
C4
Instructions
Conditional Jump
INC Saaaa
EE
(Branch)
INC Saa
E6
Instructions
INC $ff,X
F6
INC $ffff,X
FE
BCC $jt
90
BCS Srr
B0
CONDENSED TABLE OF 6502 INSTRUCTIONS LISTED ALPHABETICALLY
ADC ($aa),Y
71
AND $ffff,Y
39
ADC ($ff,X)
61
AND $ff,X
35
ADC Saa
65
AND #$dd
29
ADC Saaaa
6D
ASL Saa
06
ADC Sffff.X
7D
ASL Saaaa
0E
ADC Sffff.Y
79
ASL $ffff,X
IE
ADC Sff.X
75
ASL $ff,X
16
ADC #$dd
69
ASL A
0A
AND ($aa),Y
31
BCC Srr
90
AND (Sff.X)
21
BCS Srr
B0
AND Saa
25
BEQ Srr
F0
AND Saaaa
2D
BIT Saa
24
AND Sffff.X
3D
BIT Saaaa
2C
BMI Srr
30
CMP Saaaa
CD
BNE $rr
DO
CMP $ffff,X
DD
BPL Srr
10
CMP $ffff,Y
D9
BRK
00
CMP $ff,X
D5
BVC Srr
50
CMP #$dd
C9
BVS Srr
70
CPX Saa
E4
CLC
18
CPX Saaaa
EC
CLD
D8
CPX #$dd
E0
CLI
58
CPY Saa
C4
CLV
B8
CPY Saaaa
CC
CMP ($aa),Y
D1
CPY #Sdd
CO
CMP ($ff,X)
Cl
DEC Saa
C6
CMP Saa
C5
DEC Saaaa
CE
Microprocessor Instruction Set Tables
481
CONDENSED TABLE OF 6502 INSTRUCTIONS LISTED ALPHABETICALLY ( Continued)
DEC Sffff,X
DE
LDA Sffff,X
BD
DEC $ff,X
D6
LDA Sffff.Y
B9
DEX
CA
LDA $ff,X
B5
DEY
88
LDA #Sdd
A9
EOR (Saa).Y
51
LDX Saa
A6
EOR (Sff.X)
41
LDX Saaaa
AE
EOR $aa
45
LDX Sffff.Y
BE
EOR Saaaa
4D
LDX $ff,Y
B6
EOR Sffff.X
5D
LDX #$dd
A2
EOR $ffff,Y
59
LDY Saa
A4
EOR $ff,X
55
LDY Saaaa
AC
EOR #Sdd
49
LDY Sffff.X
BC
INC $aa
E6
LDY Sff.X
B4
INC Saaaa
EE
LDY #$dd
AO
INC $ffff,X
FE
LSR Saa
46
INC Sff.X
F6
LSR Saaaa
4E
INX
E8
LSR Sffff.X
5E
INY
C8
LSR Sff.X
56
JMP (Saaaa)
6C
LSR A
4A
JMP Saaaa
4C
NOP
EA
JSR Saaaa
20
ORA (Saa),Y
11
LDA (Saa).Y
B1
ORA (Sff.X)
01
LDA (Sff.X)
A1
ORA Saa
05
LDA Saa
A5
ORA Saaaa
0D
LDA Saaaa
AD
ORA Sffff.X
ID
ORA Sffff.Y
19
SBC $ff,X
F5
ORA Sff.X
15
SBC #$dd
E9
ORA #$dd
09
SEC
38
PHA
48
SED
F8
PHP
08
SEI
78
PLA
68
STA ($aa),Y
91
PLP
28
STA (Sff.X)
81
ROL Saa
26
STA Saa
85
ROL Saaaa
2E
STA Saaaa
8D
ROL Sffff.X
3E
STA Sffff.X
9D
ROL Sff,X
36
STA Sffff.Y
99
ROL A
2A
STA $ff,X
95
ROR $aa
66
STX Saa
86
ROR Saaaa
6E
STX Saaaa
8E
ROR Sffff.X
7E
STX $ff,Y
96
ROR $ff,X
76
STY Saa
84
ROR A
6A
STY Saaaa
8C
RTI
40
STY $ff,X
94
RTS
60
TAX
AA
SBC ($aa),Y
FI
TAY
A8
SBC (Sff.X)
El
TSX
BA
SBC Saa
E5
TXA
8A
SBC Saaaa
ED
TXS
9A
SBC Sffff.X
FD
TYA
98
SBC Sffff,Y
F9
CONDENSED TABLE OF 6502 INSTRUCTIONS LISTED BY OP CODE
00
BRK
31
AND (Saa).Y
01
ORA (Sff.X)
35
AND $ff,X
05
ORA Saa
36
ROL Sff.X
06
ASL Saa
38
SEC
08
PHP
39
AND Sffff.Y
09
ORA #$dd
3D
AND Sffff.X
0A
ASL A
3E
ROL Sffff.X
0D
ORA Saaaa
40
RTI
0E
ASL Saaaa
41
EOR (Sff.X)
10
BPL Srr
45
EOR Saa
11
ORA ($aa),Y
46
LSR Saa
15
ORA $ff,X
48
PHA
16
ASL $ff,X
49
EOR #$dd
18
CLC
4A
LSR A
19
ORA $ffff,Y
4C
JMP Saaaa
ID
ORA $ffff,X
4D
EOR Saaaa
IE
ASL $ffff,X
4E
LSR Saaaa
20
JSR Saaaa
50
BVC Srr
21
AND ($ff,X)
51
EOR ($aa),Y
24
BIT Saa
55
EOR Sff.X
25
AND Saa
56
LSR Sff.X
26
ROL Saa
58
CLI
28
PLP
59
EOR Sffff.Y
29
AND #$dd
5D
EOR $ffff,X
2A
ROL A
5E
LSR Sffff.X
2C
BIT Saaaa
60
RTS
2D
AND Saaaa
61
ADC (Sff.X)
2E
ROL Saaaa
65
ADC Saa
30
BMI Srr
66
ROR $aa
68
PLA
99
STA Sffff.Y
69
ADC #$dd
9A
TXS
6A
ROR A
9D
STA $ffff,X
6C
JMP (Saaaa)
A0
LDY #$dd
6D
ADC Saaaa
A1
LDA ($ff,X)
6E
ROR Saaaa
A2
LDX #$dd
70
BVS Srr
A4
LDY Saa
71
ADC ($aa),Y
A5
LDA Saa
75
ADC Sff.X
A6
LDX Saa
76
ROR Sff.X
A8
TAY
78
SEI
A9
LDA #$dd
79
ADC Sffff.Y
AA
TAX
7D
ADC Sffff.X
AC
LDY Saaaa
7E
ROR $ffff,X
AD
LDA Saaaa
81
STA (Sff.X)
AE
LDX Saaaa
84
STY Saa
B0
BCS Srr
85
STA Saa
B1
LDA ($aa),Y
86
STX Saa
B4
LDY $ff,X
88
DEY
B5
LDA $ff.X
8A
TXA
B6
LDX $ff,Y
8C
STY Saaaa
B8
CLV
8D
STA Saaaa
B9
LDA Sffff.Y
8E
STX Saaaa
BA
TSX
90
BCC Srr
BC
LDY Sffff.X
91
STA ($aa),Y
BD
LDA $ffff,X
94
sty $ff,x
BE
LDX Sffff.Y
95
STA Sff.X
CO
CPY #$dd
96
STX $ff,Y
Cl
CMP (Sff.X)
98
TYA
C4
CPY Saa
482 Microprocessor Instruction Set Tables
£ Q 8 a Q
CONDENSED TABLE OF 6502 INSTRUCTIONS LISTED BY OP CODE (Continued)
CMP $aa
DEC $aa
INY
CMP #$dd
DEX
CC CPY $aaaa
CD CMP Saaaa
CE DEC Saaaa
DO BNE Srr
D1 CMP ($aa),Y
D5 CMP $ff,X
D6 DEC $ff,X
D8 CLD
D9 CMP Sffff.Y
DD CMP Sffff,X
DE DEC Sffff.X
E0 CPX #$dd
El SBC ($ff,X)
E4 CPX $aa
E5 SBC $aa
E6 INC $aa
E8 INX
E9 SBC #$dd
EA NOP
EC CPX Saaaa
ED SBC Saaaa
EE INC Saaaa
F0 BEQ Srr
FI SBC ($aa),Y
F5 SBC $ff,X
F6 INC $ff,X
F8 SED
F9 SBC $ffff,Y
FD SBC $ffff,X
FE INC Sffff.X
Microprocessor Instruction Set Tables 483
Appendixes
APPENDIX 1. THE ANALOG INTERFACE
The data in a microprocessor is in digital form. This differs
from the outside world where data is in analog (continuous)
form. To get digital data, we need to use an analog-to-
digital <A/D) converter; it will convert analog voltage or
current into an equivalent digital word.
Conversely, after a CPU has processed data, it is often
necessary to convert the digital answer into an analog
voltage or current. This conversion requires a digital-to-
analog (D/A) converter.
The analog interface is the boundary where digital and
analog meet, where the microcomputer connects to the
outside world. At this interface, we find either an A/D
converter (input side) or a D/A converter (output side).
This chapter discusses some of the hardware and software
found at the analog interface.
A1-1 OP-AMP BASICS
Let us briefly review the operational amplifier (op amp)
because this device is used with D/A and A/D converters.
We will zero in on the key features that make the op amp
useful at the analog interface.
input voltage may be treated as 0 V. Furthermore, the input
impedance of the inverting input approaches infinity (some¬
times FETs are used for the input stage, as in B1FET op
amps). These key features, zero input voltage and infinite
input impedance, make the inverting input a virtual ground
point .
How is a virtual ground different from an ordinary
ground? An ordinary ground has zero voltage while sinking
any amount of current. A virtual ground, however, is a
ground for voltage but not for current; it has zero voltage
but can sink no current. In the discussion that follows, we
will approximate the inverting input of an op amp as a
virtual ground point: this means zero voltage and zero
current.
/ /
Fig. Al-1 Operational amplifier.
Virtual Ground
Figure Al l shows the symbol for an op amp. V OUT is the
output voltage with respect to ground. A is the open-loop
voltage gain of the op amp, often more than 100,000. When
connected as an inverter, the noninverting input (+ input)
is grounded. The inverting input (- input) receives the
signal voltage.
Because the voltage gain of an op amp is so large, the
input voltage is in microvolts. To a first approximation, the
2.5 kC2 i kn
Output Voltage and Current
Figure Al-2a shows an inverting op amp with input and
output resistors. V, N is the input voltage with respect to
ground, and V OLT is the output voltage with respect to
ground. Because of the high gain and input impedance, we
can approximate the inverting input as a virtual ground
point. Therefore, all the input voltage appears across the
input resistor, which means that the input current is
J= Vl N
^IN
(All)
Summing Circuit
Figure A1-3 is an op-amp circuit whose output current is
the sum of the input currents. Here is the proof. Because
of the virtual ground point, each input voltage appears
across its resistor. This means that the input currents are
Since none of the input current can enter the virtual
ground point, it must pass through the output resistor. In
other words, the output current equals the input current.
And the output voltage is
h
Ry
h
T.
Rx
/« =
*0
Kirchhoff’s current law gives a total input current of
Tout ~ ^out (A 1-2)
The minus sign indicates phase inversion. If the input
voltage is positive, the output voltage is negative.
As an example of calculating input current and output
voltage, look at Fig. A1-2/?. The input current is
/ — h + h + /| + A)
Again, the virtual ground guarantees that all this input
current goes through the output resistor. As before,
Tqut ~ — ^out
5 V
2.5 kO
2 mA
The output voltage is
Tout ~ — 2 mA X 1 kfl = — 2 V
v 3 i/, v Q
A1-2 A BASIC D/A CONVERTER
The op-amp summing circuit can be used to build a D/A
converter by selecting input resistors that are weighted in
binary progression. Figure A1-4 gives you the idea. V REH
is an accurate reference voltage, and the resistors are
precision resistors to get accurate input currents. The
switches can be open or closed. When all switches are
open, all input currents are zero and the output current is
zero.
All Bits High
When all switches are closed, the input currents are
h
Treh
R
I 2
Tree
2 R
/.
= Tret-
8 R
Fig. A1-4 D/A conversion with binary-weighted resistors.
486 Appendixes
The output current with all switches closed is the
all input currents and equals
I = + 0.5 + 0.25 + 0.125)
sum of
(A 1 -3)
TABLE AM. WEIGHTE1
d 3 d 2 d, d 0
D D/A CONVERTER
Output
current, Fraction of
mA maximum
V'ref
/ = 1.875-^g
0
0
0
0
0
0
R
0
0
0
1
0.125
1
15
0
0
1
0
0.25
2
15
By opening and closing switches we can produce 16 different
0
0
1
1
0.375
3
15
output currents from 0 to 1.875V REF //?.
0
1
0
0
0.5
4
15
0
1
0
1
0.625
5
1 5
Any Digital Input
0
0
1
1
1
1
0
1
0.75
0.875
(J
15
1 5
If 0 stands for an open switch and 1 for a closed
switch.
1
0
0
0
1
8
'15
we can rewrite Eq. A1-3 as
1
0
0
1
1.125
f)
15
1
0
1
0
1.25
10
/ = + 0.5 D 2 + 0.25 D, + 0.125D„)
R
(A 1-4)
1
1
0
1
1
0
1
0
1.375
1.5
1 1
1 5
12
15
1
1
0
1
1.625
13
15
In powers of 2,
1
1
1
0
1.75
1-1
15
1
1
1
1
1.875
15
15
/ = _^(D, + 2-'D : + 2 “-D, + 2-'D 0 ) (Al-5)
R
This says that the output current is the sum of binary-
weighted input currents. In other words, we have a D/A
converter. For instance, suppose V REF = 5 V and R = 5
kfi. Then the total output current varies from 0 to 1.875
mA, as shown in Table A1-1.
Current Switches
Figure Al-5 shows how we can transistorize the switching.
Data bits D 3 through D {) drive the bases of the transistors
through the current-limiting resistors. When a bit is high,
it produces enough base current to saturate its transistor.
When a bit is low, the transistor is cut off. Since each
transistor is saturated or cut off, it acts like a closed or
open switch. (Base resistance is not critical; it need only
be less than collector resistance multiplied by (3 dc .)
If the lower 4 bits of an output port are connected to D }
to Z) 0 , the circuit of Fig. Al-5 will convert digital data to
analog current. For instance, assume port 22H has been
programmed as an output port in a minimum system. If the
lower 4 bits of port 22H are connected to D 3 to D {) , this
program segment will operate the D/A converter:
Label
Mnemonic
Comment
MVI A,FFH
initialize accumulator
LOOP:
INR A
;Count up
OUT 22H
;Output nibble
JMPLOOP
;Get next nibble
O3 Z?2 ^1 °0
Fig. Al-5 Transistor switches for D/A converter.
Appendixes 48 7
Maximum
(b)
Fig. Al-6 (a) Staircase output current; ( b) each step equals an
LSB increment.
The first INR A produces accumulator contents of 00H.
Subsequent INR executions produce 01H, 02H, . . . , OFH,
10H, 11H.1FH, 20H, 21H.FFH. As far as
D 3 to D 0 are concerned, they see a nibble stream of 0000,
0001,0010, 0011, ...,1111,0000, 0001, and so on.
Figure Al-6 a illustrates how the output current of the
D/A converter appears. As each input nibble is latched into
port 22H, the output current moves one step higher until
reaching the maximum current. Then the cycle repeats. If
all resistors are exact and all transistors matched, all steps
are identical in size.
Resolution
In the perfect staircase of Fig. Al-6 b a step is called an
LSB increment because it is produced by a change in the
LSB. One way to measure the quality of a D/A converter
is its resolution , the ratio of the LSB increment to the
maximum output. As a formula.
Resolution = —-— (Al-6)
2 n - 1
For instance, a 4-bit D/A converter has a resolution of
Resolution =-= —
2 4 — 1 15
This is sometimes read as 1 part in 15.
The number of different steps an /7-bit converter produces
is
Steps = 2" - 1 (A 1 -6a)
Therefore, an alternative way to think of resolution is
Resolution = —!— (Al-6 b)
steps
Percent resolution is given by
Percent resolution = resolution x 100% (A 1-7)
If the resolution is 1 part in 15, then
Percent resolution = x 100% = 6.67%
The greater the number of bits, the better the resolution.
With Eqs. Al-6 and A1-7 we can calculate the resolution
and percent resolution for more bits. Table A1-2 is a
summary of the resolution for converters with 4 to 18 bits.
Because the number of bits determines the resolution in
Eq. Al-6, an indirect way to specify resolution is by stating
the number of bits. For instance, an 8-bit converter has 8-
bit resolution, a 10-bit converter has 10-bit resolution, and
so on. This is a quick and easy way to pin down the
resolution. When necessary, Eqs. Al-6, Al-6 a, and A1-7
can give additional information.
Accuracy
In a D/A converter, absolute accuracy refers to how close
each output current is to its ideal value. In Fig. A1-5
absolute accuracy depends on the reference voltage, resistor
tolerance, transistor mismatch, and so forth. In a typical
application, a trimmer adjustment is included to set the
full-scale output at a preassigned value.
Relative accuracy refers to how close each output level
is to its ideal fraction of full-scale output. With a 4-bit
TABLE Al-2. RESOLUTION
Bits
Resolution
Percent
4
1 part in 15
6.67
6
1 part in 63
1.59
8
1 part in 255
0.392
10
1 part in 1,023
0.0978
12
1 part in 4,095
0.0244
14
1 part in 16,383
0.0061
16
1 part in 65,535
0.00153
18
1 part in 262,143
0.000381
488 Appendixes
converter, the ideal output levels as a fraction of full-scale
should be 0, A, A, fk, and so on. Because data sheets
specify relative accuracy rather than absolute accuracy, our
subsequent discussions will emphasize relative accuracy.
Relative accuracy depends mainly on the tolerance of the
weighted resistors in Fig. A1-5. If they are exactly /?, 2R,
4/?, and 8/?, all steps equal 1 LSB increment in Fig. Al¬
ba. When the resistors depart from ideal values, the steps
may be larger or smaller than 1 LSB increment.
Error = 1 LSB
(b)
Fig. Al-7 Error specified in LSB increments.
Errors are specified in terms of LSB increments. For
instance, Fig. Al-7a shows an error of 1 LSB; the actual
output (solid line) differs from the ideal output (dashed
line) by 1 LSB increment. If a negative error follows a
positive error, the staircase can fall as shown in Fig. Al-
1b. Here you see an error of + 1 LSB followed by an error
of - 1 LSB.
Monotonicity
A monotonic D/A converter is one that produces an increase
in output current for each successive digital input. The
staircases of Fig. Al-7a and b are not monotonic because
they do not produce an increase for each digital input.
Figure Al-7a is almost monotonic, but Fig. A1-7Z? is far
from monotonic. Monotonicity is the least we can expect
from a D/A converter because it only makes sense; the
output should increase when the input does.
For a D/A converter to be monotonic the error must be
less than ±i LSB at each output level. Why? Because in
Fig. Al-8 Critical level for monotonicity.
the worst case, a +£-LSB error followed by a — i-LSB
error produces the critical level where monotonicity is about
to be lost. Figure Al-8 illustrates this critical case, an error
of LSB followed by an error of — | LSB. If the error
of a converter is less than LSB for each output level,
we are guaranteed a rising current for each successive
digital input. Almost all commercially available D/A con¬
verters are monotonic because they have an accuracy of
better than ±i LSB at each output level.
Settling Time
After you apply a digital input, it takes a D/A converter
anywhere from nanoseconds to microseconds to produce
the correct output. Settling time is defined as the time it
takes for the converter output to stabilize to within \ LSB
of its final value. This time depends on the stray capacitance,
saturation delay time, and other factors. Settling time is
important because it places a limit on how fast you can
change the digital inputs.
Disadvantages of Weighted Resistors
For a weighted-resistor circuit to be monotonic the tolerance
of the resistors must be less than the percent resolution.
For instance, if the resolution is r* (6.67 percent), resistors
with a tolerance of less than ±6.67 percent will produce a
monotonic staircase. If the resolution is 2 W (about 0.4
percent), the resistors need a tolerance of better than ±0.4
percent for a monotonic output. As you see, 4 bits are no
problem, but 8 bits are.
Another difficulty arises with weighted resistors. As the
number of bits increases, the range of resistance values gets
awkward. For 8 bits, we need resistances of /?, 2/?, 4/?,
. . . , 128/?. The largest resistance is 128 times the smallest.
For a 12-bit converter, the largest resistance needs to be
2,048 times the smallest. Because of the tolerance and
range problems, mass production of weighted-resistor D/A
converters is impractical.
Appendixes 489
A1-3 THE LADDER METHOD
One way to get around the problems of a binary-weighted
resistors is to use a ladder circuit. Figure A1-9 a is an
example of the R-2R ladder commonly used in integrated
D/A converters. Only two resistance values are needed; this
eliminates the range problem. Furthermore, since the resis¬
tors are on the same chip, they have almost identical
characteristics; this minimizes the tolerance problem. In
other words, as the number of bits increases, an integrated
ladder can divide the current much more accurately than a
binary-weighted circuit.
Ladder Properties
An R-2R ladder does something interesting to the impedance
at different points in the circuit. To begin with, the two
resistors at node D in Fig. A1-9 a are in parallel and may
be reduced to an equivalent resistance /?, shown in Fig.
A1-9 b. Now, to the right of node C we have R in series
with /?, a total of 2R. Since node C has 2 R is in parallel
with 2R, the circuit reduces to Fig. Al-9r.
Looking into the left side of node B (Fig. Al-9e), we
see 2 R in parallel with 2 R. Therefore, the circuit reduces
to Fig. A1-9 d. Again, 2 R is in parallel with 2/?, so the
circuit reduces to the single R shown in Fig. A1-9^.
Figure A1-10 summarizes ladder impedances. Do you
see the point? Looking into the left side of a node, we
always see an equivalent resistance of R. Just to the right
of each node, we always see a resistance of 2 R. This
impedance phenomenon is the key to analyzing modern D/
A converters because they use the ladders instead of
weighted resistors.
Binary Division of Current
Figure A1-11 shows how a ladder can divide the current
into binary levels. The typical D/A converter has a reference
current set by the user. In this example, the reference
current is 2 mA. The bottom of each 2 R resistor is grounded
in either switch position. When a switch is to the right, the
current through a 2 R resistor flows to the upper ground.
When a switch is to the left, the lower ground sinks the
current. With all the switches to the right, as shown in Fig.
A1-11, / OUT is zero.
Here is how the ladder divides the 2 mA of reference
current. Just to the right of node A we see an equivalent
resistance of 2 R. Therefore, the 2 mA of input current
divides equally at node A. Similarly, at node B we see 2 R
in parallel with 2 R\ again, the current divides equally into
0.5-mA branch currents. This process continues through
the ladder, so that we wind up with the upper grounds
sinking 1, 0.5, 0.25, and 0.125 mA.
Other Switch Positions
When we move the switches, we do not change the way
the current divides at the nodes, it still divides equally at
each node. But when a switch is to the left, it steers the
Fig. AMO Ladder impedances.
490 Appendixes
4 R B R C R D
Fig. Al-11 D/A conversion with R-2R ladder.
current into the lower ground. Bits to D 0 control the
transistorized switches. From previous discussions, we can
see that
/out = (Dj + 2-'D 2 + 2~ 2 £>| + 2-^D 0 )~ (AI-8)
Therefore, the output current of a 4-bit ladder is from 0 to
ISir
16 /ref-
More Bits
the ladder remain constant; all that changes are the ground
points. Constant current implies constant voltage, which
means that stray capacitance in the ladder has little effect.
In other words, we do not get the usual exponential charge
and discharge associated with a change in voltage. This
reduces the settling time. For this reason, IC converters
often use the current-steering approach shown in Fig.
Al-11.
A1-4 THE COUNTER METHOD OF
A/D CONVERSION
A similar analysis applies to longer ladders. The output
current is
/out = (0„-1 + 2+ • • • + 2'-"D 0 )^p (A 1 -9)
For instance, an 8-bit ladder produces a maximum output
current of M/ref- The LSB increment is 2 ib/ RKF .
Figure A1 -12 shows the simplest but least used method of
A/D conversion. V 1N is the analog input voltage. D 1 to D 0
are the digital output. The digital output drives a D/A
converter, which produces an analog output F oux . When
COUNT is high, the counter counts upward. When COUNT
is low, the counter stops. For convenience, an 8-bit D/A
converter and 8-bit counter are used, but the idea applies
to any number of bits.
Why Steer Current Operation
Current steering may seem more complicated than neces- The A/D conversion takes place as follows. First, the
sary, but there is good reason for it. The currents throughout START pulse goes low, clearing the counter. When the
Comparator
Appendixes 491
START pulse returns high, the counter is ready to go.
Initially, V OLl is zero; therefore, the op amp has a high
output and COUNT is high. The counter starts counting
upward from zero. Since the output of the counter drives a
D/A converter, the converter output is a positive voltage
staircase. As long as V lN is greater than V OUT , the op amp
has a positive output, COUNT remains high, and the
staircase voltage keeps rising.
At some point along the staircase, the next step makes
V 0 ut greater than V w . This forces COUNT to go low, and
the counter stops. Now, the digital output D 7 to D 0 is the
digital equivalent of the analog input. The negative-going
edge of the COUNT signal is used as an end-of-conversion
signal; this tells other circuits that the A/D conversion is
finished.
If the analog input V ]N is changed, external circuits must
send another START pulse to start the conversion. This
clears the count and a new cycle begins. When the digital
data is ready, the end-of-conversion signal has a falling
edge.
Disadvantage
The main disadvantage of the counter method is its slow
speed. In the worst case (maximum analog input) the
counter has to reach the maximum count before the staircase
voltage is greater than the analog input. For an 8-bit
converter, this means a conversion time of 255 clock
periods. For a 12-bit converter, the conversion time is 4,095
clock periods.
before, the output of a D/A converter drives the inverting
input of an op-amp comparator. The difference, however,
is in how the SAR register converges on the digital
equivalent. (SAR stands for successive-approximation reg¬
ister.) When the conversion is finished, the digital equivalent
is transferred to the output buffer register.
MSB First
When the start-of-conversion signal goes low, the SAR
register is cleared and V OUT drops to zero. When the start-
of-conversion signal goes high, the conversion begins.
Instead of counting up 1 bit at a time, the successive-
approximation method starts by setting the MSB. In other
words, during the first clock pulse the control circuit loads
a high MSB into the SAR register, whose output then equals
1000 0000
As soon as this digital output appears, F 0 ut jumps to Ml
times full-scale. If this is more than V IN , the negative output
of the comparator signals the control circuit to reset the
MSB. On the other hand, if V OUT is less than V 1N , the
positive output of the comparator indicates that the MSB
is to remain set. In some designs, setting and testing the
MSB take place during the first clock pulse following the
start of conversion. In other designs, several clock pulses
may be needed to set the MSB, test it, and reset it if
necessary.
A1-5 SUCCESSIVE APPROXIMATION
Remaining Bits
The most widely used approach in A/D conversion is the Let us assume that the MSB was not reset. The SAR register
successive-approximation method (see Fig. A I-13). As contents are now 1000 0000. The next clock pulse will set
Comparator
D-j Dq i D4 Og Og D -| D o
Start of conversion
CLK
End of conversion
Fig. Al-13 A/D conversion by successive approximation.
492 Appendixes
D 6 , giving a digital output of
1100 0000
V 0 ut now steps to Mi times full-scale. If V OUT is greater
than V lN , the negative op-amp output causes D b to reset. If
V 0UT is less than V IN , D 6 remains set.
During the remaining clock pulses, successive bits are
set and tested. Whenever a bit causes V OUT to exceed V IN ,
the bit is reset. In this way, all bits are set, tested, and
reset if necessary. With the fastest circuits, the conversion
is finished after eight clock pulses, and the D/A output is
the analog equivalent of the register contents. Slower designs
take longer because more clock pulses are needed to set,
test, and possibly reset each bit.
Output Buffer
When the conversion is finished, the control circuit sends
out a low end-of-conversion signal. The falling edge of this
signal loads the digital equivalent into the buffer register.
In this way, the digital output will remain even though we
start a new conversion cycle.
Advantage
The main advantage of the successive-approximation method
is speed. At best, it takes only n clock pulses to produce
n-b\t resolution of the analog signal. This is a big improve¬
ment over the counter method. Even with slower designs,
the successive-approximation method is still considerably
better than the counter method.
Appendixes
493
APPENDIX 2. BINARY-HEXADECIMAL-DECIMAL EQUIVALENTS
Binary
Hexadecimal
UB Decimal
LB Decimal
Binary
Hexadecimal
UB Decimal
LB Decimal
0000 0000
00
0
0
0011 0000
30
12,288
48
0000 0001
01
256
1
0011 0001
31
12,544
49
0000 0010
02
512
2
0011 0010
32
12,800
50
0000 0011
03
768
3
0000 0100
04
1,024
4
0011 0011
33
13,056
51
0000 0101
05
1.280
5
0011 0100
34
13,312
52
0000 0110
06
1,536
6
0011 0101
35
13,568
53
0000 0111
07
1,792
7
0011 0110
36
13,824
54
0000 1000
08
2,048
8
0011 0111
37
14,080
55
0000 1001
09
2,304
9
0011 1000
38
14,336
56
0000 1010
0A
2,560
10
0011 1001
39
14,592
57
0011 1010
3A
14,848
58
0011 1011
3B
15,104
59
0000 1011
OB
2,816
11
0011 1100
3C
15,360
60
0000 1100
oc
3,072
12
0000 1101
OD
3,328
13
0011 1101
3D
15,616
61
0000 1110
OE
3,584
14
0011 1110
3E
15,872
62
0000 1111
OF
3,840
15
oon nn
3F
16,128
63
0001 0000
10
4,096
16
0100 0000
40
16,384
64
0001 0001
11
4,352
17
0100 0001
41
16,640
65
0001 0010
12
4,608
18
0100 0010
42
16,896
66
0001 0011
13
4,864
19
0100 0011
43
17,152
67
0001 0100
14
5,120
20
0100 0100
44
17,408
68
0100 0101
45
17.664
69
0001 0101
15
5,376
21
0100 0110
46
17,920
70
0001 0110
16
5,632
22
0001 0111
17
5,888
23
0100 0111
47
18,176
71
0001 1000
18
6,144
24
0100 1000
48
18,432
72
0001 1001
19
6,400
25
0100 1001
49
18,688
73
0001 1010
1A
6,656
26
0100 1010
4A
18,944
74
0001 1011
IB
6,912
27
0100 1011
4B
19,200
75
0001 1100
1C
7,168
28
0100 1100
4C
19,456
76
0001 1101
ID
7,424
29
0100 1101
4D
19,712
77
0001 1110
IE
7,680
30
0100 1110
4E
19,968
78
0100 1111
4F
20,224
79
oooi mi
IF
7,936
31
0101 0000
50
20,480
80
0010 0000
20
8,192
32
0010 0001
21
8,448
33
0101 0001
51
20,736
81
0010 0010
22
8,704
34
0101 0010
52
20,992
82
0010 0011
23'
8,960
35
oioi oon
53
21,248
83
0010 0100
24
9,216
36
0101 0100
54
21,504
84
0010 0101
25
9,472
37
0101 0101
55
21,760
85
0010 0110
26
9,728
38
0101 0110
56
22,016
86
0010 0111
27
9,984
39
0101 0111
57
22,272
87
0010 1000
28
10,240
40
0101 1000
58
22,528
88
0101 1001
59
22,784
89
0010 1001
29
10,496
41
0101 1010
5A
23,040
90
0010 1010
2A
10,752
42
0010 1011
2B
11,008
43
0101 1011
5B
23,296
91
0010 1100
2C
11,264
44
0101 1100
5C
23,552
92
0010 1101
2D
11,520
45
0101 1101
5D
23,808
93
0010 1110
2E
11,776
46
0101 1110
5E
24,064
94
ooio mi
2F
12,032
47
oioi nn
5F
24,320
95
494 Appendixes
Binary
Hexadecimal
UB Decimal
LB Decimal
Binary
Hexadecimal
UB Decimal
LB Decimal
0110 0000
60
24,576
96
1001 0010
92
37,376
146
0110 0001
61
24,832
97
1001 0011
93
37,632
147
0110 0010
62
25,088
98
1001 0100
94
37,888
148
0110 0011
63
25,344
99
1001 0101
95
38.144
149
0110 0100
64
25,600
100
iooi ono
96
38,400
150
0110 0101
65
25,856
101
1001 0111
97
38,656
151
0110 0110
66
26,112
102
1001 1000
98
38,912
152
0110 0111
67
26,368
103
1001 1001
99
39,168
153
0110 1000
68
26,624
104
1001 1010
9A
39,424
154
0110 1001
69
26,880
105
1001 1011
9B
39,680
155
0110 1010
6A
27,136
106
1001 1100
9C
39,936
156
0110 1011
6B
27,392
107
1001 1101
9D
40,192
157
0110 1100
6C
27,648
108
1001 1110
9E
40,448
158
0110 1101
6D
27,904
109
iooi nil
9F
40,704
159
0110 1110
6E
28,160
no
1010 0000
AO
40,960
160
ono mi
6F
28,416
111
1010 0001
A1
41,216
161
0111 0000
70
28,672
112
1010 0010
A2
41,472
162
0111 0001
71
28,928
113
1010 0011
A3
41,728
163
0111 0010
72
29,184
114
1010 0100
A4
41,984
164
0111 0011
73
29,440
115
10100101
A5
42,240
165
0111 0100
74
29,696
116
ioio ono
A6
42,496
166
0111 0101
75
29,952
117
1010 0111
A7
42,752
167
0111 0110
76
30,208
118
1010 1000
A8
43,008
168
0111 0111
77
30,464
119
1010 1001
A9
43,264
169
0111 1000
78
30,720
120
1010 1010
AA
43,520
170
01 11 1001
79
30,976
121
1010 1011
AB
43,776
171
0111 1010
7A
31,232
122
1010 1100
AC
44,032
172
0111 1011
7B
31,488
123
1010 1101
AD
44,288
173
0111 1100
7C
31,744
124
1010 1110
AE
44,544
174
0111 1101
7D
32,000
125
ioio ini
AF
44,800
175
0111 1110
7E
32,256
126
1011 0000
BO
45,056
176
oin mi
7F
32,512
127
1011 0001
B1
45,312
177
1000 0000
80
32,768
128
1011 0010
B2
45,568
178
1000 0001
81
33,024
129
1011 0011
B3
45,824
179
1000 0010
82
33,280
130
1011 0100
B4
46,080
180
1000 0011
83
33,536
131
1011 0101
B5
46,336
181
1000 0100
84
33,792
132
ion ono
B6
46,592
182
1000 0101
85
34,048
133
1011 0111
B7
46,848
183
iooo ono
86
34,304
134
1011 1000
B8
47,104
184
1000 0111
87
34,560
135
1011 1001
B9
47,360
185
1000 1000
88
34,816
136
1011 1010
BA
47,616
186
1000 1001
89
35,072
137
1011 1011
BB
47,872
187
1000 1010
8A
35,328
138
1011 1100
BC
48,128
188
1000 1011
8B
35,584
139
1011 1101
BD
48,384
189
1000 1100
8C
35,840
140
1011 1110
BE
48,640
190
1000 1101
8D
36,096
141
ion nil
BF
48,896
191
1000 1110
8E
36,352
142
1100 0000
CO
49,152
192
iooo nil
8F
36,608
143
1100 0001
Cl
49,408
193
1001 0000
90
36,864
144
1100 0010
C2
49,664
194
1001 0001
91
37,120
145
1100 0011
C3
49,920
195
Appendixes 495
APPENDIX 2. BINARY-HEXADECIMAL-DECIMAL EQUIVALENTS ( Continued)
Binary
Hexadecimal
UB Decimal
LB Decimal
Binary
Hexadecimal
UB Decimal
LB Decimal
1100 0100
C4
50,176
196
1110 0010
E2
57,856
226
1100 0101
C5
50,432
197
1110 0011
E3
58,112
227
1100 0110
C6
50,688
198
1110 0100
E4
58,368
228
1100 0111
Cl
50,944
199
1110 0101
E5
58,624
229
1100 1000
C8
51,200
200
11100110
E6
58,880
230
1100 1001
C9
51,456
201
1110 0111
E7
59,136
231
1100 1010
CA
51,712
202
1110 1000
E8
59,392
232
1100 1011
CB
51,968
203
1 11101001
E9
59,648
233
1100 1100
cc
52,224
204
1110 1010
EA
59,904
234
1100 1101
CD
52,480
205
1110 1011
EB
60,160
235
1100 1110
CE
52,736
206
1110 1100
EC
60,416
236
iioo mi
CF
52,992
207
1110 1101
ED
60,672
237
1101 0000
DO
53,248
208
1110 1110
EE
60,928
238
1101 0001
D1
53,504
209
mo nil
EF
61,184
239
1101 0010
D2
53,760
210
1111 0000
FO
61,440
240
1101 0011
D3
54,016
211
1111 0001
FI
61,696
241
1101 0100
D4
54,272
212
nil ooio
F2
61,952
242
1101 0101
D5
54,528
213
nn oon
F3
62,208
243
1101 0110
D6
54,784
214
nil oioo
F4
62,464
244
1101 0111
D7
55,040
215
nil oioi
F5
62,720
245
1101 1000
D8
55,296
216
1111 0110
F6
62,976
246
1101 1001
D9
55,552
217
nil oni
F7
63,232
247
1101 1010
DA
55,808
218
nn iooo
F8
63,488
248
1101 1011
DB
56,064
219
nil iooi
F9
63,744
249
1101 1100
DC
56,320
220
nil ioio
FA
64,000
250
1101 1101
DD
56,576
221
nn ion
FB
64,256
251
1101 1110
DE
56,832
222
1111 1100
FC
64,512
252
noi mi
DF
57,088
223
1111 1101
FD
64,768
253
1110 0000
EO
57,344
224
1111 1110
FE
65,024
254
1110 0001
El
57,600
225
nn nn
FF
65,280
255
496 Appendixes
APPENDIX 3. 7400 SERIES TTL
Number
Function
Number
Function
7400
Quad 2-input nand gates
7455
Expandable 4-input 2-wide and-or-invert
7401
Quad 2-input nand gates (open collector)
gates
7402
Quad 2-input nor gates
7459
Dual 2-3 input 2-wide and-or-invert gates
7403
Quad 2-input nor gates (open collector)
7460
Dual 4-input expanders
7404
Hex inverters
7461
Triple 3-input expanders
7405
Hex inverters (open collector)
7462
2-2-3-3 input 4-wide expanders
7406
Hex inverter buffer-driver
7464
2-2-3-4 input 4-wide and-or-invert gates
7407
Hex buffer-drivers
7465
4-wide and-or-invert gates
7408
Quad 2-input and gates
(open collector)
7409
Quad 2-input and gates (open collector)
7470
Edge-triggered JK flip-flop
7410
Triple 3-input nand gates
7472
JK master-slave flip-flop
7411
Triple 3-input and gates
7473
Dual JK master-slave flip-flop
7412
Triple 3-input nand gates (open collector)
7474
Dual D flip-flop
7413
Dual Schmitt triggers
7475
Quad latch
7414
Hex Schmitt triggers
7476
Dual JK master-slave flip-flop
7416
Hex inverter buffer-drivers
7480
Gates full adder
7417
Hex buffer-drivers
7482
2-bit binary full adder
7420
Dual 4-input nand gates
7483
4-bit binary full adder
7421
Dual 4-input and gates
7485
4-bit magnitude comparator
7422
Dual 4-input nand gates (open collector)
7486
Quad exclusive-or gate
7423
Expandable dual 4-input nor gates
7489
64-bit random-access read-write memory
7425
Dual 4-input nor gates
7490
Decade counter
7226
Quad 2-input TTL-MOS interface nand
7491
8-bit shift register
gates
7492
Divide-by-12 counter
7427
Triple 3-input nor gates
7493
4-bit binary counter
7428
Quad 2-input nor buffer
7494
4-bit shift register
7430
8-input nand gate
7495
4-bit right-shift-left-shift register
7432
Quad 2-input or gates
7496
5-bit parallel-in-parallel-out shift register
7437
Quad 2-input nand buffers
74100
4-bit bistable latch
7438
Quad 2-input nand buffers (open collector)
74104
JK master-slave flip-flop
7439
Quad 2-input nand buffers (open collector)
74105
JK master-slave flip-flop
7440
Dual 4-input nand buffers
74107
Dual JK master-slave flip-flop
7441
BCD-to-decimal decoder-Nixie driver
74109
Dual JK positive-edge-triggered flip-flop
7442
BCD-to-decimal decoder
74116
Dual 4-bit latches with clear
7443
Excess 3-to-decimal decoder
74121
Monostable multivibrator
7444
Excess Gray-to-decimal
74122
Monostable multivibrator with clear
7445
BCD-to-decimal decoder-driver
74123
Monostable multivibrator
7446
BCD-to-seven segment decoder-drivers
74125
Three-state quad bus buffer
(30-V output)
74126
Three-state quad bus buffer
7447
BCD-to-seven segment decoder-drivers
74132
Quad Schmitt trigger
(15-V output)
74136
Quad 2-input exclusive-or gate
7448
BCD-to-seven segment decoder-drivers
74141
BCD-to-decimal decoder-driver
7450
Expandable dual 2-input 2-wide and-or-
74142
BCD counter-latch-driver
invert gates
74145
BCD-to-decimal decoder-driver
7451
Dual 2-input 2-wide and-or-invert gates
74147
10/4 priority encoder
7452
Expandable 2-input 4-wide and-or gates
74148
Priority encoder
7453
Expandable 2-input 4-wide and-or-invert
74150
16-line-to-1 -line multiplexer
gates
74151
8-channel digital multiplexer
7454
2-input 4-wide and-or-invert gates
74152
8-channel data selector-multiplexer
Appendixes 497
APPENDIX 3. 7400 SERIES TTL ( Continued )
Number
Function
Number
Function
74153
Dual 4/1 multiplexer
74190
Up-down decade counter
74154
4-line-to-16-line decoder-demultiplexer
74191
Synchronous binary up-down counter
74155
Dual 2/4 demultiplexer
74192
Binary up-down counter
74156
Dual 2/4 demultiplexer
74193
Binary up-down counter
74157
Quad 2/1 data selector
74194
4-bit directional shift register
74160
Decade counter with asynchronous clear
74195
4-bit parallel-access shift register
74161
Synchronous 4-bit counter
74196
Presettable decade counter
74162
Synchronous 4-bit counter
74197
Presettable binary counter
74163
Synchronous 4-bit counter
74198
8-bit shift register
74164
8-bit serial shift register
74199
8-bit shift register
74165
Parallel-load 8-bit serial shift register
74221
Dual one-shot Schmitt trigger
74166
8-bit shift register
74251
Three-state 8-channel multiplexer
74173
4-bit three-state register
74259
8-bit addressable latch
74174
Hex F flip-flop with clear
74276
Quad JK flip-flop
74175
Quad D flip-flop with clear
74279
Quad debouncer
74176
35-MHz presettable decade counter
74283
4-bit binary full adder with fast carry
74177
35-MHz presettable binary counter
74284
Three-state 4-bit multiplexer
74179
4-bit parallel-access shift register
74285
Three-state 4-bit multiplexer
74180
8-bit odd-even parity generator-checker
74365
Three-state hex buffers
74181
Arithmetic-logic unit
74366
Three-state hex buffers
74182
Look-ahead carry generator
74367
Three-state hex buffers
74184
BCD-to-binary converter
74368
Three-state hex buffers
74185
Binary-to-BCD converter
74390
Individual clocks with dip-flops
74189
Three-state 64-bit random-access memory 1
74393
Dual 4-bit binary counter
498 Appendixes
APPENDIX 4. PINOUTS AND FUNCTION TABLES
74LS83
The 74LS83 is a 4-bit full adder; the binary output is
S = A + B
74LS83
Fig. A4-1
In Fig. A4-1, pins 1, 3, 8, and 10 are the A input (A 3 , A 2 ,
A,, A 0 )\ pins 16, 4, 7, and 11 are the B input (Z? 3 , B 2 , Z?,,
B 0 ); and pins 15, 2, 6, and 9 are the S output (S 3 , S 2 , 5,.
S 0 ). Pin 13 is the CARRY IN, and pin 14 is the CARRY
OUT.
74LS157
This chip is a word multiplexer. Two words of 4 bits each
are the inputs; one word of 4 bits is the output. The two
input words are designated L (left) and R (right); the output
word is Y. In Fig. A4-2, pin 1 (SELECT) and pin 15
(STROBE) are control inputs. The L word goes to pins 14,
11, 5, 2 (C 3 , L 2 , L i# L 0 ), and the R word goes to pins 13,
10, 6, and 3 (fl 3 , R 2 , R lt R 0 ).
74LS157
Fig. A4-2
TABLE A4-1. FUNCTION TABLE
STROBE
SELECT
Y
Comment
1
X
0
Output goes low
0
0
L
Output equals left word
0
1
R
Output equals right word
As indicated in Table A4-1, a high STROBE input
produces a low output, no matter what the input words.
When STROBE is low, the SELECT input controls the
operation. A low SELECT will send the L word to the
output; a high SELECT sends the R word to the output.
74LS173
Fig. A4-3
74LS173
The 74LS173 is a 4-bit buffer register with three-state
outputs. In Fig. A4-3, pins 14, 13, 12, and 11 are the data
inputs (D 3> D 2 , D ,, D 0 ). Pins 3, 4, 5, and 6 are the data
outputs (<2 3 , Q 2 , Q x , <2 w ). Pins 9 and 10 (G, and G 2 ) are
the input control. Pins 1 and 2 (M and N) are the output
control.
As shown in Table A4-2, both M and N must be low to
get a Q output. If either M or N (or both) is high, the
output is three-stated (floating or high impedance).
When M and N are both low, Table A4-3 applies. As
indicated, a high CLEAR will clear all Q bits to 0. When
CLEAR is low, G, and G 2 control input loading. If either
G, or G 2 (or both) are high, no change takes place in the
Q bits. When both G, and G 2 are low, the next positive
clock edge loads the input data.
TABLE A4-2. OUTPUT
CONTROL
M
N
Output
0
0
Connected
0
1
Hi-Z
1
0
Hi-Z
1
1
Hi-Z
TABLE A4-3. FUNCTION TABLE FOR M = 0 AND
N = 0
CLEAR
CLOCK
G 2
D„
Q„
Comment
1
X
X
X
X
0
Clear output
0
0
X
X
X
NC
No change
0
t
1
X
X
NC
No change
0
t
X
1
X
NC
No change
0
t
0
0
0
0
Reset bit n
0
t
0
0
1
1
Set bit n
Appendixes 499
74189
TABLE A4-4. FUNCTION TABLE
a 3 C
1
16
CE C
2
15
WEZ
3
14
d 3 c
4
13
q 3 c
5
12
d 2 C
6
11
q 2 c
7
10
GND C
8
9
3Vfc c
3*2
=m 0
□ ^0
□ Q 0
□ 01
□ Q 1
Fig. A4-4
74189
The 74189 is a 64-bit RAM organized as 16 words of 4
bits each. In Fig. A4-4 pins 1, 15, 14, and 13 are the
address inputs (A 3 , A 2 , A,, A 0 ). Pins 4, 6, 10, and 12 are
the data inputs (D 3 , D 2 , D,, D 0 ). Pins 5, 7, 9, and 11 are
the data outputs (Q 3 , Q 2 , Go Go)*
CE
WE
Output
Comment
1
X
Hi-Z
Do nothing
0
0
Hi-Z
Write complement
0
1
Stored word
Read
Table A4-4 summarizes the operation of this read-write
memory. When CE is high, the output is three-stated (high
impedance). When CE is low and WE is low, the comple¬
ment of the input data word is stored at the addressed
memory location; during this write operation, the output is
three-stated. When CE is low and WE is high, the stored
word appears at the output.
500 Appendixes
APPENDIX 5. SAP-1 PARTS LIST
Chips
Cl: 74LS107, dual JK master-slave flip-flop
C2: 74LS107
C3: 74LS126, quad three-state normally open switches
C4: 74LS173, buffer register, three-state outputs, 4 bits
C5: 74LS157, 2-to-l nibble multiplexer
C6: 74189, 64-bit (16 x 4) static RAM, three-state
outputs
C7: 74189
C8: 74LS173
C9: 74LS173
CIO: 74LS173
Cl 1: 74LS173
Cl2: 74LS126
C13: 74LS126
Cl4: 74LS86, quad 2-input exclusive-or gates
Cl5: 74LS86
Cl6: 74LS83, quad full adders
Cl7: 74LS83
Cl8: 74LS126
Cl9: 74LS126
C20: 74LS173
C21: 74LS173
C22: 74LS173
C23: 74LS173
C24: 7400, quad 2-input nand gates
C25: 74LS10, triple 3-input nand gates
C26: 74LS00
C27: 7404, hex inverter
C28: NE555, timer
C29: 74LS107
C30: LM340T-5, voltage regulator, 5 V
C31: 74LS04, hex inverter
C32: 74LS20, dual 4-input nand gates
C33: 74LS20
C34: 74LS20
C35: 74LS04
C36: 74LS107
C37: 74LS107
C38: 74LS107
C39: 74LS00
C40: 74LS00
C41: 74LS00
C42: 74LS00
C43: 74LS00
C44: 74LS20
C45: 74LS10
C46: 74LS00
C47: 74LS04
C48: 74LS04
Diodes
Dl: 1N4001, rectifier diode, 50 PIV, 1 A
D2: 1N4001
D3: 1N4001
D4: 1N4001
Switches
SI: SPST DIP switch, 4 bits
S2: DPST on-off
S3: SPST DIP, 8 bits
S4: SPST push button, momentary, normally open
S5: SPDT push button, momentary
S6: SPDT push button, momentary
S7: SPDT on-on switch
Miscellaneous
Resistors: eight 1-kfi, fourteen 10-kD, one 18-kD, one
36-kO
Capacitors: 0.01-(utF, 0.1 -|ulF, 1000-|ulF (50 V)
Transformer: F-25X — 115V primary, 12.6 V secondary
CT, 1.5 A
Fuse: |-A slow blow
Totals
1N4001 -4
74LS20-4
LM340T-5-1
74LS83-2
NE555-1
74LS86-2
7400-1
74LS107-6
74LS00-7
74LS126-5
7404-1
74LS157-1
74LS04—4
74LS173-9
74LS10-2
74189-2
Appendixes
501
APPENDIX 6. 8085 INSTRUCTIONS
Instruction
Op Code
T states
AC1 byte
CE
7
ADC A
8F
4
ADC B
88
4
ADC C
89
4
ADC D
8A
4
ADC E
8B
4
ADC H
8C
4
ADC L
8D
4
ADC M
8E
7
ADD A
87
4
ADD B
80
4
ADD C
81
4
ADD D
82
4
ADD E
83
4
ADD H
84
4
ADD L
85
4
ADD M
86
7
ADI byte
C6
7
ANA A
A7
4
ANA B
AO
4
ANA C
A1
4
ANA D
A2
4
ANA E
A3
4
ANA H
A4
4
ANA L
A5
4
ANA M
A6
7
ANI byte
E6
7
CALL address
CD
18
CC address
DC
18/9
CM address
FC
18/9
CMA
2F
4
CMC
3F
4
CMP A
BF
4
CMP B
B8
4
CMP C
B9
4
CMP D
BA
4
CMP E
BB
4
CMP H
BC
4
CMP L
BD
4
CMP M
BE
7
CNC address
D4
18/9
CNZ address
C4
18/9
CP address
F4
18/9
CPE address
EC
18/9
CPI byte
FE
7
CPO address
E4
18/9
CZ address
CC
18/9
DAA
27
4
DAD B
09
10
DAD D
19
10
DAD H
29
10
Main Effect
A + B + CY
A + E
H 4- CY
A + B
A + C
A + D
A + E
A + H
A + L
A 4- M hl
A 4- byte
A and A
A AND B
A AND C
A AND D
A AND E
A AND H
A AND L
A AND M hl
A and byte
— address
— address if CY =
— address if S = 1
■A
- address if CY — 0
- address if Z = 0
- address if 5 = 0
- address if P = 1
1 if A = byte
- address if P = 0
- address if Z = 1
BCD number
- HL + BC
- HL 4- DE
- HL 4- HL
502 Appendixes
Instruction
Op Code
T states
Flags
Main Effect
DAD SP
DCR A
DCR B
DCR C
DCR D
DCR E
DCR H
DCR L
DCR M
DCX B
DCX D
DCX H
DCX SP
DI
El
HLT
IN byte
INR A
INR B
INR C
INR D
INR E
INR H
INR L
INR M
INX B
INX D
INX H
INX SP
JC address
JM address
JMP address
JNC address
JNZ address
JP address
JPE address
JPO address
JZ address
39
3D
05
0D
15
ID
25
2D
35
OB
IB
2B
3B
F3
FB
76
DB
3C
04
0C
14
1C
24
2C
34
03
13
23
33
DA
FA
C3
D2
C2
F2
EA
E2
CA
10
4
4
4
4
4
4
4
10
6
6
6
6
4
4
5
10
4
4
4
4
4
4
4
10
6
6
6
6
10/7
10/7
10
10/7
10/7
10/7
10/7
10/7
10/7
CY
All but CY
All but CY
All but CY
All but CY
All but CY
All but CY
All but CY
All but CY
None
None
None
None
None
None
None
None
All but CY
All but CY
All but CY
All but CY
All but CY
All but CY
All but CY
All but CY
None
None
None
None
None
None
None
None
None
None
None
None
None
HL HL + SP
A A - 1
B <- B - 1
C <-C - 1
D <— D - 1
E <— E - 1
H <— H — 1
L <— L - 1
Mhl ■*“ M HL — 1
BC BC — 1
DE DE - 1
HL <— HL - 1
SP 4- SP - 1
Disable interrupts
Enable interrupts
Stop processing
A byte
A <— A + 1
B B + 1
C <- C + 1
D <— D + 1
E <- E + 1
H <— H + 1
L <- L + 1
M hl M hl + 1
BC <— BC 4- 1
DE <— DE 4- 1
HL HL 4- 1
SP <- SP 4- 1
PC <— address if CY = 1
PC address if S = 1
PC <— address
PC <— address if CY = 0
PC <— address if Z = 0
PC <— address if S = 0
PC <— address if P = 1
PC «— address if P = 0
PC address if Z = 1
LDA address
3A
13
None
A ^ M adr
LDAX B
0A
7
None
A M bc
LDAX D
1A
7
None
A <- M de
LHLD address
2A
16
None
H <- M adr
LXI B, dble
01
10
None
BC <- dble
LXI D, dble
11
10
None
DE <- dble
LXI H, dble
21
10
None
HL dble
LXI SP, dble
31
10
None
SP dble
MOV A,A
7F
4
None
A <— A
MOV A,B
78
4
None
A <- B
MOV A,C
79
4
None
A ^C
MOV A,D
7A
4
None
A D
MOV A,E
7B
4
None
A E
MOV A,H
1C
4
None
A <- H
Appendixes 5 03
APPENDIX 6. 8085 INSTRUCTIONS ( Continued )
Instruction
Op Code
T states
Flags
MOV A,L
7D
4
None
MOV A,M
7E
7
None
MOV B,A
47
4
None
MOV B,B
40
4
None
MOV B,C
41
4
None
MOV B,D
42
4
None
MOV B,E
43
4
None
MOV B,H
44
4
None
MOV B,L
45
4
None
MOV B,M
46
7
None
MOV C,A
4F
4
None
MOV C,B
48
4
None
MOV C,C
49
4
None
MOV C,D
4A
4
None
MOV C,E
4B
4
None
MOV C,H
4C
4
None
MOV C,L
4D
4
None
MOV C,M
4E
7
None
MOV D,A
57
4
None
MOV D,B
50
4
None
MOV D,C
51
4
None
MOV D,D
52
4
None
MOV D,E
53
4
None
MOV D,H
54
4
None
MOV D,L
55
4
None
MOV D,M
56
7
None
MOV E,A
5F
4
None
MOV E,B
58
4
None
MOV E,C
59
4
None
MOV E,D
5A
4
None
MOV E,E
5B
4
None
MOV E,H
5C
4
None
MOV E,L
5D
4
None
MOV E,M
5E
7
None
MOV H,A
67
4
None
MOV H,B
60
4
None
MOV H,C
61
4
None
MOV H,D
62
4
None
MOV H,E
63
4
None
MOV H,H
64
4
None
MOV H,L
65
4
None
MOV H,M
66
7
None
MOV L,A
6F
4
None
MOV L,B
68
4
None
MOV L,C
69
4
None
MOV L,D
6A
4
None
MOV L,E
6B
4
None
MOV L,H
6C
4
None
MOV L,L
6D
4
None
MOV L,M
6E
7
None
MOV M,A
77
7
None
504 Appendixes
Main Effect
A L
a-m hl
B <- A
B <— B
B <— C
B <— D
B <— E
B <- H
B <-L
B -M hl
C <- A
C <- B
c
C <- D
C ^E
C <— H
C L
C^M hl
D A
D B
D
D <- D
D <- E
D <- H
D 4- L
D 4- M hl
E 4- A
E <— B
E «-C
E 4 - D
E «-E
E <— H
E L
E^M hl
H 4- A
H <— B
H *-C
H D
H ^E
H <- H
H <- L
H^M hl
L <- A
L <- B
L
L <- D
L <— E
L 4- H
L ^ L
B *— M hl
M H l A
Instruction
T states
Main Effect
Op Code
Flags
MOV M,B
MOV M,C
MOV M,D
MOV M,E
MOV M,H
MOV M,L
MV1 A,byte
MVI B,byte
MVI C,byte
MVI D,byte
MVI E,byte
MVI H,byte
MVI L,byte
MVI M,byte
NOP
ORA A
ORA B
ORA C
ORA D
ORA E
ORA H
ORA L
ORA M
ORI byte
OUT byte
PCHL
POP B
POP D
POP H
RAL
RAR
RC
RET
RIM
RLC
RM
RNC
RNZ
RP
RPE
RPO
RRC
RST 0
RST 1
RST 2
RST 3
RST 4
RST 5
70
71
72
73
74
75
3E
06
0E
16
IE
26
2E
36
00
B7
BO
B1
B2
B3
B4
B5
B6
F6
D3
E9
Cl
D1
El
17
IF
D8
C9
20
07
F8
DO
CO
F0
E8
E0
OF
Cl
CF
D7
DF
E7
EF
7
7
7
7
7
7
7
7
7
7
7
7
7
10
4
4
4
4
4
4
4
4
7
7
10
6
10
10
10
4
4
12/6
10
4
4
12/6
12/6
12/6
12/6
12/6
12/6
4
12
12
12
12
12
12
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
All
All
All
All
All
All
All
All
All
None
None
None
None
None
CY
CY
None
None
None
CY
None
None
None
None
None
None
CY
None
None
None
None
None
None
M hl
M«l
M„ l
m„ l
m hi .
A <-
- B
-C
- D
- E
- H
- L
byte
B «- byte
C <— byte
D <— byte
E <— byte
H <- byte
L byte
Mhl byte
Delay
A
A
A
A
A
A
A
A
A
Port byte «
PC HL
B «- M stk
D <- M stk
H M stk
A or A
A OR B
A or C
A OR D
A or E
A or H
A or L
A or M hl
A or byte
A
POP PSW
FI
10
None
F «- M stk , A 4- M stk
- 1
PUSH B
C5
12
None
M slk — 1 «— B, M slk
- 2 ^C
PUSH D
D5
12
None
M stk - 1 <— D, M stk
- 2 ^ E
PUSH H
E5
12
None
M stk - 1 <— H, M SIk
- 2 <— L
PUSH PSW
F5
12
None
M slk — 1 «— A, M stk
- 2 ^F
Rotate all left
Rotate all right
PC <— return address if CY = 1
PC return address
A <- I
Rotate left with carry
PC
PC
PC
PC
PC
PC
return address if S = 1
return address if CY = 0
return address if Z
return address if S
return address if P
return address if P
Rotate right with carry
PC <- 0000H
PC <- 0008H
PC ^ 001 OH
PC ^0018H
PC <- 0020H
PC <- 0028H
0
0
1
0
Appendixes 5 05
APPENDIX 6. 8085 INSTRUCTIONS ( Continued )
Instruction Op Code T states Flags Main Effect
RST 6
F7
12
None
RST 7
FF
12
None
RZ
C8
12/6
None
SBB A
9F
4
All
SBB B
98
4
All
SBB C
99
4
All
SBB D
9A
4
All
SBB E
9B
4
All
SBB H
9C
4
All
SBB L
9D
4
All
SBB M
9E
7
All
SBI byte
DE
7
All
SHLD address
22
16
None
SIM
30
4
None
SPHL
F9
6
None
ST A address
32
13
None
STAX B
02
7
None
STAX D
12
7
None
STC
37
4
CY
SUB A
97
4
All
SUB B
90
4
All
SUB C
91
4
All
SUB D
92
4
All
SUB E
93
4
All
SUB H
94
4
All
SUB L
95
4
All
SUB M
96
7
All
SUI byte
D6
7
All
XCHG
EB
4
None
XRA A
AF
4
All
XRA B
A8
4
All
XRA C
A9
4
All
XRA D
AA
4
All
XRA E
AB
4
All
XRA H
AC
4
All
XRA L
AD
4
All
XRA M
AE
7
All
XRI byte
EE
7
All
XTHL
E3
16
None
PC <- 0030H
PC <- 0038H
PC return address if Z
A <- A - A - CY
A <- A - B - CY
A A - C - CY
A <— A — D - CY
A <- A - E - CY
A <- A - H - CY
A <— A - L - CY
A A - M - CY
A A - byte - CY
^adr+l < H, M adr L
I A
SP HL
M adr <- A
M bc A
M de < A
CY <- 1
A <— A - A
A <- A - B
A <— A - C
A <- A - D
A 4- A - E
A <— A - H
A <- A - L
A <— A - M
A A — byte
HL ** DE
A <— A xor A
A <— A xor B
A <— A xor C
A <— A xor D
A <— A xor E
A A xor H
A <— A xor L
A <— A xor M
A <— A xor byte
HL ** stack
1
5 06 Appendixes
APPENDIX 7. MEMORY LOCATIONS:
POWERS OF 2
Power
Address Bits
Hexadecimal
Decimal
of 2
0000 0000 0000 0001
0001H
1
0
0000 0000 0000 0010
0002H
2
1
0000 0000 0000 0100
0004H
4
2
0000 0000 0000 1000
0008H
8
3
0000 0000 0001 0000
001 OH
16
4
0000 0000 0010 0000
0020H
32
5
0000 0000 0100 0000
0040H
64
6
0000 0000 1000 0000
0080H
128
7
0000 0001 0000 0000
0100H
256
8
0000 0010 0000 0000
0200H
512
9
0000 0100 0000 0000
0400H
1,024
10
0000 1000 0000 0000
0800H
2,048
11
0001 0000 0000 0000
1000H
4,096
12
0010 0000 0000 0000
2000H
8,192
13
0100 0000 0000 0000
4000H
16,384
14
1000 0000 0000 0000
8000H
32,768
15
APPENDIX 8. MEMORY LOCATIONS:
16K AND 8K INTERVALS
Address Bits
Hexadecimal
Decimal
Zone
Zone bits = A, 5 A, 4
0000 0000 0000 0000
ooii mi mi nil
0000H
3FFFH
0
16,383
0
0100 0000 0000 0000
oin mi mi mi
4000H
7FFFH
16,384
32,767
1
1000 0000 0000 0000
ion nil nil nil
8000H
BFFFH
32,768
49,151
2
1100 0000 0000 0000
nil nil nil nil
C000H
FFFFH
49,152
65,535
3
Zone bits = A I5 A 14 A I
13
0000 0000 0000 0000
oooi nil nil nil
0000H
1FFFH
0
8,191
0
0010 0000 0000 0000
oon nil nn nil
2000H
3FFFH
8,192
16,383
1
0100 0000 0000 0000
0101 1111 1111 1111
4000H
5FFFH
16,384
24,575
2
0110 0000 0000 0000
0111 1111 1111 1111
6000H
7FFFH
24,576
32,767
3
1000 0000 0000 0000
iooi nil nn nn
8000H
9FFFH
32,768
40,959
4
1010 0000 0000 0000
1011 1111 1111 1111
A000H
BFFFH
40,960
49,151
5
1100 0000 0000 0000
1101 1111 1111 1111
C000H
DFFFH
49,152
57,343
6
1110 0000 0000 0000
1111 1111 1111 1111
E000H
FFFFH
57,344
65,535
7
APPENDIX 9. MEMORY LOCATIONS:
4K INTERVALS
Address Bits
Hexadecimal
Decimal
Zone
Zone bits = A^A^A^A^
0000 0000 0000 0000
0000 1111 1111 1111
0000H
OFFFH
0
4,095
0
0001 0000 0000 0000
oooi nn nn nn
1000H
1FFFH
4,096
8,191
1
0010 0000 0000 0000
ooio nn nn nn
2000H
2FFFH
8,192
12,287
2
0011 0000 0000 0000
oon nn nn nn
3000H
3FFFH
12,288
16,383
3
0100 0000 0000 0000
oioo ini nn nn
4000H
4FFFH
16,384
20,479
4
0101 0000 0000 0000
oioi nil nn nn
5000H
5FFFH
20,480
24,575
5
0110 0000 0000 0000
ono nn ini nn
6000H
6FFFH
24,576
28,671
6
0111 0000 0000 0000
0111 1111 1111 1111
7000H
7FFFH
28,672
32,767
7
1000 0000 0000 0000
1000 1111 1111 1111
8000H
8FFFH
32,768
36,863
8
1001 0000 0000 0000
1001 1111 1111 1111
9000H
9FFFH
36,864
40,959
9
1010 0000 0000 0000
1010 1111 1111 1111
A000H
AFFFH
40,960
45,055
10
1011 0000 0000 0000
1011 1111 1111 1111
B000H
BFFFH
45,056
49,151
11
1100 0000 0000 0000
1100 1111 1111 1111
C000H
CFFFH
49,152
53,247
12
1101 0000 0000 0000
1101 1111 1111 1111
D000H
DFFFH
53,248
57,343
13
1110 0000 0000 0000
1110 1111 1111 1111
E000H
EFFFH
57,344
61,439
14
1111 0000 0000 0000
nil nn nn nn
F000H
FFFFH
61,440
65,535
15
Appendixes 507
APPENDIX 10. MEMORY LOCATIONS: 2K INTERVALS
Address Bits
Hexadecimal
Decimal
Zone
Address Bits
Hexadecimal
Decimal
Zone
Zone bits = A,
5-^ 14 A ] 3 A j 2 A j |
0000 0000 0000 0000
oooooni mi mi
0000 H
07FFH
0
2,047
0
1000 0000 0000 0000
iooo oni mi nn
8000H
87FFH
32,768
34,815
16
0000 1000 0000 0000
0000 1111 1111 1111
0800H
OFFFH
2,048
4,095
1
1000 1000 0000 0000
1000 1111 1111 1111
8800H
8 FFFH
34,816
36,863
17
0001 0000 0000 0000
oooi oni nil nil
1000H
17FFH
4,096
6,143
2
1001 0000 0000 0000
iooi oni nil nn
9000H
97FFH
36,864
38,911
18
0001 1000 0000 0000
oooi nil nil nil
1800H
1FFFH
6,144
8,191
3
1001 1000 0000 0000
1001 1111 1111 1111
9800H
9FFFH
38,912
40,959
19
0010 0000 0000 0000
ooiooni nil nil
2000H
27FFH
8,192
10,239
4
1010 0000 0000 0000
10100111 1111 1111
A000H
A7FFH
40,960
43,007
20
0010 1000 0000 0000
ooio nil nil nil
2800H
2FFFH
10,240
12,287
5
1010 1000 0000 0000
1010 1111 1111 1111
A800H
AFFFH
43,008
45,055
21
0011 0000 0000 0000
oon oni nil nil
3000H
37FFH
12,288
14,335
6
1011 0000 0000 0000
ion oni nn nn
B000H
B7FFH
45,056
47,103
22
0011 1000 0000 0000
oon nil nil nn
3800H
3FFFH
14,336
16,383
7
1011 1000 0000 0000
ion nn nn nn
B800H
BFFFH
47,104
49,151
23
0100 0000 0000 0000
0100 0111 1111 1111
4000H
47FFH
16,384
18,431
8
1100 0000 0000 0000
1100 0111 1111 1111
C000H
C7FFH
49,152
51,199
24
0100 1000 0000 0000
0100 1111 1111 1111
4800H
4FFFH
18,432
20,479
9
1100 1000 0000 0000
1100 1111 1111 1111
C800H
CFFFH
51,200
53,247
25
0101 0000 0000 0000
oioi oni nn nn
5000H
57FFH
20,480
22,527
10
1101 0000 0000 0000
1101 0111 1111 1111
D000H
D7FFH
53,248
55,295
26
0101 1000 0000 0000
0101 1111 1111 1111
5800H
5FFFH
22,538
24,575
11
1101 1000 0000 0000
noi nn nn nn
D800H
DFFFH
55,296
57,343
27
0110 0000 0000 0000
01100111 1111 1111
6000H
67FFH
24,576
26,623
12
1110 0000 0000 0000
11100111 1111 1111
E000H
E7FFH
57,344
59,391
28
0110 1000 0000 0000
0110 1111 1111 1111
6800H
6 FFFH
26,624
28,671
13
1110 1000 0000 0000
1110 1111 1111 1111
E800H
EFFFH
59,392
61,439
29
0111 0000 0000 0000
0111 0111 1111 1111
7000H
77FFH
28,672
30,719
14
1111 0000 0000 0000
nn oni nn nn
F000H
F7FFH
61,440
63,487
30
0111 1000 0000 0000
0111 1111 1111 1111
7800H
7FFFH
30,720
32,767
15
1111 1000 0000 0000
nn nn nn nn
F800H
FFFFH
63,488
65,535
31
508 Appendixes
APPENDIX 11. MEMORY LOCATIONS: IK INTERVALS
Address Bits
Hexadecimal
Decimal
Zone
Address Bits
Hexadecimal
Decimal
Zone
Zone bits = A,
5A 14 A| 3 A| 2 A| j A jo
0000 0000 0000 0000
ooooooii mi mi
OOOOH
03FFH
0
1,023
0
0101 oooo oooo oooo
oioi oon nn nn
5000H
53FFH
20,480
21,503
20
0000 0100 0000 0000
oooooni nil nil
0400H
07FFH
1,024
2,047
1
0101 oioo oooo oooo
0101 0111 1111 1111
5400H
57FFH
21,504
22,527
21
0000 1000 oooo oooo
oooo ion nil nn
0800H
OBFFH
2,048
3,071
2
0101 1000 0000 0000
0101 1011 1111 1111
5800H
5BFFH
22,528
23,551
22
0000 1100 oooo oooo
0000 1111 1111 1111
OCOOH
OFFFH
3,072
4,095
3
0101 1100 0000 0000
oioi nn nn nn
5C00H
5FFFH
23,552
24,575
23
0001 oooo oooo oooo
0001 0011 1111 1111
1000H
13FFH
4,096
5,119
4
0110 oooo oooo oooo
onooon nn nn
6000H
63FFH
24,576
25,599
24
0001 0100 oooo oooo
0001 0111 1111 1111
1400H
17FFH
5,120
6,143
5
0110 0100 oooo oooo
onooin nn nn
6400H
67FFH
25,600
26,623
25
0001 1000 0000 0000
0001 1011 1111 1111
1800H
1BFFH
6,144
7,167
6
0110 1000 oooo oooo
ono ion nn nn
6800H
6BFFH
26,624
27,647
26
0001 1100 0000 0000
0001 1111 1111 1111
1C00H
1FFFH
7,168
8,191
7
0110 1100 oooo oooo
ono nn nn nn
6C00H
6FFFH
27,648
28,671
27
0010 oooo oooo oooo
0010 0011 1111 1111
2000H
23FFH
8,192
9,215
8
0111 oooo oooo oooo
oni oon nn nn
7000H
73FFH
28,672
29,695
28
0010 0100 oooo oooo
0010 0111 1111 1111
2400H
27FFH
9,216
10,239
9
0111 oioo oooo oooo
oni oni nn nn
7400H
77FFH
29,696
30,719
29
0010 1000 oooo oooo
0010 1011 1111 1111
2800H
2BFFH
10,240
11,263
10
0111 1000 0000 0000
oni ion mi nn
7800H
7BFFH
30,720
31,743
30
0010 1100 oooo oooo
0010 1111 1111 1111
2C00H
2FFFH
11,264
12,287
11
0111 1100 0000 0000
oni nil nn nil
7C00H
7FFFH
31,744
32,767
31
0011 oooo oooo oooo
0011 0011 1111 1111
3000H
33FFH
12,288
13,311
12
1000 oooo oooo oooo
looooon nn nn
8000H
83FFH
32,768
33,791
32
0011 0100 oooo oooo
oon oni nn nil
3400H
37FFH
13,312
14,335
13
1000 oioo oooo oooo
1000 0111 1111 1111
8400H
87FFH
33,792
34,815
33
0011 1000 0000 0000
oon ion nn nn
3800H
3BFFH
14,336
15,359
14
1000 1000 oooo oooo
1000 1011 1111 1111
8800H
8BFFH
34,816
35,839
34
0011 1100 0000 0000
oon nn nn nn
3C00H
3FFFH
15,360
16,383
15
1000 1100 oooo oooo
1000 1111 1111 1111
8C00H
8FFFH
35,840
36,863
35
0100 oooo oooo oooo
oioooon nn nn
4000H
43FFH
16,384
17,407
16
1001 oooo oooo oooo
iooi oon nn nn
9000H
93FFH
36,864
37,887
36
0100 0100 oooo oooo
0100 0111 1111 1111
4400H
47FFH
17,408
18,431
17
1001 0100 oooo oooo
1001 0111 1111 1111
9400H
97FFH
37,888
38,911
37
0100 1000 oooo oooo
0100 1011 1111 1111
4800H
4BFFH
18,432
19,455
18
1001 1000 0000 0000
1001 1011 1111 1111
9800H
9BFFH
38,912
39,935
38
0100 1100 oooo oooo
oioo nn nn nn
4C00H
4FFFH
19,456
20,479
19
1001 1100 0000 0000
1001 1111 1111 1111
9C00H
9FFFH
39,936
40,959
39
Appendixes
509
APPENDIX 11. MEMORY LOCATIONS: IK INTERVALS ( Continued)
Address Bits
Hexadecimal
Decimal
Zone
Address Bits
Hexadecimal
Decimal
Zone
Zone bits = Aj
5A 14 A 1 3A 12 A 1] A 10
1010 0000 0000 0000
ioioooii mi mi
A000H
A3FFH
40,960
41,983
40
1101 0000 0000 0000
1101 0011 1111 1111
D000H
D3FFH
53,248
54,271
52
1010 0100 0000 0000
loiooin nil nil
A400H
A7FFH
41,984
43,007
41
1101 0100 0000 0000
noi oni nil nn
D400H
D7FFH
54,272
55,295
53
1010 1000 0000 0000
ioio ion nil nil
A800H
ABFFH
43,008
44,031
42
1101 1000 0000 0000
noi ion nil nn
D800H
DBFFH
55,296
56,319
54
1010 1100 0000 0000
ioio nil nil nil
ACOOH
AFFFH
44,032
45,055
43
1101 1100 0000 0000
1101 1111 1111 1111
DCOOH
DFFFH
56,320
57,343
55
1011 0000 0000 0000
ion ooii mi mi
B000H
B3FFH
45,056
46,079
44
1110 0000 0000 0000
1110 0011 1111 1111
E000H
E3FFH
57,344
58,367
56
1011 0100 0000 0000
ion oni nil nil
B400H
B7FFH
46,080
47,103
45
1110 0100 0000 0000
liiooin nn ini
E400H
E7FFH
58,368
59,391
57
1011 1000 0000 0000
ion ion mi nil
B800H
BBFFH
47,104
48,127
46
1110 1000 0000 0000
1110 1011 1111 1111
E800H
EBFFH
59,392
60,415
58
1011 1100 0000 0000
ion nil nil nil
BCOOH
BFFFH
48,128
49,151
47
1110 1100 0000 0000
1110 1111 1111 1111
ECOOH
EFFFH
60,416
61,439
59
1100 0000 0000 0000
noooon mi nil
C000H
C3FFH
49,152
50,175
48
1111 0000 0000 0000
nn oon nn nn
F000H
F3FFH
61,440
62,463
60
1100 0100 0000 0000
noooin nn nil
C400H
C7FFH
50,176
51,199
49
n n oioo oooo oooo
1111 0111 1111 1111
F400H
F7FFH
62,464
63,487
61
1100 1000 0000 0000
1100 1011 1111 1111
C800H
CBFFH
51,200
52,223
50
1111 1000 0000 0000
nil ion nn ini
F800H
FBFFH
63,488
64,511
62
1100 1100 0000 0000
1100 1111 1111 1111
CCOOH
CFFFH
52,224
53,247
51
1111 noo oooo oooo
nil nn nil nn
FCOOH
FFFFH
64,512
65,535
63
510 Appendixes
APPENDIX 12. PROGRAMMING MODELS
0000
0001
A 0002
d
d 0003
r 0004
e
s 0005
s 0006
s 0007
0008
0009
Fig. A12-1
0000
0001
A 0002
d
d 0003
r 0004
e
s 0005
s 0006
I 0007
0008
0009
Fig. A12-2
Accumulator
hh
X Register
hh
Y Register j
hh
1
Stack pointer
hh
PCh—-P rogram
hh
counter—PC L
hh
Status register
N V —BDIZC
bb — bbbbb
h | h
6502 programming model.
Accumulator A
hh
Accumulator B
hh
X H —X Register—X L
hh | hh
SP H —Stack pointer—SP L
hh | hh
PC H —Program
hh
i counter—PC L
hh
Status register
1 1 H1N ZVC
1 1 bbbbbb
h h
6800/6808 programming model.
Memory
0000
0001
0002
0003
0004
0005
0006
0007
0008
0009
000A
hh
hh
hh
hh
hh
hh
hh
hh
hh
hh
hh
Accumulator
hh
Register B
hh
Register C
hh
Register D
hh
Register E
hh
.
Register H
hh
_i
Register L
hh
i ___
SPh—S tack pointer—SP L
hh | hh
PC H —Program
hh
counter—PC L
hh
Status register
SZ — A— P — C
bb—b—b —b
h | h
Fig. A12-3 8085/Z80 (8085/8080 subset) programming model.
Memory
A
d
d
r
e
s
s
e
s
0100
0101
0102
0103
0104
0105
0106
0107
0108
0109
010A
010B
010C
010D
010E
010F
0110
0111
0112
0113
0114
0115
0116
0117
hh
hh
hh
hh
hh
hh
hh
hh
hh
hh
hh
hh
hh
hh
hh
hh
hh
hh
hh
hh
hh
hh
hh
hh
— Accumulator AX —
AH j AL
hh D 1 dv hh
-Base BX-
BH
hh
CH
hh
- Count CX-
i
i
- Data DX -
BL
hh
CL
hh
DH
hh
DL
hh
Source index
hhhh
Destination index
hhhh
Stack pointer
hhhh
Base pointer
hhhh
Code segment
hhhh
Data segment
hhhh
Extra segment
hhhh
Stack segment
hhhh
Instruction pointer
hhhh
--”22^7- r i c
new
yb 8085-like
-0 D 1 T
-b b b b
h | h
S Z — A— P — C
b b — b — b — b
h | h
Fig. A12-4 8088/8086 programming model.
Appendixes 511
Answers to Odd-Numbered Problems
CHAP. 1. 1-1. a. 1 b. 2 c. 2Vi 1-3. a. 10 b. 2 c. 5
d. 16 1-5. 1,024, 4,096, 8K 1-7. 1010 1100, 172 1-9.
201 1-11.11000111,199 1-13,111000 1-15.10010110
1- 17. F52B, F52C, F52D, F52E, F52F, F530 1-19.
a. 1111 1111 b. 1010 1011 1100 c. 1100 1101 0100 0010
d. 1111001100101001 1-21.0011 1110,0000 1110, 1101
0011, 0010 0000, 0111 0110 1-23. a. 4,095 b. 16,383
c. 32,740 d. 46,040 1-25. 16,384, 16K 1-27. 0000,
FFFF 1-29. a. EE b. 1D7B c. 3BFF d. B8B5 1-31.
a. 87 b. 2,043 c. 597,266 1-33. 100 1100, 100 1001, 101
'O0TT, 101 0100
CHAP. 2. 2-1 One or more, one 2-3. Nonin¬
verter 2-5.64,000000 2-7.3,9,C,F 2-9.128,1111111
2- 11.0,59 2-13. Y = A + B, low 2-15.8 2-17. 0, Y
= A + B + C, 000 to 110, 111 2-19. Y = ABC, 0 2-
21. Y = AB + CD , 16, 0000, 0001, 0010, 0100, 0101,
0110, 1000, 1001, 1010 2-23. a. 0000 b. 0001 c. JIM
d. OPR 2-25. a. Positive b. Negative c. Positive d. Negative.
CHAP. 3. 3-1. High; low; inverter 3-3. None, Z 5 , Z 6
3- 5. Q is 1, Q is 0 3-7. Change the output nor gate of
Fig. 3-28 a to a bubbled and gate; all bubbles cancel leaving
the simplified circuit of Fig. 3-28 b. 3-9. 0, 1 3-11.512
3-13. 16; 0, 1, 1, 0 3-15. I, 0, inverter 3-17. a. None
b. Z 7 c. Z 2 d. X 2 and Y 2 3-19. 0, 1 3-21. 512 3-23.
Low, high 3-25. a. 0 b. 1 c. 1 d. 1 3-27. a. 1,1010b.
01001 c. 11111 d. 10010 3-29. Remove the inverter
3-31. a. CARRY = 0, SUM = 0 b. 0, 1 c. 0, 1 d. 1, 0
3-33. a. 0011 1100 b. 0101 0000 1100 c. 0001 1110 0101
1100 d. 1111 0000 1101 0010
CHAP. 4. 4-1. 1.075 mA, 1.387 mA 4-3. 5 4-5. All;
b, c, f, g
5-5.
aabbccdd
CD CD CD CD
AB
AB
AB
AB
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
5-9.
CD CD CD CD
CHAP. 5. 5-1. A BCD, ABCD, ABCD
5-3.
AABBCCDD
t>-
513
5 - 11 .
5 - 15 .
CD CD CD CD
5-13.
CD CD CD CD
AABBCCDD
CD CD CD CD
AABBCCDD
CHAP. 6. 6-1. a. 0001 1000, 18H b. 0010 0100, 24H
c. 0010 1010, 2AH d. 0110 0011, 63H 6-3. a. 7BH
b. 78H c. A8H d. D1H 6-5. a. +30 b. -7 c. -28
d. +49 6-7. a. F9H b. 01H c. 03H d. 1FH 6-9.
a. 1110 1101, EDH b. 1101 0000, DOH c. 0010 0101,
25H d. 1101 1111, DFH 6-11. 9BH, DDH
CHAP. 7. 7-1. a. C b. G 7-3. a. 0000 b. 1001 7-5.3
MHz; the output frequency is half the input frequency
7- 7. 0 = 0, Y = 1; Q = 1, Y = CLK
CHAP. 8. 8-1. a. 0001 0111 b. 1000 1101 8-3. 385 D
8- 5. 4 (jls 8-7. 6.4 8-9. 65,535 8-11. 1 pus, 6 |jls
8-13. 1.6 jxs, 0.2 |uls 8-15. Two answers: 7490 (divide by
10) and 7492 (divide by 6), or 7490 (divide by 5) and 7492
(divide by 12) 8-17. 136 8-19. a. 0, 1 b. 1, 1 c. 0
CHAP. 9. 9-1. 16,384 9-3. 12
Address
Data
DDDD
UDDD UDDU
DDDU
DUUU UUDD
DDUD
DDUU DUUD
DDUU
DDUD DDUU
DUDD
DDDU DUUU
DUDU
DUDU UUUU
DUUD
UUUD UUDU
DUUU
UUUU UDDD
514 Answers to Odd-Numbered Problems
9-7.63 9-9. BFFFH; 49,151 9-11. a. 47, 212, 207, 110,
83, 122 b. 36,357
CHAP. 10.
10-3.
10 - 1 .
Address
Mnemonic
OH
LDA DH
1H
ADD EH
2H
SUB FH
3H
OUT
4H
HLT
DH
OSH
EH
04H
FH
06H
Address
Mnemonic
OH
LDA BH
1H
ADD CH
2H
SUB DH
3H
ADD EH
4H
SUB FH
5H
HLT
BH
08H
CH
04H
DH
03H
EH
05 H
FH
02H
10- 7. LDA: 1A3H or 0001 1010 0011, 2C3H or
0010 1100 0011, 3E3H or 0011 1110 0011; SUB: 1A3H
or 0001 1010 0011, 2E1H or 0010 1110 0001, 3CFH or
0011 1100 1111 10-9. a. Negative edge; CLK is on its
rising edge b. High c. Low d. High 10-11. a. Low b. Low
c. High
CHAP. 11. 11-1. Mnemonic
MVI A,64H
MVI B,96H
MVI C,C8H
HLT
11- 3.
Mnemonic
MVI A,32H
STA 4000H
MVI A,33H
STA 4001H
MVI A,34H
STA 4002H
HLT
11-5. Mnemonic
10-5.
r i T 2 r 3' T 4 T 5
MVI A,44H
MVI B,22H
ADD B
STA 5000H
HLT
11-7. a. 120 b. 119 c. Change the first instruction to MVI
C,D2H
11-9. Mnemonic
MVI A,00H
MVIB,19H
MVI C,07H
CALL F006H
STA 2000H
HLT
11-11. Label Mnemonic
IN 01H
ANI 01H
JNZ ODD
MVI A,45H
JMP DONE
ODD:
MVI A,4FH
DONE:
MVI C,08H
AGAIN:
OUT 04H
RAR
DCR C
JNZ AGAIN
HLT
Answers to Odd-Numbered Problems 515
11-13.
11-15.
11-17.
11-19.
Address
Contents
2000H
DBH
2001H
02H
2002H
E6H
2003H
01H
2004H
CAH
2005H
00H
2006H
20H
2007 H
DBH
2008H
01H
2009H
32H
200AH
00H
200BH
40H
200CH
76H
Address
Contents
2000H
0EH
2001H
23H
2002H
0DH
2003H
C2H
2004H
02H
2005H
20H
2006H
C9H
Label
Mnemonic
MVI A,05H
LOOP:
CALL F020H
DCR A
JNZ LOOP
RET
Address
Contents
E100H
3EH
E101H
05H
E102H
CDH
E103H
20 H
E104H
F0H
E105H
3DH
E106H
C2H
E107H
02H
E108H
E1H
E109H
C9H
Address
Contents
F080H
3EH
F081H
06 H
F082H
32H
F083H
93H
F084H
F0H
F085H
CDH
F086H
60H
F087H
F0H
F088H
3AH
F089H
93H
F08AH
FOH
11 - 21 .
F08BH
3DH
F08CH
32H
F08DH
93H
F08EH
FOH
F08FH
C2H
F090H
85H
F091H
FOH
F092H
C9H
Address
Contents
2000H
D3H
2001H
04H
2002H
0EH
2003H
42H
2004H
0DH
2005 H
C2H
2006H
04H
2007H
20H
2008H
2FH
2009H
00H
200AH
C3H
200BH
00 H
200CH
20H
CHAP. 12. 12-1. Mnemonic
MVI A,00H
MVI B,01H
MVI C,59H
MVI D,02H
MVI E,F1H
ADD C
ADD E
MOV L,A
MVI A,00H
ADC B
ADD D
MOV H,A
HLT
An alternative solution is
Mnemonic
MVI A,F1H
ADI 59H
MOV L,A
MVI A,02H
ACI01H
MOV H,A
HLT
12-3.
Label Mnemonic
LXI H.4FFFH
LOOP: INX H
MOV B,M
MOV A,H
516
Answers to Odd-Numbered Problems
12-5.
12-7.
ADI 40H
MOV H,A
MOV M,B
SUI 40H
MOV H,A
CPI 53H
JNZ LOOP
MOV A,L
CPI FFH
JNZ LOOP
HLT
Label Mnemonic
LXI SP.EOOOH
MVI A,00H
MVI B,FFH
LOOP: INR A
OUT 22H
CALL F010H
DCR B
JNZ LOOP
HLT
12-9.
Label Mnemonic
LXI SP,E000H
LXI H,4FFFH
LOOP: INX H
MOV A,M
MOV B,08H
AGAIN: OUT 22H
CALL F010H
RAR
DCR B
JNZ AGAIN
MOV A,L
CPI FFH
JNZ LOOP
HLT
CHAP. 14. 14-1. How you would accomplish your task
without a computer. 14-3. Branch. 14-5. The subroutine
(part of the program) needs to be written only once but can
then be used many times. 14-7. Formula tran slation.
14-9. Creating a language which would encourage pro¬
grammers to write by using what are considered “correct”
programming practices.
Label Mnemonic
LXI SP.EOOOH
LXI H,5FFFH
LOOP: INX H
MOV A,M
OUT 22H
CALL F020H
MOV A,H
CPI 61H
JNZ LOOP
MOV A,L
CPI FFH
JNZ LOOP
HLT
CHAP. 15. 15-1. By its address. 15-3. 1,048,576.
15-5. The accumulator. 15-7. Registers are faster.
15-9. The status register (or condition code register or flag
register). 15-11. The carry flag. 15-13. No. 15-15. DE.
15-17. C581. 15-19. 8 bits. 15-21. 256 bytes. 15-23.
16 bits. 15-25. Nothing. They are always set. 15-27.
None. 15-29. It is named AX and is 16 bits wide with an
8-bit upper half (called AH) and an 8-bit lower half (called
AL). 15-31. The instruction pointer. 15-33. 65,536 bytes.
CHAP. 16. 16-1. Nothing. 16-3. The original number
in the accumulator is still there. 16-5. 00. 16-7. It copies
the contents of the Y register to the accumulator. 16-9.
STY. 16-11.01. 16-13.16. 16-15. CleaR accumulator
A.
16-17.
Addr
Obj
Assembler
Comment
0000
C6
LDAB #$89
Load the number immediately following the LDAB
op code (C6) into accumulator B (89)
0001
89
0002
17
TBA
Transfer (copy) the contents of B to A
0003
3E
WAI
Stop
16-19. 76. 16-21. It copies the contents of register C to
register B. 16-23. STA aaaa [LD (aaaa),A]- 16-25.
DEBUG. 16-27. Register or memory. 16-29. DL. 16-
31. The contents of memory location 4456, 6 . 16-33. It
stands for assemble and it translates 8088/8086 mnemonics
into machine code. 16-35. It executes one instruction and
then displays the current values of all registers and stops.
Answers to Odd-Numbered Problems 517
16-37.
-a
9522:0100 mov BL,
AT
9522:dims mov CL,
BL
9522:0104
-u 1DD 1D3
9522:01DD B3S9
MOV
BL, 63
9522:0102 66D9
MOV
CL, BL
-r
ax=oooo bx=oooo
cx=cmcm
DX=0000
SP-ADDE
BP=0000
SI=0000
DI=0000
DS=9S22 £3=9522
SS=q525
CS=9522
IP=D1D 0
NV UP El
PL NZ
NA PO NC
9522:0100 B369
MOV BL,
AT
-t
AX=0000 BX=0089
cx=oaaa
DX=0000
SP—ADDE
BP=0000
si=ooao
DI=00D0
DS=9522 ES=9522
SS=^S2B
CS=9522
IP=D1D2
NV UP El
PL NZ
NA PO NC
9522:0102 flflD9
MOV CL,
BL
-t
AX=0000 BX=00fl9
CX=0069
DX=0000
SP=ADDE
BP=0000
SI=0000
DI=0000
DS=9522 ES=9522
SS=9S22
CS=9S22
NV UP El
PL NZ
NA PO NC
Note: Answers to Chapters 18 to 23 are in the teacher’s manual.
518 Answers to Odd-Numbered Problems
Index
Note: For entries marked with (#), refer also to specific families listed under “Microprocessor families.”
Absolute accuracy, 488
Absolute addressing, 265, 333-334
Access time, 132-133
Accumulator. 142, 158, 174, 176, 184, 226,
230, 232, 233, 235 (See also ALU)
Accumulator addressing, 264-268
Accuracy, 488^189
Active low state, 98
ADD instruction, 143, 148-150, 178, 197-198
Adder-subtracter, 85-87, 142, 158
Addition, 79-87, 199, 271-272, 281-282,
284-287 , 290-292 , 294, 298-300
Addition-with-carry, 274, 276-277
Address, 12, 131, 133, 135-137, 330 (See also
Addressing mode)
Address bus, 225
Address field, 145
Address line, 131
Address mapping, 183
Address state, 147 (See also T state)
#Addressing mode, 224-226
absolute, 265, 333-334
base plus index, 340
base relative plus index, 340-341
direct, 187, 264-268
extended, 266
immediate, 187, 244, 247, 264-268
implied, 188, 264-267
indexed, 332-336
indexed indirect, 335
indirect, 205, 331,333, 336, 338-340
indirect indexed, 334-335
paging, 263-264
program direct, 268
program indirect, 340
program relative, 337-338
range, 225
register (accumulator), 188, 264—268
register indirect, 336, 338-340
register relative, 337
relative, 330, 332-333, 335, 337-338
zero page, 333-334
Alphanumerics, 14
ALU, 7, 79, 175
American Standard Code for Information Ex¬
change, 14-15, 271
ANA instruction, 184
Analog interface, 485
Analog-to-digital (A/D) converter, 485, 491-
493
and gate, 22-23, 33-34, 49, 54
and instruction, 305-306, 308-310, 312-314
and operations, 65-66
and sign, 24-25
AND-OR gate, 55
and-or-invert gate, 55-57
AN I instruction, 184
#Architecture, 224-226
of SAP-1, 140-142
of SAP-2, 173-176
of SAP-3, 195-196
#Arithmetic instructions, 271-276
Arithmetic-logic unit, 7, 79, 175
ASCII code, 14-15, 271
Assembler, 181, 222, 354-355, 357, 358 (See
also Machine language)
Assembly language, 145, 221-222, 337
Associative law, 64
Asynchronous operation, 142 (See also Clock¬
ing)
B register, 142, 158, 175
Base, 6-7
Base plus index addressing, 340
Base register, 340
Base relative plus index addressing, 340-341
BASIC, 221
BCD number, 13-14, 270-271
BCD-to-decimal conversion, 13-14
Bidirectional register, 173
Binary adder, 82-83
Binary adder-subtracter, 85-87, 142, 158
Binary addition, 79-87 (See also Addition)
Binary code, 2-3
Binary digit, 4
Binary number, 2-3, 6-15, 270, 271, 274
Binary odometer, 1-2, 84
Binary programming (see Machine language)
Binary subtraction, 80-81,85-87 (See also
Subtraction)
Binary weight, 6
Binary word, 20
Binary-coded-decimal number, 13-14, 270-271
Binary-to-decimal conversion, 3, 6-7
Binary-to-decimal decoder, 27
Binary-to-hexadecimal conversion, 10-11, 12
Bipolar families, 48
Bit, 4
Bit comparison, 42
BIT instruction, 309-310, 311
Bit position, 271
Bit-serial form (see Serial data stream; Serial
loading)
Boldface notation, 42
Boolean algebra, 19, 23-27, 64-70
Boolean function generator, 58-60
Borrow, 196, 275-276, 281
#Branch instruction, 179-180, 219, 342-343
Branch-back instruction (see Return instruction)
Breakpoint, 294
Broadside loading, 110
Bubble memory, 135
Bubbled and gate, 33-34
Bubbled or gate, 36
Buffer, 54 (See also Buffer register)
Buffer register, 54, 106-107, 110, 122
Bus, 69, 122
Bus transient, 152
Bus-organized computer, 121, 122-125, 152
Byte, 6, 189-193
defined, 345, 348, 351
C language, 221
C register, 175
CALL instruction, 180, 182, 210-211
Carry flag, 196-197, 272, 274-277, 281, 312
Cell, 134
Central processing unit (see CPU)
Chip, 4, 49
Chip enable, 134
Chunking, 11
Clear, 97
Clear-start debouncer, 158-159
Clock, 93, 158
Clock generator, 102-103
Clocking:
edge-triggered, 96-100
level, 93-97, 102
master-slave, 100-103
positive and negative, 94
CM A instruction, 184
CMOS, 48
COBOL, 221
Code, binary, 2-3
Code segment register, 268
Comment, 181-182
Commutative law, 64
#Compare and test instruction, 343
Compatibility, 51-52
Complement, 19
Complement instruction, 311, 314
Complementary MOSFETs, 48
Computer, 7
architecture, 224-226
bus-organized, 121, 122-125, 152
(See also Microprocessor)
CON (see Control unit)
Condition code register, 227-228, 232-233
Conditional jump (branching), 179, 180, 187,
342-343
Contact bounce, 92-93
Content, 131, 224-225
Control input, 90
Control matrix, 36-37, 161
Control ROM, 163
Control routine, 148-152
Control unit, 7, 146-152
Controlled buffer register, 106-107
Controlled inverter, 41-42
Controlled shift register, 108-110
Controller-sequencer, 141-142, 161, 174
Conversion, 331
analog-to-digital, 485, 491-493
BCD-to-decimal, 13-14
binary-to-decimal, 6-7
binary-to-hexadecimal, 10-11,494-496
decimal-to-binary, 8
decimal-to-hexadecimal, 13
digital-to-analog, 485, 486, 489
hexadecimal-to-binary, 10-11,270
hexadecimal-to-decimal, 11-13
Core RAM, 133
Index 519
Counter:
down, 118
mod-10, 116-118
presettable, 118-120, 162
program. 113, 140, 147, 153, 173, 227,
230-232, 234, 330
programmable modulus, 120
ring, 114—116, 146-147, 159-161
ripple, 110-113
software, 181
synchronous, 113-114
TTL, 120
up-down, 118
Counter method of A/D conversion, 491-492
#CPU, 7,213 (See also ALU; Control unit)
CPU register, 195-196
Current sink, 52
Current steering, 491
D flip-flop, 96-98
D latch, 95-96
DAD instruction, 204—205
Data, 3
Data bus, 225
Data processor, 3
Data segment, 338
Data selector, 58-59
Data settling (see Bus transient;
Settling time)
#Data transfer instructions, 241-260
Date pointer, 205
De Morgan’s theorem, 33-37, 66
Debouncer, 92-93, 158-159
DEBUG, 253, 255-260, 293-302, 337-340
Decade counter, 118, 120
Decimal addition, 284-285, 290-292, 298-300
Decimal adjust, 280, 284-285, 290, 298
Decimal flag, 279-281
Decimal number, 84—85
Decimal odometer, 1
Decimal weight, 6
Decimal-to-binary conversion, 8, 21-22
Decimal-to-hexadecimal conversion, 13
Decision-making element, 25
Decoder:
binary-to-decimal, 27
binary-to-hexadecimal, 54
decimal-to-BCD, 54
instruction, 125,. 158-159
seven-segment, 54
#Decrement instruction, 178, 180-181,200,
205, 343
Define byte, 345, 348, 351
Delay, 189-190
Digit, 1
Digital-to-analog (D/A) converter, 485, 486-489
Diode ROM, 130-131
Diode-transistor logic, 48
Direct addressing, 187, 264—268
Direct reset, 97
Direct set, 97
Disassembler, 222
Distributive law, 65
Division. 276, 302
Don’t care condition, 75-77, 95
Do-nothing state (see NOP instruction)
Double-byte addition, 199
Double-byte subtraction, 202
Double-dabble, 8
Double inversion, 34, 66
Double-precision number, 274
Down counter, 118
Driver, 54
DTL, 48
Duality theorem, 66-67
Dynamic RAM, 133-134
ECL, 48
Edge triggering, 96-100
Effective address, 330
8080/8085/Z80 family, 214, 417-422, 502-506
addressing, 266-267, 336, 409
architecture, 233-235, 329
arithmetic instructions, 286-287, 292-
293,391-395, 411-412, 416
conditional jump (branch)
instructions, 351-352, 402, 413-414,
417
CPU control instructions, 381,410, 415
data transfer instructions, 249-253, 381-
390, 410-411,415-416
flag instructions, 287-292, 390-391,408-
409,411,416
increment and decrement instructions,
398-400, 413, 416-417
input-output instructions, 408, 415, 417
interrupt instructions, 407-408, 415, 417
logical instructions, 395-398, 412, 416
programming, 511
rotate and shift instructions, 323-324,
398,412-413,416
stack instructions, 406-407, 415, 417
subroutine instructions, 370-373, 402-
406,414-415,417
test and compare instructions, 352, 401,
413.417
unconditional jump instructions, 350-351,
400.413.417
8086/8088 family, 214, 469-470
addressing, 267-269, 336-341
architecture, 235-237, 329
arithmetic instructions, 293-294, 300-
302, 447-450, 466
conditional jump (branch) instructions,
357-358, 456-459, 467
CPU control instructions, 445, 465
data transfer instructions, 253-260, 445-
446, 466
flag instructions, 294—299, 446-447, 466
increment and decrement instructions,
455, 467
input-output instructions, 462-463, 468
interrupt instructions, 461-462, 468
logical instructions, 314-317, 450-451,466
loop instructions, 464—465, 468
programming, 511
rotate and shift instructions, 324-327,
451-455, 467
stack instructions, 460-461,468
string instructions, 463-464, 468
subroutine instructions, 373-377, 459-
460, 468
test and compare instructions, 358, 456,467
unconditional jump instructions, 355-357,
455,467
Emitter-coupled logic, 48
ENABLE input, 23
Encoder, 21-22, 54
End-of-conversion signal, 492
Erasable PROM (EPROM), 132, 224
Even parity, 39, 234
exclusive-NOR gate, 42
exclusive-OR gate, 37-42, 307-309
Execution cycle, 148-152
Expandable gate, 56-57
Expander gate, 56-57
Extended addressing, 266
Extended register, 204—205
Factoring, 69, 70
Fanout, 52-53
Fetch cycle, 148, 150, 151, 227
Fetch microroutine, 152, 161
Firmware, 243, 247, 251
First-in-last-out (FILO) structure, 228, 363
#Flag instructions, 175, 175, 179, 180-181,
187, 227-228, 272-276, 310
Flip-flop, 90-103
Floating TTL input, 50-51
Flowchart, 217, 218-220
FORTH, 221
FORTRAN, 221
Full adder, 81-82
Function tables, 499—500
Fundamental product, 67
Gate:
and, 22-23, 33-34, 49,54
AND-OR, 55
and-or-invert, 55-57
expandable, 56-57
nand, 34-36, 49, 53-55, 118-120
nor, 32-34, 49, 53-54
not, 19-20
OR, 20-22, 36,54
standard TTL, 49
XNOR, 42
xor, 37-42, 49
General-purpose register, 227, 230, 232-236
Half-adder, 81
Half-carry flag, 272
Halt instruction, 143, 151, 185, 241
Hand*assembly, 178, 183, 244, 248, 251
Handshaking, 176, 186
Hardware, 3-4, 213
Hardwired control, 161
Hex inverter, 20
Hexadecimal address, 133, 136-137
Hexadecimal number, 9-13, 14, 270
Hexadecimal-to-binary conversion, 10-11,270
Hexadecimal-to-decimal conversion. 11-13
Hex-dabble, 13
High-level language, 221
High-speed TTL, 50
Hold time, 98
Immediate addressing, 187, 244, 247, 264-268
Immediate instruction, 176, 184, 201-202,
204, 206
Implied addressing, 188, 264—267
IN instruction, 185
Inactive state, 90
inclusive or (see or gate)
#Increment instruction, 147, 178, 180-181,
199-200, 205, 343
Index register, 227, 231, 232, 234, 236, 332, 340
Indexed addressing, 332, 333-336
Indexed indirect addressing, 335
Indirect addressing, 205, 331, 333, 336, 340
Indirect indexed addressing, 334-335
Indirect instruction, 205-207
Inherent addressing, 264-267
Input gate lead, 69
Input-output unit, 7
Input register, 173
Input unit, 7
Instruction cycle, 151 (See also
Machine cycle)
Instruction decoder, 125, 158-159
Instruction field, 145
Instruction pointer, 205, 236, 330
Instruction register, 125, 141, 153, 174
520 Index
Instruction set, 142-144, 240
Integrated circuit, 4, 48
Interface circuit (see Analog interface)
Inversion:
bubble, 19-20
double, 34, 66
sign, 19, 23-24
symbol, 19-20
Inverter, 19-20, 41-42
I/O unit, 7
Italic notation, 25
JK flip-flop, 99-103
JK master-slave flip-flop, 100-103
Jump flag, 187
#Jump instruction, 173, 179-180, 182, 183,
202-204, 342-343
K- (kilo-), 7
K input, 99-100
Karnaugh maps, 70-77
Label, 181-182
Ladder, 490-491
Large-scale integration, 48
Latch, 90-96
LDA instruction, 142, 148, 149, 176
LDA microroutine, 161-162
LED display, 3
Level clocking, 93-97, 102
Light-emitting diode, 3
Load the accumulator instruction, 142, 148,
149, 176, 242-248, 252-253
Loading:
parallel, 110
serial, 108-110
TTL device, 52-53
Logic circuit, 19, 68
#Logical instructions, 305-308
Loop, 181, 218-219, 342-344
Loop counter, 181
Low-level language, 221
Low-power Schottky TTL, 50, 52-53
Low-power TTL, 50
LSB (least significant byte), 274, 488
LSI, 48
Machine cycle:
definition, 151
fixed, 161-162, 163
variable, 163-164
Machine language, 145, 146, 220, 221, 337
Machine phase (see T state)
Macroinstruction, 152-153
Magnetic core, 5
Magnetic tape, 5
Manual assembly, 221
Manual-auto debouncer, 158-159
Mapping (see Address mapping)
MAR, 140, 153, 174
Mask, 131, 186, 306-308
Master-slave flip-flop, 100-103
Medium-scale integration, 48
Memory, 5-7, 130-137, 224, 268
Memory address register, 140, 153, 174
Memory data register, 174
Memory element, 90-103
Memory enable (see Chip enable; Write enable)
Memory-intensive architecture, 329
Memory location, 10-12, 331, 507-510
Memory-reference instruction, 143-144, 176—
177
Memory register (see Memory location)
Memory state, 147
Microcode (see Microprogram)
Microcomputer, 7
Microcontroller, 161-164
Microinstruction, 152
Microprocessor, 7, 213-216, 226-237, 270-
271
Microprocessor families (see 8080/8085/Z80
family; 8086/8088 family; 6502 fam¬
ily; 6800/6808 family)
Microprogram, 152-153, 161-164
Microroutine (see Microprogram)
Mnemonic, 143, 221
Modulus, 116-120
Monitor, 174, 241
assembly, 222
Monotonic D/A converter, 489
MOS families, 48
Move instruction, 177-178, 195-196, 199, 206
MRI, 143-144, 176
MSB (most significant bit), 200, 273, 274, 492
MSI, 48
Multiplexer, 58-60, 153
Multiplication, 182, 183, 276, 300-302
MVI, 189, 195-196, 199
nand gate, 34-36, 49, 53-55, 118-120
NAND latch, 92-95
Natural modulus, 120
n-channel MOSFETs, 48
neg instruction, 308, 311-312, 316-317
Negative (sign) flag, 275, 277-278, 282-283
Negative clocking, 94
Negative logic, 25
Negative toggle, 118
Nesting, 343-344
loop, 343-344
subroutine, 189-190, 364, 367, 369-371,
373-374
Nibble, 13-14
NMOS, 48
No operation instruction, 241, 242, 245, 249
Noise margin, 52
Noninverter, 20
Non saturated circuit, 4-5
Nonvolatile memory, 133
NOP instruction, 148, 185, 241, 242
nor gate, 32-34, 49, 53-54
nor latch, 91, 92
not gate, 19-20
not instruction, 308, 315-316
Notation:
boldface, 42
italic, 25
positional, 11-12
roman, 25
Number:
binary, 2, 3, 6-15, 270, 271,274
binary-coded-decimal, 13-14, 270-271
decimal, 1, 84-85
hexadecimal, 9-13, 14, 270
(See also Conversion)
Object code, 221
Object program, 145
Octet, 72, 73
Odd parity, 39, 234
Odd-parity generator, 40
Odd-parity tester, 39
Odometer, 330
binary, 1-2, 84
decimal, 1
hexadecimal, 9
Offset, 332
On-chip decoding, 131, 132
1 ’s complement, 41-42, 312
Open-collector gate, 58
Operand, 145, 176
Operation code, 144, 176-177, 241
Operational amplifier (op amp), 485^-86
or gate, 20-22, 36, 54
OR instruction, 65, 66, 184, 306-307, 309,
310, 313, 314-315
or sign, 24
OUT instruction, 143, 150-151, 185
Output buffer, 493
Output register, 7, 106-107, 110, 142, 158,
176
Overflow, 87. 196, 272-274, 279, 284, 288-
289, 296-297
Overlapping, 74
Paging, 263-264
Pair, 72 I
Parallel loading, 110 j
Parameter passing, 183
Parity, 39, 234
Parity flag, 203, 288-289, 296
Parity generator, 39-40
Pascal, 221
PC, 113. 140, 147, 153
p-channel MOSFETs, 48
Phase (see T state)
Pinouts, 499-500
PMOS, 48
Pointer, 140, 205, 227
POP instruction, 209-210
Port instruction, 185-186
Positional notation, 11-12
Positive clocking, 94
Positive logic, 25
Positive toggle, 118
Power dissipation, 49
Power of 2, 7
Power supply, 158
Preset, 97
Presettable counter, 118-120, 162
Prime memory (see Dynamic RAM; Static
RAM)
Program, 3, 216
Program counter, 113, 140, 147, 153, 173,
227, 230-232, 234, 330
Program direct addressing, 268
Program indirect addressing, 340
Program relative addressing, 337-338
Program status word, 208
Programmable modulus, 120
Programmable ROM (PROM), 131-132, 224
Programmed multiplication, 182, 183
#Programming, 135-136, 216-222
data transfer instructions, 241-260
models, 511
PROM, 131-132, 224
Propagation delay time, 49, 98
Punched cards, 5
PUSH instruction, 208-209 (See also Stack)
Pushing and popping registers, 366, 367-368,
370, 371, 374
Quad, 72-73
Race condition, 91,94, 95, 100
Radix, 6-7
RAL instruction, 185, 200, 201
Random-access memory (RAM), 133—137,
153, 224
RAR instruction, 185, 200, 201
Read-only memory (ROM), 130-133, 161-
164, 224
Index 521
Redundant Karnaugh group, 74-75
Refresh, 133-134
Register, 4, 217
bidirectional, 173
buffer, 54, 106-107, 110, 122
controlled, 106-110
CPU, 195-196
8-bit, 229-230
input, 173
output, 7, 106-107, 110, 142, 158, 176
pair, 204
shift, 108-110
shift-left, 108, 109
shift-right, 108, 109
16-bit, 230
three-state, 121-122
transfers, 122-123
width of, 229-230
(See also specific types of register)
Register addressing, 188, 264-268
Register indirect addressing, 336, 338-340
Register-intensive architecture, 329
Register parameter passing, 183
Register relative addressing, 337
Relative accuracy, 488-489
Relative addressing, 330, 332-333, 335, 337-338
Reset-and-carry, 1
Resolution, 488
Return instruction, 180, 210-211, 364—366
Ring counter, 114—116, 146-147, 159-161
Ripple counter, 110-113
Rolling, Karnaugh map, 74
ROM (see Read-only memory)
Roman notation, 25
#Rotate instruction, 185, 200, 319-321
RS latch, 90-94
SAP-1, 140-164
counters, 106, 107, 113, 116, 117
parts list, 501
RAM, 115-116
SAP-2, 144, 151, 173-193
SAP-3, 144, 195-212
Saturated circuit, 4
Saturation delay time, 4, 50
Schmitt trigger, 54-55
Schottky TTL, 50, 52-53
Segment register, 236
Serial data stream, 191-193
Serial loading, 108-110
Settling time, 489
Setup time, 98
Seven-segment decoder, 54
#Shift instruction, 319, 320
Shift register, 108-110
SHL control, 108-110
Sign bit, 83
Sign flag, 175, 179, 180-181, 287, 294-296
Signed binary number, 83, 272, 284, 289
Sign-magnitude number, 83
Single-precision number, 274
Single-step debouncer, 158-159
Sink, 52
6502 family, 214,481-483
addressing, 265, 332-335, 476, 477
architecture, 230-231, 329
arithmetic instructions, 276-277, 472,
478, 480-481
conditional jump (branch) instructions,
345-346, 475, 479-480, 481
CPU control instructions, 242, 471, 478,
480
data transfer instructions, 242-245, 471—
472, 478, 480
6502 family (Cont.)\
flag instructions, 277-281,472, 476-478,
480
increment and decrement instructions,
473-474, 479, 481
input-output instructions, 476, 480, 481
interrupt instructions, 476, 480, 481
logical instructions, 308-310, 472-473,
478-479, 481
programming, 511
rotate and shift instructions, 321-322,
473, 479, 481
stack instructions, 475-476, 480, 481
subroutine instructions, 366-369, 475,
480,481
test and compare instructions, 346, 474,
479, 481
unconditional jump instructions, 344, 474,
479, 481
6800/6808 family, 214, 434-437, 443, 444
addressing, 265-266, 335-336, 433
architecture, 329, 632-633
arithmetic instructions, 281-282, 285-
286, 424-425 , 438 , 441
conditional jump (branch)
instructions, 348-349, 429-431, 440,
442
CPU control instructions, 422, 437, 441
data transfer instructions, 245-249, 423,
437, 441
flag instructions, 282-285, 423^424, 433,
437- 438, 441
increment and decrement instructions,
428, 439, 442
input-output instructions, 432, 441, 442
interrupt instructions, 432, 441,442
logical instructions, 310-314, 425-426,
438- 439, 441-442
programming, 511
rotate and shift instructions, 322-323,
426-427, 439, 442
stack instructions, 431-432, 440-441, 442
subroutine instructions, 369-370, 431,
440, 442
test and compare instructions, 349, 428-
429, 439, 442
unconditional jump instructions, 347-348,
428, 439, 442
Small-scale integration, 48
Software, 3-4, 218
Software emulation program, 215
Source, 52
Source code, 221
Source program, 145
SSI, 48
#Stack, 195, 207-211, 228-229, 231, 233,
234, 236, 363-364
Stack pointer, 195, 207-208, 228-229, 231,
233, 234, 236, 363-364, 366-367,
369, 371, 373
Stack segment, 338
Standard TTL, 49-52
State diagram, 117
Static RAM, 133-134
Status register, 227-228, 231-234, 236
Store the accumulator, 176
Straight-line program, 218
String, 1
#Subroutine, 180, 219, 363-377
branching vs., 364
nested, 189-190, 364, 367, 369-371,
373-374
pushing and popping registers, 366, 367-
368, 370, 371, 374
# Subroutine (Cont.):
return instruction, 180, 210-211, 364-366
stack and stack pointer, 363-364, 366-
367, 369, 371, 373
Subtract instruction, 143, 150, 178, 198-199
Subtraction, 80-81, 86-87, 202, 275, 285—286,
292-293, 300
Subtraction-with-carry (borrow), 196, 275-276,
281
Successive-approximation method, 492-493
Sum-of-products circuit, 67-68
Switch, current, 487^188
Switch debouncer, 92-93
Synchronous counter, 113-114
T state, 146-151, 187
Temporary register, 175
Three-state RAM, 134
Three-state register, 121-122
Three-state switch, 121
Time delay, 189-190
Timing diagram, 91, 92, 94, 95
Timing signal, 36, 116
Timing state, 146-151
Toggle, 99-100, 102, 118
Totem-pole output, 49
Trace command, 293
Traffic light, 190-191
Trainer, microprocessor, 215
Transistor, 4
inverter, 19
latch, 90-91
register, 4
Transistor-transistor logic, 48-63
Transparent latch, 95
Triple-precision number, 274
Tristate switch, 111-112
Truth table, 20, 21
deriving logic circuit from, 68
JK master-slave, 102
Karnaugh maps from, 70-77
transistor latch, 90-91, 94
TTL, 48-63, 120, 135-136, 497-498
2’s complement, 83-87, 312, 331
Two-state design, 4—6
#Unconditional jump, 179, 180, 342
Universal logic circuit, 60
Unsigned binary number, 272, 284, 289-290
Up-down counter, 118
Virtual ground point, 485
Volatile RAM, 134
Weight:
binary, 6
decimal, 6
hexadecimal, 11-12
Weighted resistors, 489
Word, 20, 208
Word comparator, 42-43
Word multiplexer, 60
Worksheet, 222
Worst-case TTL characteristics, 50-51
Write enable, 134
xnor gate, 42
xor gate, 37-42, 49
xor instruction, 313, 315
XRA instruction, 184
XRI instruction, 184
Zero flag, 175, 179, 180-181, 275, 278-279,
283-284, 287-289, 296, 332
Zero page addressing, 333-334
522 Index
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